Merge with /home/sr/git/u-boot
This commit is contained in:
Wolfgang Denk
@@ -731,6 +731,8 @@
|
||||
#define PVR_440GX_RC 0x51B21892
|
||||
#define PVR_440GX_RF 0x51B21894
|
||||
#define PVR_405EP_RB 0x51210950
|
||||
#define PVR_440SP_RA 0x53221850
|
||||
#define PVR_440SP_RB 0x53221891
|
||||
#define PVR_601 0x00010000
|
||||
#define PVR_602 0x00050000
|
||||
#define PVR_603 0x00030000
|
||||
|
||||
@@ -1,464 +0,0 @@
|
||||
/*
|
||||
* Copyright 2005 DENX Software Engineering
|
||||
* Wolfgang Denk <wd@denx.de>
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||||
* Copyright 2004 Freescale Semiconductor.
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||||
* (C) Copyright 2002,2003 Motorola,Inc.
|
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* TQM8540 board configuration file
|
||||
*
|
||||
* Make sure you change the MAC address and other network params first,
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||||
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
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||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
|
||||
#define CONFIG_MPC8540 1 /* MPC8540 specific */
|
||||
#define CONFIG_TQM8540 1 /* TQM8540 board specific */
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */
|
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
|
||||
|
||||
/*
|
||||
* sysclk for MPC85xx
|
||||
*
|
||||
* Two valid values are:
|
||||
* 33000000
|
||||
* 66000000
|
||||
*
|
||||
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
|
||||
* is likely the desired value here, so that is now the default.
|
||||
* The board, however, can run at 66MHz. In any event, this value
|
||||
* must match the settings of some switches. Details can be found
|
||||
* in the README.mpc85xxads.
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||||
*/
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
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||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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||||
|
||||
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
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||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
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||||
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
|
||||
#define CFG_MEMTEST_END 0x10000000
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
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||||
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
|
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||
|
||||
/*
|
||||
* DDR Setup
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||||
*/
|
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
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||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
/*
|
||||
* Determine DDR configuration from I2C interface.
|
||||
*/
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
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||||
|
||||
#else
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
*/
|
||||
#define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
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||||
#define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
|
||||
#define CFG_DDR_CS0_CONFIG 0x80000102
|
||||
#define CFG_DDR_TIMING_1 0x47445331
|
||||
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
|
||||
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
|
||||
#define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
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||||
#define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
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||||
#endif
|
||||
|
||||
/*
|
||||
* Flash on the Local Bus
|
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*/
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||||
#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
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||||
#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
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||||
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#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
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||||
#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
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||||
|
||||
#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
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||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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||||
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
|
||||
#undef CFG_FLASH_CHECKSUM
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||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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||||
#define CFG_RAMBOOT
|
||||
#else
|
||||
#undef CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_EMPTY_INFO
|
||||
|
||||
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
|
||||
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
|
||||
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
|
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
|
||||
|
||||
/*
|
||||
* LSDMR masks
|
||||
*/
|
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
|
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
|
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
|
||||
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
|
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
|
||||
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
|
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
|
||||
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
|
||||
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
|
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
|
||||
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
|
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
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||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
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||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
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||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
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||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
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||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
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||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
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||||
|
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
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||||
| CFG_LBC_LSDMR_RFCR5 \
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||||
| CFG_LBC_LSDMR_PRETOACT3 \
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||||
| CFG_LBC_LSDMR_ACTTORW3 \
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||||
| CFG_LBC_LSDMR_BL8 \
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||||
| CFG_LBC_LSDMR_WRC2 \
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||||
| CFG_LBC_LSDMR_CL3 \
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||||
| CFG_LBC_LSDMR_RFEN \
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)
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||||
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||||
/*
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||||
* SDRAM Controller configuration sequence.
|
||||
*/
|
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
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||||
| CFG_LBC_LSDMR_OP_PCHALL)
|
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
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||||
| CFG_LBC_LSDMR_OP_ARFRSH)
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||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
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||||
| CFG_LBC_LSDMR_OP_ARFRSH)
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||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
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||||
| CFG_LBC_LSDMR_OP_MRW)
|
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
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||||
| CFG_LBC_LSDMR_OP_NORMAL)
|
||||
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CFG_INIT_RAM_LOCK 1
|
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CFG_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
|
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CFG_HUSH_PARSER
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/* I2C EEPROM */
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
|
||||
|
||||
/* I2C SYSMON (LM75) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CFG_DTT_MAX_TEMP 70
|
||||
#define CFG_DTT_LOW_TEMP -30
|
||||
#define CFG_DTT_HYSTERESIS 3
|
||||
|
||||
/* RapidIO MMU */
|
||||
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
|
||||
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
|
||||
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_MPC85XX_TSEC1 1
|
||||
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_MPC85XX_TSEC2 1
|
||||
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
|
||||
#define CONFIG_MPC85XX_FEC 1
|
||||
#define CONFIG_MPC85XX_FEC_NAME "FEC"
|
||||
#define FEC_PHY_ADDR 3
|
||||
#define FEC_PHYIDX 0
|
||||
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
|
||||
/* Options are TSEC[0-1], FEC */
|
||||
#define CONFIG_ETHPRIME "TSEC1"
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#else
|
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
#if defined(CFG_RAMBOOT)
|
||||
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
|
||||
#else
|
||||
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP )
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
# define ADD_PCI_CMD (CFG_CMD_PCI)
|
||||
#else
|
||||
# define ADD_PCI_CMD 0
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
|
||||
ADD_PCI_CMD | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING )
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CFG_DCACHE_SIZE 32768
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consdev=ttyS0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $bootargs " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
|
||||
":$hostname:$netdev:off panic=1\0" \
|
||||
"addcons=setenv bootargs $bootargs " \
|
||||
"console=$consdev,$baudrate\0" \
|
||||
"flash_nfs=run nfsargs addip addcons;" \
|
||||
"bootm $kernel_addr\0" \
|
||||
"flash_self=run ramargs addip addcons;" \
|
||||
"bootm $kernel_addr $ramdisk_addr\0" \
|
||||
"net_nfs=tftp $loadaddr $bootfile;" \
|
||||
"run nfsargs addip addcons;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_85xx\0" \
|
||||
"bootfile=/tftpboot/tqm8540/uImage\0" \
|
||||
"kernel_addr=FE000000\0" \
|
||||
"ramdisk_addr=FE100000\0" \
|
||||
"load=tftp 100000 /tftpboot/tqm8540/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,473 +0,0 @@
|
||||
/*
|
||||
* Copyright 2005 DENX Software Engineering
|
||||
* Wolfgang Denk <wd@denx.de>
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2002,2003 Motorola,Inc.
|
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* TQM8560 board configuration file
|
||||
*
|
||||
* Make sure you change the MAC address and other network params first,
|
||||
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
|
||||
#define CONFIG_CPM2 1 /* has CPM2 */
|
||||
#define CONFIG_MPC8560 1 /* MPC8560 specific */
|
||||
#define CONFIG_TQM8560 1 /* TQM8560 board specific */
|
||||
|
||||
/*
|
||||
* BIG FAT WARNING: Right now PCI seems to have a problem on the
|
||||
* TQM8560 on the Starter Kit. So, if the board doen't come up
|
||||
* please disable the PCI support for now. sr@denx.de, 15-09-2005
|
||||
*/
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */
|
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
|
||||
|
||||
/*
|
||||
* sysclk for MPC85xx
|
||||
*
|
||||
* Two valid values are:
|
||||
* 33000000
|
||||
* 66000000
|
||||
*
|
||||
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
|
||||
* is likely the desired value here, so that is now the default.
|
||||
* The board, however, can run at 66MHz. In any event, this value
|
||||
* must match the settings of some switches. Details can be found
|
||||
* in the README.mpc85xxads.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
|
||||
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
|
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
|
||||
#define CFG_MEMTEST_END 0x10000000
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
|
||||
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
|
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
/*
|
||||
* Determine DDR configuration from I2C interface.
|
||||
*/
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
|
||||
|
||||
#else
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
*/
|
||||
#define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
|
||||
#define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
|
||||
#define CFG_DDR_CS0_CONFIG 0x80000102
|
||||
#define CFG_DDR_TIMING_1 0x47445331
|
||||
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
|
||||
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
|
||||
#define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
|
||||
#define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Flash on the Local Bus
|
||||
*/
|
||||
#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
|
||||
#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
|
||||
|
||||
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
|
||||
#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
|
||||
|
||||
#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
#define CFG_RAMBOOT
|
||||
#else
|
||||
#undef CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_EMPTY_INFO
|
||||
|
||||
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
|
||||
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
|
||||
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
|
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
|
||||
|
||||
/*
|
||||
* LSDMR masks
|
||||
*/
|
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
|
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
|
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
|
||||
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
|
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
|
||||
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
|
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
|
||||
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
|
||||
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
|
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
|
||||
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
|
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
|
||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
|
||||
|
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
|
||||
| CFG_LBC_LSDMR_RFCR5 \
|
||||
| CFG_LBC_LSDMR_PRETOACT3 \
|
||||
| CFG_LBC_LSDMR_ACTTORW3 \
|
||||
| CFG_LBC_LSDMR_BL8 \
|
||||
| CFG_LBC_LSDMR_WRC2 \
|
||||
| CFG_LBC_LSDMR_CL3 \
|
||||
| CFG_LBC_LSDMR_RFEN \
|
||||
)
|
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence.
|
||||
*/
|
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_PCHALL)
|
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_ARFRSH)
|
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_ARFRSH)
|
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_MRW)
|
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_NORMAL)
|
||||
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CFG_INIT_RAM_LOCK 1
|
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else */
|
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CFG_HUSH_PARSER
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/* I2C EEPROM */
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
|
||||
|
||||
/* I2C SYSMON (LM75) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CFG_DTT_MAX_TEMP 70
|
||||
#define CFG_DTT_LOW_TEMP -30
|
||||
#define CFG_DTT_HYSTERESIS 3
|
||||
|
||||
/* RapidIO MMU */
|
||||
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
|
||||
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
|
||||
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_MPC85XX_TSEC1 1
|
||||
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_MPC85XX_TSEC2 1
|
||||
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
|
||||
#define CONFIG_MPC85XX_FEC 1
|
||||
#define CONFIG_MPC85XX_FEC_NAME "FEC"
|
||||
#define FEC_PHY_ADDR 3
|
||||
#define FEC_PHYIDX 0
|
||||
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
|
||||
/* Options are TSEC[0-1], FEC */
|
||||
#define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
#define CONFIG_ETHER_ON_FCC
|
||||
#define CONFIG_ETHER_ON_FCC3
|
||||
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
|
||||
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#else
|
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
#if defined(CFG_RAMBOOT)
|
||||
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
|
||||
#else
|
||||
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP )
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
# define ADD_PCI_CMD (CFG_CMD_PCI)
|
||||
#else
|
||||
# define ADD_PCI_CMD 0
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
|
||||
ADD_PCI_CMD | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING )
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CFG_DCACHE_SIZE 32768
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consdev=ttyS0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $bootargs " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
|
||||
":$hostname:$netdev:off panic=1\0" \
|
||||
"addcons=setenv bootargs $bootargs " \
|
||||
"console=$consdev,$baudrate\0" \
|
||||
"flash_nfs=run nfsargs addip addcons;" \
|
||||
"bootm $kernel_addr\0" \
|
||||
"flash_self=run ramargs addip addcons;" \
|
||||
"bootm $kernel_addr $ramdisk_addr\0" \
|
||||
"net_nfs=tftp $loadaddr $bootfile;" \
|
||||
"run nfsargs addip addcons;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_85xx\0" \
|
||||
"bootfile=/tftpboot/tqm8560/uImage\0" \
|
||||
"kernel_addr=FE000000\0" \
|
||||
"ramdisk_addr=FE100000\0" \
|
||||
"load=tftp 100000 /tftpboot/tqm8560/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
452
include/configs/TQM85xx.h
Normal file
452
include/configs/TQM85xx.h
Normal file
@@ -0,0 +1,452 @@
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Wolfgang Denk <wd@denx.de>
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2002,2003 Motorola,Inc.
|
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* TQM85xx (8560/40/55/41) board configuration file
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
|
||||
/*
|
||||
* Only MPC8540 doesn't have CPM module
|
||||
*/
|
||||
#ifndef CONFIG_MPC8540
|
||||
#define CONFIG_CPM2 1 /* has CPM2 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* sysclk for MPC85xx
|
||||
*
|
||||
* Two valid values are:
|
||||
* 33000000
|
||||
* 66000000
|
||||
*
|
||||
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
|
||||
* is likely the desired value here, so that is now the default.
|
||||
* The board, however, can run at 66MHz. In any event, this value
|
||||
* must match the settings of some switches. Details can be found
|
||||
* in the README.mpc85xxads.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
||||
|
||||
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
|
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
#define CFG_MEMTEST_START 0x00000000
|
||||
#define CFG_MEMTEST_END 0x10000000
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
|
||||
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
|
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
|
||||
#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
|
||||
|
||||
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
|
||||
/* TQM8540 & 8560 need DLL-override */
|
||||
#define CONFIG_DDR_DLL /* DLL fix needed */
|
||||
#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
|
||||
#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
|
||||
|
||||
#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
|
||||
#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
|
||||
#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
|
||||
|
||||
/*
|
||||
* Flash on the Local Bus
|
||||
*/
|
||||
#define CFG_FLASH0 0xFC000000
|
||||
#define CFG_FLASH1 0xF8000000
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
|
||||
|
||||
#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
|
||||
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
|
||||
|
||||
#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
|
||||
#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
|
||||
#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
|
||||
#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
|
||||
|
||||
#define CFG_FLASH_CFI /* flash is CFI compat. */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
|
||||
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
|
||||
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
|
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
|
||||
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CFG_INIT_RAM_LOCK 1
|
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#if defined(CONFIG_TQM8560)
|
||||
|
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else */
|
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
|
||||
|
||||
#else
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CFG_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
|
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
|
||||
|
||||
#endif /* CONFIG_TQM8560 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CFG_HUSH_PARSER
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/* I2C EEPROM */
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
|
||||
|
||||
/* I2C SYSMON (LM75) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CFG_DTT_MAX_TEMP 70
|
||||
#define CFG_DTT_LOW_TEMP -30
|
||||
#define CFG_DTT_HYSTERESIS 3
|
||||
|
||||
/* RapidIO MMU */
|
||||
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
|
||||
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
|
||||
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_MPC85XX_TSEC1 1
|
||||
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_MPC85XX_TSEC2 1
|
||||
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define FEC_PHY_ADDR 3
|
||||
#define FEC_PHYIDX 0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
|
||||
/* Options are TSEC[0-1], FEC */
|
||||
#define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
#if defined(CONFIG_TQM8540)
|
||||
/*
|
||||
* TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
|
||||
* The FEC port is connected on the same signals as the FCC3 port
|
||||
* of the TQM8560 to the baseboard (STK85xx Starterkit).
|
||||
*
|
||||
* On the STK85xx Starterkit the X47/X50 jumper has to be set to
|
||||
* a - d (X50.2 - 3) to enable the FEC port.
|
||||
*/
|
||||
#define CONFIG_MPC85XX_FEC 1
|
||||
#define CONFIG_MPC85XX_FEC_NAME "FEC"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
|
||||
/*
|
||||
* TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
|
||||
* can be used at once, since only one FCC port is available on the STK85xx
|
||||
* Starterkit.
|
||||
*
|
||||
* To use this port you have to configure U-Boot to use the FCC port 1...2
|
||||
* and set the X47/X50 jumper to:
|
||||
* FCC1: a - b (X47.2 - X50.2)
|
||||
* FCC2: a - c (X50.2 - 1)
|
||||
*/
|
||||
#define CONFIG_ETHER_ON_FCC
|
||||
#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TQM8560)
|
||||
/*
|
||||
* TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
|
||||
* can be used at once, since only one FCC port is available on the STK85xx
|
||||
* Starterkit.
|
||||
*
|
||||
* To use this port you have to configure U-Boot to use the FCC port 1...3
|
||||
* and set the X47/X50 jumper to:
|
||||
* FCC1: a - b (X47.2 - X50.2)
|
||||
* FCC2: a - c (X50.2 - 1)
|
||||
* FCC3: a - d (X50.2 - 3)
|
||||
*/
|
||||
#define CONFIG_ETHER_ON_FCC
|
||||
#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
|
||||
#define CONFIG_ETHER_ON_FCC1
|
||||
#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
|
||||
#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
|
||||
#define CONFIG_ETHER_ON_FCC2
|
||||
#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
|
||||
#define CONFIG_ETHER_ON_FCC3
|
||||
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
|
||||
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with ts */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
# define ADD_PCI_CMD (CFG_CMD_PCI)
|
||||
#else
|
||||
# define ADD_PCI_CMD 0
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP | \
|
||||
ADD_PCI_CMD | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING )
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CFG_DCACHE_SIZE 32768
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CFG_BOOTFILE \
|
||||
"netdev=eth0\0" \
|
||||
"consdev=ttyS0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $bootargs " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
|
||||
":$hostname:$netdev:off panic=1\0" \
|
||||
"addcons=setenv bootargs $bootargs " \
|
||||
"console=$consdev,$baudrate\0" \
|
||||
"flash_nfs=run nfsargs addip addcons;" \
|
||||
"bootm $kernel_addr\0" \
|
||||
"flash_self=run ramargs addip addcons;" \
|
||||
"bootm $kernel_addr $ramdisk_addr\0" \
|
||||
"net_nfs=tftp $loadaddr $bootfile;" \
|
||||
"run nfsargs addip addcons;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_85xx\0" \
|
||||
"kernel_addr=FE000000\0" \
|
||||
"ramdisk_addr=FE100000\0" \
|
||||
"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -73,7 +73,7 @@
|
||||
* Initial RAM & stack pointer (placed in SDRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
|
||||
#define CFG_INIT_RAM_END (8 << 10)
|
||||
#define CFG_INIT_RAM_END (4 << 10)
|
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
306
include/configs/luan.h
Normal file
306
include/configs/luan.h
Normal file
@@ -0,0 +1,306 @@
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
* John Otken, jotken@softadvances.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* luan.h - configuration for LUAN board
|
||||
***********************************************************************/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_LUAN 1 /* Board is Luan */
|
||||
#define CONFIG_440SP 1 /* Specific PPC440SP support */
|
||||
#define CONFIG_4xx 1 /* PPC4xx family */
|
||||
#define CONFIG_440 1
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
|
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
|
||||
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* MUST be zero */
|
||||
|
||||
#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
|
||||
#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
|
||||
#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
|
||||
#define CFG_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
|
||||
|
||||
#define CFG_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
|
||||
|
||||
#define CFG_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */
|
||||
|
||||
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
|
||||
|
||||
#if CFG_LARGE_FLASH == 0xffc00000
|
||||
#define CFG_FLASH_BASE CFG_LARGE_FLASH
|
||||
#else
|
||||
#define CFG_FLASH_BASE CFG_SMALL_FLASH
|
||||
#endif
|
||||
|
||||
#undef CFG_DRAM_TEST
|
||||
#if CFG_SRAM_BASE
|
||||
#define CFG_KBYTES_SDRAM 1024*2
|
||||
#else
|
||||
#define CFG_KBYTES_SDRAM 1024
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in SDRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE
|
||||
#define CFG_INIT_RAM_END (8 << 10)
|
||||
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#undef CONFIG_SERIAL_MULTI
|
||||
#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
/*
|
||||
* Define here the location of the environment variables (FLASH or EEPROM).
|
||||
* Note: DENX encourages to use redundant environment in FLASH.
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define CFG_FLASH_ADDR0 0x555
|
||||
#define CFG_FLASH_ADDR1 0x2aa
|
||||
#define CFG_FLASH_WORD_SIZE unsigned char
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#endif /* CFG_ENV_IS_IN_FLASH */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */
|
||||
#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */
|
||||
#define IIC0_DIMM0_ADDR 0x52
|
||||
#define IIC0_DIMM1_ADDR 0x53
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"hostname=luan\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_4xx\0" \
|
||||
"bootfile=/tftpboot/luan/uImage\0" \
|
||||
"kernel_addr=fc000000\0" \
|
||||
"ramdisk_addr=fc100000\0" \
|
||||
"load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 1
|
||||
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
|
||||
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
|
||||
|
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */
|
||||
#define CONFIG_NET_MULTI /* needed for NetConsole */
|
||||
|
||||
/* Partitions */
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_ISO_PARTITION
|
||||
|
||||
#ifdef DEBUG
|
||||
#define CONFIG_PANIC_HANG
|
||||
#else
|
||||
#define CONFIG_HW_WATCHDOG /* watchdog */
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_SETGETDCR | \
|
||||
CFG_CMD_SDRAM | \
|
||||
0)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
#undef CONFIG_LYNXKDI /* support kdi files */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_PCI)
|
||||
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
|
||||
#define CFG_PCI_TARGET_INIT
|
||||
#undef CFG_PCI_MASTER_INIT
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
|
||||
|
||||
#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
|
||||
#define CFG_CACHELINE_SIZE 32 /* ... */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
223
include/ppc440.h
223
include/ppc440.h
@@ -78,7 +78,7 @@
|
||||
#define ivor13 0x19d /* interrupt vector offset register 13 */
|
||||
#define ivor14 0x19e /* interrupt vector offset register 14 */
|
||||
#define ivor15 0x19f /* interrupt vector offset register 15 */
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
|
||||
#define mcsrr0 0x23a /* machine check save/restore register 0 */
|
||||
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
|
||||
#define mcsr 0x23c /* machine check status register */
|
||||
@@ -178,7 +178,6 @@
|
||||
#define sdr_plbtr 0x4200
|
||||
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| SDRAM Controller
|
||||
+----------------------------------------------------------------------------*/
|
||||
@@ -504,7 +503,7 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
| L2 Cache
|
||||
+----------------------------------------------------------------------------*/
|
||||
#if defined (CONFIG_440GX)
|
||||
#if defined (CONFIG_440GX) || defined(CONFIG_440SP)
|
||||
#define L2_CACHE_BASE 0x030
|
||||
#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
|
||||
#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
|
||||
@@ -527,7 +526,7 @@
|
||||
| Clocking, Power Management and Chip Control
|
||||
+----------------------------------------------------------------------------*/
|
||||
#define CNTRL_DCR_BASE 0x0b0
|
||||
#if defined (CONFIG_440GX)
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
|
||||
#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
|
||||
#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
|
||||
#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
|
||||
@@ -690,6 +689,40 @@
|
||||
/*---------------------------------------------------------------------------+
|
||||
| Universal interrupt controller 0 interrupts (UIC0)
|
||||
+---------------------------------------------------------------------------*/
|
||||
#if defined(CONFIG_440SP)
|
||||
#define UIC_U0 0x80000000 /* UART 0 */
|
||||
#define UIC_U1 0x40000000 /* UART 1 */
|
||||
#define UIC_IIC0 0x20000000 /* IIC */
|
||||
#define UIC_IIC1 0x10000000 /* IIC */
|
||||
#define UIC_PIM 0x08000000 /* PCI0 inbound message */
|
||||
#define UIC_PCRW 0x04000000 /* PCI0 command write register */
|
||||
#define UIC_PPM 0x02000000 /* PCI0 power management */
|
||||
#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
|
||||
#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
|
||||
#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
|
||||
#define UIC_P1CRW 0x00200000 /* PCI1 command write register */
|
||||
#define UIC_P1PM 0x00100000 /* PCI1 power management */
|
||||
#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
|
||||
#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
|
||||
#define UIC_P2IM 0x00020000 /* PCI2 inbound message */
|
||||
#define UIC_P2CRW 0x00010000 /* PCI2 command register write */
|
||||
#define UIC_P2PM 0x00008000 /* PCI2 power management */
|
||||
#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
|
||||
#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
|
||||
#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
|
||||
#define UIC_D0CSF 0x00000800 /* DMA0 command status */
|
||||
#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
|
||||
#define UIC_D1CSF 0x00000200 /* DMA1 command status */
|
||||
#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
|
||||
#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
|
||||
#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
|
||||
#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
|
||||
#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
|
||||
#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
|
||||
#define UIC_GPTCT 0x00000004 /* GPT count timer */
|
||||
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
|
||||
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
|
||||
#else /* CONFIG_440SP */
|
||||
#define UIC_U0 0x80000000 /* UART 0 */
|
||||
#define UIC_U1 0x40000000 /* UART 1 */
|
||||
#define UIC_IIC0 0x20000000 /* IIC */
|
||||
@@ -722,6 +755,7 @@
|
||||
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
|
||||
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
|
||||
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
|
||||
#endif /* CONFIG_440SP */
|
||||
|
||||
/* For compatibility with 405 code */
|
||||
#define UIC_MAL_TXEOB UIC_MTE
|
||||
@@ -730,6 +764,40 @@
|
||||
/*---------------------------------------------------------------------------+
|
||||
| Universal interrupt controller 1 interrupts (UIC1)
|
||||
+---------------------------------------------------------------------------*/
|
||||
#if defined(CONFIG_440SP)
|
||||
#define UIC_EIR0 0x80000000 /* External interrupt 0 */
|
||||
#define UIC_MS 0x40000000 /* MAL SERR */
|
||||
#define UIC_MTDE 0x20000000 /* MAL TXDE */
|
||||
#define UIC_MRDE 0x10000000 /* MAL RXDE */
|
||||
#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
|
||||
#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
|
||||
#define UIC_MTE 0x02000000 /* MAL TXEOB */
|
||||
#define UIC_MRE 0x01000000 /* MAL RXEOB */
|
||||
#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
|
||||
#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
|
||||
#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
|
||||
#define UIC_L2C 0x00100000 /* L2 cache */
|
||||
#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
|
||||
#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
|
||||
#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
|
||||
#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
|
||||
#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
|
||||
#define UIC_EIR1 0x00004000 /* External interrupt 1 */
|
||||
#define UIC_EIR2 0x00002000 /* External interrupt 2 */
|
||||
#define UIC_EIR3 0x00001000 /* External interrupt 3 */
|
||||
#define UIC_EIR4 0x00000800 /* External interrupt 4 */
|
||||
#define UIC_EIR5 0x00000400 /* External interrupt 5 */
|
||||
#define UIC_DMAE 0x00000200 /* DMA error */
|
||||
#define UIC_I2OE 0x00000100 /* I2O error */
|
||||
#define UIC_SRE 0x00000080 /* Serial ROM error */
|
||||
#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
|
||||
#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
|
||||
#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
|
||||
#define UIC_ETH0 0x00000008 /* Ethernet 0 */
|
||||
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
|
||||
#define UIC_ETH1 0x00000002 /* Reserved */
|
||||
#define UIC_XOR 0x00000001 /* XOR */
|
||||
#else /* CONFIG_440SP */
|
||||
#define UIC_MS 0x80000000 /* MAL SERR */
|
||||
#define UIC_MTDE 0x40000000 /* MAL TXDE */
|
||||
#define UIC_MRDE 0x20000000 /* MAL RXDE */
|
||||
@@ -762,6 +830,7 @@
|
||||
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
|
||||
#define UIC_ETH1 0x00000002 /* Ethernet 1 */
|
||||
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
|
||||
#endif /* CONFIG_440SP */
|
||||
|
||||
/* For compatibility with 405 code */
|
||||
#define UIC_MAL_SERR UIC_MS
|
||||
@@ -850,6 +919,11 @@
|
||||
#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
|
||||
#define EBC_BXAP_BCE_DISABLE 0x00000000
|
||||
#define EBC_BXAP_BCE_ENABLE 0x00400000
|
||||
#define EBC_BXAP_BCT_MASK 0x00300000
|
||||
#define EBC_BXAP_BCT_2TRANS 0x00000000
|
||||
#define EBC_BXAP_BCT_4TRANS 0x00100000
|
||||
#define EBC_BXAP_BCT_8TRANS 0x00200000
|
||||
#define EBC_BXAP_BCT_16TRANS 0x00300000
|
||||
#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
|
||||
#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||
#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
|
||||
@@ -905,133 +979,22 @@
|
||||
#define EBC_CFG_PR_128 0x0000C000
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| SDR 0 Bit Settings
|
||||
| SDR0 Bit Settings
|
||||
+-----------------------------------------------------------------------------*/
|
||||
#define SDR0_SDSTP0_ENG_MASK 0x80000000
|
||||
#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
|
||||
#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
|
||||
#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
|
||||
#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
|
||||
#define SDR0_SDSTP0_SRC_MASK 0x40000000
|
||||
#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
|
||||
#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
|
||||
#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
|
||||
#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
|
||||
#define SDR0_SDSTP0_SEL_MASK 0x38000000
|
||||
#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
|
||||
#define SDR0_SDSTP0_SEL_CPU 0x08000000
|
||||
#define SDR0_SDSTP0_SEL_EBC 0x28000000
|
||||
#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
|
||||
#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
|
||||
#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
|
||||
#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
|
||||
#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
|
||||
#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
|
||||
#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
|
||||
#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
|
||||
#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
|
||||
#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
|
||||
#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
|
||||
#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
|
||||
#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
|
||||
#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
|
||||
#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
|
||||
#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
|
||||
#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
|
||||
#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
|
||||
#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
|
||||
#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
|
||||
#define SDR0_SDCS_SDD (0x80000000 >> 31)
|
||||
|
||||
#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
|
||||
#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
|
||||
#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
|
||||
#define SDR0_SDSTP1_EBCDV0_MASK 0x03000000
|
||||
#define SDR0_SDSTP1_EBCDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
|
||||
#define SDR0_SDSTP1_EBCDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
|
||||
#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
|
||||
#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
|
||||
#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
|
||||
#define SDR0_SDSTP1_RW_MASK 0x00300000
|
||||
#define SDR0_SDSTP1_RW_8BIT 0x00000000
|
||||
#define SDR0_SDSTP1_RW_16BIT 0x00100000
|
||||
#define SDR0_SDSTP1_RW_32BIT 0x00200000
|
||||
#define SDR0_SDSTP1_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
|
||||
#define SDR0_SDSTP1_RW_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
|
||||
#define SDR0_SDSTP1_EARV_MASK 0x00080000
|
||||
#define SDR0_SDSTP1_EARV_EBC 0x00000000
|
||||
#define SDR0_SDSTP1_EARV_PCI 0x00080000
|
||||
#define SDR0_SDSTP1_PAE_MASK 0x00040000
|
||||
#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
|
||||
#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
|
||||
#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
|
||||
#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
|
||||
#define SDR0_SDSTP1_PHCE_MASK 0x00020000
|
||||
#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
|
||||
#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
|
||||
#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
|
||||
#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
|
||||
#define SDR0_SDSTP1_PISE_MASK 0x00010000
|
||||
#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
|
||||
#define SDR0_SDSTP1_PISE_ENABLE 0x00010000
|
||||
#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
|
||||
#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
|
||||
#define SDR0_SDSTP1_PCWE_MASK 0x00008000
|
||||
#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
|
||||
#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
|
||||
#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
|
||||
#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
|
||||
#define SDR0_SDSTP1_PPIM_MASK 0x00008000
|
||||
#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
|
||||
#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
|
||||
#define SDR0_SDSTP1_PR64E_MASK 0x00000400
|
||||
#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
|
||||
#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
|
||||
#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
|
||||
#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
|
||||
#define SDR0_SDSTP1_PXFS_MASK 0x00000300
|
||||
#define SDR0_SDSTP1_PXFS_HIGH 0x00000000
|
||||
#define SDR0_SDSTP1_PXFS_MED 0x00000100
|
||||
#define SDR0_SDSTP1_PXFS_LOW 0x00000200
|
||||
#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
|
||||
#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
|
||||
#define SDR0_SDSTP1_PDM_MASK 0x00000040
|
||||
#define SDR0_SDSTP1_PDM_MULTIPOINT 0x00000000
|
||||
#define SDR0_SDSTP1_PDM_P2P 0x00000040
|
||||
#define SDR0_SDSTP1_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<6)
|
||||
#define SDR0_SDSTP1_PDM_DECODE(n) ((((unsigned long)(n))>>6)&0x01)
|
||||
#define SDR0_SDSTP1_EPS_MASK 0x00000038
|
||||
#define SDR0_SDSTP1_EPS_GROUP0 0x00000000
|
||||
#define SDR0_SDSTP1_EPS_GROUP1 0x00000008
|
||||
#define SDR0_SDSTP1_EPS_GROUP2 0x00000010
|
||||
#define SDR0_SDSTP1_EPS_GROUP3 0x00000018
|
||||
#define SDR0_SDSTP1_EPS_GROUP4 0x00000020
|
||||
#define SDR0_SDSTP1_EPS_GROUP5 0x00000028
|
||||
#define SDR0_SDSTP1_EPS_GROUP6 0x00000030
|
||||
#define SDR0_SDSTP1_EPS_GROUP7 0x00000038
|
||||
#define SDR0_SDSTP1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<3)
|
||||
#define SDR0_SDSTP1_EPS_DECODE(n) ((((unsigned long)(n))>>3)&0x07)
|
||||
#define SDR0_SDSTP1_RMII_MASK 0x00000004
|
||||
#define SDR0_SDSTP1_RMII_100MBIT 0x00000000
|
||||
#define SDR0_SDSTP1_RMII_10MBIT 0x00000004
|
||||
#define SDR0_SDSTP1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
|
||||
#define SDR0_SDSTP1_RMII_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
|
||||
#define SDR0_SDSTP1_TRE_MASK 0x00000002
|
||||
#define SDR0_SDSTP1_TRE_DISABLE 0x00000000
|
||||
#define SDR0_SDSTP1_TRE_ENABLE 0x00000002
|
||||
#define SDR0_SDSTP1_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
|
||||
#define SDR0_SDSTP1_TRE_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
|
||||
#define SDR0_SDSTP1_NTO1_MASK 0x00000001
|
||||
#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
|
||||
#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
|
||||
#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
|
||||
#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
|
||||
|
||||
#define SDR0_EBC_RW_MASK 0x30000000
|
||||
#define SDR0_EBC_RW_8BIT 0x00000000
|
||||
#define SDR0_EBC_RW_16BIT 0x10000000
|
||||
#define SDR0_EBC_RW_32BIT 0x20000000
|
||||
#define SDR0_EBC_RW_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
|
||||
#define SDR0_EBC_RW_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
|
||||
#if defined(CONFIG_440GP)
|
||||
#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
|
||||
#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
|
||||
#endif /* defined(CONFIG_440GP) */
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
|
||||
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
|
||||
#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
|
||||
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
|
||||
#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
|
||||
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
|
||||
|
||||
#define SDR0_UARTX_UXICS_MASK 0xF0000000
|
||||
#define SDR0_UARTX_UXICS_PLB 0x20000000
|
||||
@@ -1196,7 +1159,7 @@
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Clocking
|
||||
+-----------------------------------------------------------------------------*/
|
||||
#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
|
||||
#if !defined (CONFIG_440GX) && !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && !defined(CONFIG_440SP)
|
||||
#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
|
||||
#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
|
||||
#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
|
||||
|
||||
@@ -131,7 +131,9 @@ typedef struct emac_4xx_hw_st {
|
||||
|
||||
#if defined(CONFIG_440GX)
|
||||
#define EMAC_NUM_DEV 4
|
||||
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && defined(CONFIG_NET_MULTI)
|
||||
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
|
||||
defined(CONFIG_NET_MULTI) && \
|
||||
!defined(CONFIG_440SP)
|
||||
#define EMAC_NUM_DEV 2
|
||||
#else
|
||||
#define EMAC_NUM_DEV 1
|
||||
@@ -321,7 +323,7 @@ typedef struct emac_4xx_hw_st {
|
||||
#define EMAC_M0_WKE (0x04000000)
|
||||
|
||||
/* on 440GX EMAC_MR1 has a different layout! */
|
||||
#if defined(CONFIG_440GX)
|
||||
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
|
||||
/* MODE Reg 1 */
|
||||
#define EMAC_M1_FDE (0x80000000)
|
||||
#define EMAC_M1_ILE (0x40000000)
|
||||
|
||||
Reference in New Issue
Block a user