Convert CONFIG_SYS_LOAD_ADDR to Kconfig

Now that we have consistent usage, migrate this symbol to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Tom Rini
2021-08-23 10:25:31 -04:00
parent 72d81360aa
commit 49c8ef0e45
935 changed files with 636 additions and 564 deletions

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@@ -57,9 +57,5 @@
* (which is common practice).
*/
/*
* MISC
*/
#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */
#endif /* __CONFIG_H */

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@@ -57,9 +57,5 @@
* (which is common practice).
*/
/*
* MISC
*/
#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */
#endif /* __CONFIG_H */

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@@ -66,8 +66,6 @@
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_LOAD_ADDR 0x40010000
#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
#define CONFIG_SYS_PLL_ODR 0x36
#define CONFIG_SYS_PLL_FDR 0x7D

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@@ -78,8 +78,6 @@
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
#define CONFIG_SYS_CLK 75000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2

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@@ -31,8 +31,6 @@
*/
#undef CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
/*
* Clock configuration: enable only one of the following options
*/

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@@ -75,8 +75,6 @@
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET (0)
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK

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@@ -75,7 +75,6 @@
"save\0" \
""
#define CONFIG_SYS_LOAD_ADDR 0x20000
#define CONFIG_SYS_CLK 66000000
/*

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@@ -64,8 +64,6 @@
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
#define CONFIG_SYS_LOAD_ADDR 0x800000
#define CONFIG_BOOTCOMMAND "bootm ffe40000"
#ifdef CONFIG_MCFFEC

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@@ -72,8 +72,6 @@
"save\0" \
""
#define CONFIG_SYS_LOAD_ADDR 0x20000
#define CONFIG_SYS_CLK 64000000
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */

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@@ -81,8 +81,6 @@
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_LOAD_ADDR 0x40010000
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3

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@@ -75,8 +75,6 @@
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_LOAD_ADDR 0x40010000
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3

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@@ -77,8 +77,6 @@
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_LOAD_ADDR 0x40010000
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3

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@@ -60,8 +60,6 @@
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR 0x200000
#define CONFIG_SYS_HZ 1000
/* Definitions for initial stack pointer and data area (in DPRAM) */

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@@ -230,7 +230,6 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -285,7 +285,6 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -315,7 +315,6 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -281,7 +281,6 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -407,7 +407,6 @@ extern unsigned long get_clock_freq(void);
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -269,7 +269,6 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */

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@@ -611,7 +611,6 @@ extern unsigned long get_sdram_size(void);
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -460,7 +460,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -89,6 +89,4 @@
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
#endif /* _CONFIG_SBX81LIFKW_H */

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@@ -89,6 +89,4 @@
#define CONFIG_PHY_BASE_ADR 0x01
#endif /* CONFIG_CMD_NET */
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
#endif /* _CONFIG_SBX81LIFXCAT_H */

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@@ -592,7 +592,6 @@ unsigned long get_board_sys_clk(void);
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -652,7 +652,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -588,7 +588,6 @@ unsigned long get_board_sys_clk(void);
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -537,7 +537,6 @@ unsigned long get_board_sys_clk(void);
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -208,7 +208,6 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -377,7 +377,6 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
/*

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@@ -104,14 +104,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
GENERATED_GBL_DATA_SIZE)
/*
* Load address and memory test area should agree with
* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
*/
#define CONFIG_SYS_LOAD_ADDR 0x300000
/* memtest works on 63 MB in DRAM */
/*
* Static memory controller configuration
*/

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@@ -216,14 +216,6 @@
GENERATED_GBL_DATA_SIZE)
#endif /* CONFIG_MEM_REMAP */
/*
* Load address and memory test area should agree with
* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
*/
#define CONFIG_SYS_LOAD_ADDR 0x300000
/* memtest works on 63 MB in DRAM */
/*
* Static memory controller configuration
*/

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@@ -28,10 +28,6 @@
"erase 0xfff00000 0xffffffff; " \
"cp.b 0x20000 0xfff00000 ${filesize}\0"
/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 45000000

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@@ -16,7 +16,6 @@
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000

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@@ -16,7 +16,6 @@
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000

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@@ -16,7 +16,6 @@
#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000

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@@ -70,7 +70,6 @@
"${blkcnt}; fi\0"
/* Link Definitions */
#define CONFIG_SYS_LOAD_ADDR 0x80280000
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000

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@@ -97,7 +97,6 @@
"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
/* Link Definitions */
#define CONFIG_SYS_LOAD_ADDR 0x89000000
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000

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@@ -71,7 +71,6 @@
#define CONFIG_NETMASK 255.255.255.0
#undef CONFIG_SERVERIP
#define CONFIG_SERVERIP 192.168.10.1
#define CONFIG_SYS_LOAD_ADDR 0x12000000
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \

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@@ -44,8 +44,6 @@
#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
64 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)

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@@ -154,9 +154,6 @@
#endif
#endif
/* default RAM address for user programs */
#define CONFIG_SYS_LOAD_ADDR 0x20000
#define CONFIG_FPGA_COUNT 1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_WAIT 1000

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@@ -106,8 +106,6 @@
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */

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@@ -93,8 +93,6 @@
#endif
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
/* bootstrap + u-boot + env + linux in dataflash on CS0 */

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@@ -209,8 +209,6 @@
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */

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@@ -67,8 +67,6 @@
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */

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@@ -61,9 +61,6 @@
"bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\
"bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0"
/* Ethernet */
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* USB host */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL

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@@ -62,10 +62,6 @@
/* Ethernet - not present */
/* USB - not supported */
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SYS_USE_DATAFLASH
/* bootstrap + u-boot + env + linux in dataflash on CS0 */

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@@ -65,8 +65,6 @@
#endif
#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_BOOTCOMMAND "nand read " \

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@@ -79,20 +79,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \
GENERATED_GBL_DATA_SIZE)
/*
* Load address and memory test area should agree with
* arch/riscv/config.mk. Be careful not to overwrite U-Boot itself.
*/
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */
/*
* memtest works on 512 MB in DRAM
*/
/*
* FLASH and environment organization
*/
/* use CFI framework */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT

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@@ -29,7 +29,6 @@
#define CONFIG_SYS_MALLOC_LEN SZ_2M
#define CONFIG_SYS_BOOTM_LEN SZ_128M
#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
* UART configuration

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@@ -16,7 +16,6 @@
#define PHYS_SDRAM_1 V2M_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x80000)
/*
* Initial SP before reloaction is placed at end of first DRAM bank,

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@@ -88,7 +88,6 @@ extern phys_addr_t prior_stage_fdt_address;
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_LOAD_ADDR 0x2000000
/*
* CONFIG_SYS_LOAD_ADDR - 1 MiB.

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@@ -20,7 +20,6 @@
/* Boot Linux */
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTCOMMAND "bootm"
#define CONFIG_SYS_LOAD_ADDR 0x42000000
/* Extra Environment */
#define CONFIG_EXTRA_ENV_SETTINGS \

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@@ -80,7 +80,6 @@
#define FSL_QSPI_FLASH_NUM 2
#define CONFIG_SYS_FSL_QSPI_LE
#endif
#define CONFIG_SYS_LOAD_ADDR 0x82000000
/* We boot from the gfxRAM area of the OCRAM. */
#define CONFIG_BOARD_SIZE_LIMIT 520192

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@@ -15,7 +15,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -24,7 +24,6 @@
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -24,7 +24,6 @@
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -24,7 +24,6 @@
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -15,7 +15,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -22,7 +22,6 @@
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -24,7 +24,6 @@
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -24,7 +24,6 @@
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -24,7 +24,6 @@
#endif /* CONFIG_USB_OHCI_HCD */
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -15,7 +15,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -33,8 +33,6 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
/*

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@@ -26,7 +26,6 @@
/* U-Boot */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M)
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -25,7 +25,6 @@
/* U-Boot */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M)
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -25,7 +25,6 @@
/* U-Boot */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M)
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SKIP_LOWLEVEL_INIT

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@@ -20,8 +20,6 @@
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_MXC_GPT_HCLK
#define CONFIG_SYS_LOAD_ADDR 0x10700000
/* MMC */
#define CONFIG_FSL_USDHC

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@@ -48,11 +48,6 @@
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif /* !CONFIG_SPL_BUILD, ... */
/*
* Our DDR memory always starts at 0x80000000 and U-Boot shall have
* relocated itself to higher in memory by the time this value is used.
*/
#define CONFIG_SYS_LOAD_ADDR 0x80000000
/*
* ----------------------------------------------------------------------------
* DDR information. We say (for simplicity) that we have 1 bank,

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@@ -127,7 +127,6 @@
"reset;"
/* Default location for tftp and bootm */
#define CONFIG_SYS_LOAD_ADDR 0x80280000
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
/* On CCP board, USDHC1 is for eMMC */

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@@ -147,7 +147,6 @@
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
#define CONFIG_SYS_LOAD_ADDR 0x80280000
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000

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@@ -23,7 +23,6 @@
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE

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@@ -135,9 +135,6 @@ enter a valid image address in flash */
#endif
#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
from which user programs will be started */
/*---*/
/*

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@@ -102,7 +102,6 @@
"vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0"
/* Link Definitions */
#define CONFIG_SYS_LOAD_ADDR 0x80280000
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000

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@@ -60,8 +60,6 @@
#undef CONFIG_SERVERIP
#define CONFIG_SERVERIP 192.168.10.1
#define CONFIG_SYS_LOAD_ADDR 0x12000000
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \

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@@ -82,7 +82,6 @@
#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000

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@@ -38,7 +38,6 @@
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
#define CONFIG_SYS_LOAD_ADDR 0x80008000
#define CONFIG_FDTADDR 0x84000000
/* We boot from the gfxRAM area of the OCRAM. */

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@@ -468,7 +468,6 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
* For booting Linux, the board info and command line data

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@@ -83,8 +83,6 @@
/* DFU class support */
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
/* bootstrap + u-boot + env in nandflash */
#define CONFIG_BOOTCOMMAND \

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@@ -173,7 +173,6 @@
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
/*
* Linux Information

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@@ -25,8 +25,6 @@
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
- GENERATED_GBL_DATA_SIZE)

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@@ -81,8 +81,6 @@
#define CONFIG_HW_WATCHDOG
#endif
#define CONFIG_SYS_LOAD_ADDR 0x12000000
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200\0" \

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@@ -20,7 +20,6 @@
#define PHYS_SDRAM_1_SIZE SZ_1G
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* UART */

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@@ -21,7 +21,6 @@
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
#define CONFIG_SYS_BOOTM_LEN SZ_64M
/* Generic Timer Definitions */

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@@ -13,8 +13,6 @@
#define PHYS_SDRAM_1_SIZE 0x7B000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000)
/* Size of Malloc Pool */
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE)

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@@ -26,7 +26,6 @@
/*
* cmd
*/
#define CONFIG_SYS_LOAD_ADDR 0x80100000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE)
/*

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@@ -47,8 +47,6 @@
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x20000
/*#define CONFIG_SYS_DRAM_TEST 1 */
#undef CONFIG_SYS_DRAM_TEST

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@@ -15,7 +15,6 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Memory */
#define CONFIG_SYS_LOAD_ADDR 0x100000
#define CONFIG_PHYSMEM
#define CONFIG_SYS_STACK_SIZE (32 * 1024)

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@@ -169,7 +169,6 @@
* Other required minimal configurations
*/
#define CONFIG_SYS_LOAD_ADDR 0x00800000
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
/* Enable command line editing */

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@@ -16,7 +16,6 @@
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M)
#define CONFIG_SYS_MALLOC_LEN SZ_64K
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
/*
* Environment

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@@ -34,7 +34,6 @@
/* 128MB SDRAM in 1 bank */
#define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* 512kB on-chip NOR flash */

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@@ -13,7 +13,4 @@
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
/* Memory Info */
#define CONFIG_SYS_LOAD_ADDR 0x83000000
#endif /* __CONFIG_H */

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@@ -10,7 +10,4 @@
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
/* Memory Info */
#define CONFIG_SYS_LOAD_ADDR 0x83000000
#endif /* __CONFIG_H */

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@@ -45,12 +45,6 @@
/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030
/* specific .lds file */
/* Boot Argument Buffer Size */
/* memtest works on */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
#define CONFIG_RD_LVL
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE

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@@ -42,8 +42,6 @@
/* select serial console configuration */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)

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@@ -49,8 +49,6 @@
#define CONFIG_NET_RETRY_COUNT 100
#define CONFIG_SYS_LOAD_ADDR 0x80800000 /* loadaddr env var */
/*
* Ethernet on SOC (FEC)
*/

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@@ -45,8 +45,6 @@
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
/* SPL */
#define CONFIG_SPL_MAX_SIZE 0x7000
#define CONFIG_SPL_STACK 0x308000

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@@ -12,8 +12,6 @@
/* RAM */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
/* SPL */

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@@ -60,7 +60,6 @@
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */

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@@ -114,10 +114,6 @@
#define CONFIG_BOOTCOMMAND MMCBOOTCOMMAND
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_LOAD_ADDR 0x12000000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR

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