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armv8: LS2080A: Rename LS2085A to reflect LS2080A

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LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Prabhakar Kushwaha
2015-11-09 16:42:07 +05:30
committed by York Sun
parent 14480454c7
commit 449372148f
67 changed files with 251 additions and 197 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
include/configs/ls2085a_common.h → include/configs/ls2080a_common.h
View File

@@ -11,7 +11,7 @@
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_FSL_LSCH3
#define CONFIG_LS2085A
#define CONFIG_LS2080A
#define CONFIG_MP
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
@@ -20,7 +20,7 @@
#define CONFIG_ARM_ERRATA_828024
#define CONFIG_ARM_ERRATA_826974
#include <asm/arch/ls2085a_stream_id.h>
#include <asm/arch/ls2080a_stream_id.h>
#include <asm/arch/config.h>
#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
#define CONFIG_SYS_HAS_SERDES
@@ -80,6 +80,7 @@
#define CPU_RELEASE_ADDR secondary_boot_func
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
/*
* DDR controller use 0 as the base address for binding.
@@ -88,6 +89,7 @@
#define CONFIG_SYS_DP_DDR_BASE_PHY 0
#define CONFIG_DP_DDR_CTRL 2
#define CONFIG_DP_DDR_NUM_CTRLS 1
#endif
/* Generic Timer Definitions */
/*
@@ -182,8 +184,10 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
#ifndef CONFIG_LS2080A
#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
#endif
/*
* Carve out a DDR region which will not be used by u-boot/Linux
@@ -204,7 +208,7 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_PCIE3 /* PCIE controler 3 */
#define CONFIG_PCIE4 /* PCIE controler 4 */
#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie"
#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
#define CONFIG_SYS_PCI_64BIT

8
include/configs/ls2085a_emu.h → include/configs/ls2080a_emu.h
View File

@@ -7,10 +7,10 @@
#ifndef __LS2_EMU_H
#define __LS2_EMU_H
#include "ls2085a_common.h"
#include "ls2080a_common.h"
#define CONFIG_IDENT_STRING " LS2085A-EMU"
#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU"
#define CONFIG_IDENT_STRING " LS2080A-EMU"
#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-EMU"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
@@ -27,7 +27,9 @@
#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
#define CONFIG_FSL_DDR_SYNC_REFRESH

8
include/configs/ls2085a_simu.h → include/configs/ls2080a_simu.h
View File

@@ -7,10 +7,10 @@
#ifndef __LS2_SIMU_H
#define __LS2_SIMU_H
#include "ls2085a_common.h"
#include "ls2080a_common.h"
#define CONFIG_IDENT_STRING " LS2085A-SIMU"
#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU"
#define CONFIG_IDENT_STRING " LS2080A-SIMU"
#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2080A-SIMU"
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 133333333
@@ -20,7 +20,9 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
/* SMSC 91C111 ethernet configuration */
#define CONFIG_SMC91111

4
include/configs/ls2085aqds.h → include/configs/ls2080aqds.h
View File

@@ -7,7 +7,7 @@
#ifndef __LS2_QDS_H
#define __LS2_QDS_H
#include "ls2085a_common.h"
#include "ls2080a_common.h"
#define CONFIG_DISPLAY_BOARDINFO
@@ -35,7 +35,9 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */

4
include/configs/ls2085ardb.h → include/configs/ls2080ardb.h
View File

@@ -7,7 +7,7 @@
#ifndef __LS2_RDB_H
#define __LS2_RDB_H
#include "ls2085a_common.h"
#include "ls2080a_common.h"
#undef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX 2
@@ -37,7 +37,9 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif
#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */

6
include/linux/usb/xhci-fsl.h
View File

@@ -54,9 +54,9 @@ struct fsl_xhci {
#if defined(CONFIG_LS102XA)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#elif defined(CONFIG_LS2085A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
#elif defined(CONFIG_LS2080A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
#endif
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \