power: rename stpmu1 to official name stpmic1
Alignment with kernel driver name & binding introduced by https://patchwork.kernel.org/cover/10761943/ to use the final marketing name = STPMIC1. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Patrick Delaunay
@@ -1,60 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This file is part of stpmu1 pmic driver
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*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author: Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
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*
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* License type: GPLv2
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Philippe Peurichard <philippe.peurichard@st.com>,
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* Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
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*/
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#ifndef __DT_BINDINGS_STPMU1_H__
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#define __DT_BINDINGS_STPMU1_H__
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#ifndef __DT_BINDINGS_STPMIC1_H__
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#define __DT_BINDINGS_STPMIC1_H__
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/* IRQ definitions */
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#define IT_PONKEY_F 0
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#define IT_PONKEY_R 1
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#define IT_WAKEUP_F 2
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#define IT_WAKEUP_R 3
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#define IT_VBUS_OTG_F 4
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#define IT_VBUS_OTG_R 5
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#define IT_SWOUT_F 6
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#define IT_SWOUT_R 7
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#define IT_PONKEY_F 0
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#define IT_PONKEY_R 1
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#define IT_WAKEUP_F 2
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#define IT_WAKEUP_R 3
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#define IT_VBUS_OTG_F 4
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#define IT_VBUS_OTG_R 5
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#define IT_SWOUT_F 6
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#define IT_SWOUT_R 7
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#define IT_CURLIM_BUCK1 8
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#define IT_CURLIM_BUCK2 9
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#define IT_CURLIM_BUCK3 10
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#define IT_CURLIM_BUCK4 11
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#define IT_OCP_OTG 12
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#define IT_OCP_SWOUT 13
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#define IT_OCP_BOOST 14
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#define IT_OVP_BOOST 15
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#define IT_CURLIM_BUCK1 8
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#define IT_CURLIM_BUCK2 9
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#define IT_CURLIM_BUCK3 10
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#define IT_CURLIM_BUCK4 11
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#define IT_OCP_OTG 12
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#define IT_OCP_SWOUT 13
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#define IT_OCP_BOOST 14
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#define IT_OVP_BOOST 15
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#define IT_CURLIM_LDO1 16
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#define IT_CURLIM_LDO2 17
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#define IT_CURLIM_LDO3 18
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#define IT_CURLIM_LDO4 19
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#define IT_CURLIM_LDO5 20
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#define IT_CURLIM_LDO6 21
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#define IT_SHORT_SWOTG 22
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#define IT_SHORT_SWOUT 23
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#define IT_CURLIM_LDO1 16
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#define IT_CURLIM_LDO2 17
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#define IT_CURLIM_LDO3 18
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#define IT_CURLIM_LDO4 19
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#define IT_CURLIM_LDO5 20
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#define IT_CURLIM_LDO6 21
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#define IT_SHORT_SWOTG 22
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#define IT_SHORT_SWOUT 23
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#define IT_TWARN_F 24
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#define IT_TWARN_R 25
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#define IT_VINLOW_F 26
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#define IT_VINLOW_R 27
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#define IT_SWIN_F 30
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#define IT_SWIN_R 31
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#define IT_TWARN_F 24
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#define IT_TWARN_R 25
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#define IT_VINLOW_F 26
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#define IT_VINLOW_R 27
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#define IT_SWIN_F 30
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#define IT_SWIN_R 31
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#endif /* __DT_BINDINGS_STPMU1_H__ */
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#endif /* __DT_BINDINGS_STPMIC1_H__ */
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@@ -3,83 +3,90 @@
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#ifndef __PMIC_STPMU1_H_
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#define __PMIC_STPMU1_H_
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#ifndef __PMIC_STPMIC1_H_
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#define __PMIC_STPMIC1_H_
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#define STPMU1_MASK_RESET_BUCK 0x18
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#define STPMU1_BUCKX_CTRL_REG(buck) (0x20 + (buck))
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#define STPMU1_VREF_CTRL_REG 0x24
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#define STPMU1_LDOX_CTRL_REG(ldo) (0x25 + (ldo))
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#define STPMU1_USB_CTRL_REG 0x40
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#define STPMU1_NVM_USER_STATUS_REG 0xb8
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#define STPMU1_NVM_USER_CONTROL_REG 0xb9
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#define STPMIC1_MAIN_CONTROL_REG 0x10
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#define STPMIC1_MASK_RESET_BUCK 0x18
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#define STPMIC1_MASK_RESET_LDOS 0x1a
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#define STPMIC1_BUCKX_CTRL_REG(buck) (0x20 + (buck))
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#define STPMIC1_VREF_CTRL_REG 0x24
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#define STPMIC1_LDOX_CTRL_REG(ldo) (0x25 + (ldo))
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#define STPMIC1_USB_CTRL_REG 0x40
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#define STPMIC1_NVM_USER_STATUS_REG 0xb8
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#define STPMIC1_NVM_USER_CONTROL_REG 0xb9
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#define STPMU1_MASK_RESET_BUCK3 BIT(2)
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/* Main PMIC Control Register (MAIN_CONTROL_REG) */
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#define STPMIC1_CTRL_SWITCH_OFF BIT(0)
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#define STPMIC1_CTRL_RESTART BIT(1)
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#define STPMU1_BUCK_EN BIT(0)
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#define STPMU1_BUCK_MODE BIT(1)
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#define STPMU1_BUCK_OUTPUT_MASK GENMASK(7, 2)
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#define STPMU1_BUCK_OUTPUT_SHIFT 2
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#define STPMU1_BUCK2_1200000V (24 << STPMU1_BUCK_OUTPUT_SHIFT)
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#define STPMU1_BUCK2_1350000V (30 << STPMU1_BUCK_OUTPUT_SHIFT)
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#define STPMU1_BUCK3_1800000V (39 << STPMU1_BUCK_OUTPUT_SHIFT)
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#define STPMIC1_MASK_RESET_BUCK3 BIT(2)
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#define STPMIC1_MASK_RESET_BUCK_DBG GENMASK(3, 0)
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#define STPMIC1_MASK_RESET_LDOS_DBG 0x6F
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#define STPMU1_VREF_EN BIT(0)
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#define STPMIC1_BUCK_EN BIT(0)
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#define STPMIC1_BUCK_MODE BIT(1)
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#define STPMIC1_BUCK_OUTPUT_MASK GENMASK(7, 2)
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#define STPMIC1_BUCK_OUTPUT_SHIFT 2
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#define STPMIC1_BUCK2_1200000V (24 << STPMIC1_BUCK_OUTPUT_SHIFT)
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#define STPMIC1_BUCK2_1350000V (30 << STPMIC1_BUCK_OUTPUT_SHIFT)
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#define STPMIC1_BUCK3_1800000V (39 << STPMIC1_BUCK_OUTPUT_SHIFT)
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#define STPMU1_LDO_EN BIT(0)
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#define STPMU1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
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#define STPMU1_LDO12356_OUTPUT_SHIFT 2
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#define STPMU1_LDO3_MODE BIT(7)
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#define STPMU1_LDO3_DDR_SEL 31
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#define STPMU1_LDO3_1800000 (9 << STPMU1_LDO12356_OUTPUT_SHIFT)
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#define STPMU1_LDO4_UV 3300000
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#define STPMIC1_VREF_EN BIT(0)
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#define STPMU1_USB_BOOST_EN BIT(0)
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#define STPMU1_USB_PWR_SW_EN GENMASK(2, 1)
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#define STPMIC1_LDO_EN BIT(0)
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#define STPMIC1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
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#define STPMIC1_LDO12356_OUTPUT_SHIFT 2
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#define STPMIC1_LDO3_MODE BIT(7)
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#define STPMIC1_LDO3_DDR_SEL 31
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#define STPMIC1_LDO3_1800000 (9 << STPMIC1_LDO12356_OUTPUT_SHIFT)
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#define STPMIC1_LDO4_UV 3300000
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#define STPMU1_NVM_USER_CONTROL_PROGRAM BIT(0)
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#define STPMU1_NVM_USER_CONTROL_READ BIT(1)
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#define STPMIC1_USB_BOOST_EN BIT(0)
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#define STPMIC1_USB_PWR_SW_EN GENMASK(2, 1)
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#define STPMU1_NVM_USER_STATUS_BUSY BIT(0)
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#define STPMU1_NVM_USER_STATUS_ERROR BIT(1)
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#define STPMIC1_NVM_USER_CONTROL_PROGRAM BIT(0)
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#define STPMIC1_NVM_USER_CONTROL_READ BIT(1)
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#define STPMU1_DEFAULT_START_UP_DELAY_MS 1
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#define STPMU1_DEFAULT_STOP_DELAY_MS 5
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#define STPMU1_USB_BOOST_START_UP_DELAY_MS 10
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#define STPMIC1_NVM_USER_STATUS_BUSY BIT(0)
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#define STPMIC1_NVM_USER_STATUS_ERROR BIT(1)
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#define STPMIC1_DEFAULT_START_UP_DELAY_MS 1
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#define STPMIC1_DEFAULT_STOP_DELAY_MS 5
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#define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10
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enum {
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STPMU1_BUCK1,
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STPMU1_BUCK2,
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STPMU1_BUCK3,
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STPMU1_BUCK4,
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STPMU1_MAX_BUCK,
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STPMIC1_BUCK1,
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STPMIC1_BUCK2,
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STPMIC1_BUCK3,
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STPMIC1_BUCK4,
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STPMIC1_MAX_BUCK,
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};
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enum {
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STPMU1_BUCK_MODE_HP,
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STPMU1_BUCK_MODE_LP,
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STPMIC1_BUCK_MODE_HP,
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STPMIC1_BUCK_MODE_LP,
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};
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enum {
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STPMU1_LDO1,
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STPMU1_LDO2,
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STPMU1_LDO3,
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STPMU1_LDO4,
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STPMU1_LDO5,
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STPMU1_LDO6,
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STPMU1_MAX_LDO,
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STPMIC1_LDO1,
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STPMIC1_LDO2,
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STPMIC1_LDO3,
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STPMIC1_LDO4,
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STPMIC1_LDO5,
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STPMIC1_LDO6,
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STPMIC1_MAX_LDO,
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};
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enum {
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STPMU1_LDO_MODE_NORMAL,
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STPMU1_LDO_MODE_BYPASS,
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STPMU1_LDO_MODE_SINK_SOURCE,
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STPMIC1_LDO_MODE_NORMAL,
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STPMIC1_LDO_MODE_BYPASS,
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STPMIC1_LDO_MODE_SINK_SOURCE,
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};
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enum {
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STPMU1_PWR_SW1,
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STPMU1_PWR_SW2,
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STPMU1_MAX_PWR_SW,
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STPMIC1_PWR_SW1,
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STPMIC1_PWR_SW2,
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STPMIC1_MAX_PWR_SW,
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};
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#endif
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