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ARM: dts: rmobile: Import DTS from Linux 4.12

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Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.12-rc6,
commit 6f7da290413ba713f0cdd9ff1a2a9bb129ef4f6c . This includes both M3
and H3 ULCB and Salvator-X boards.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
2017-07-21 23:16:59 +02:00
committed by Nobuhiro Iwamatsu
parent 48aa812676
commit 4157c472c3
12 changed files with 4558 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

70
include/dt-bindings/clock/r8a7795-cpg-mssr.h Normal file
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/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7795 CPG Core Clocks */
#define R8A7795_CLK_Z 0
#define R8A7795_CLK_Z2 1
#define R8A7795_CLK_ZR 2
#define R8A7795_CLK_ZG 3
#define R8A7795_CLK_ZTR 4
#define R8A7795_CLK_ZTRD2 5
#define R8A7795_CLK_ZT 6
#define R8A7795_CLK_ZX 7
#define R8A7795_CLK_S0D1 8
#define R8A7795_CLK_S0D4 9
#define R8A7795_CLK_S1D1 10
#define R8A7795_CLK_S1D2 11
#define R8A7795_CLK_S1D4 12
#define R8A7795_CLK_S2D1 13
#define R8A7795_CLK_S2D2 14
#define R8A7795_CLK_S2D4 15
#define R8A7795_CLK_S3D1 16
#define R8A7795_CLK_S3D2 17
#define R8A7795_CLK_S3D4 18
#define R8A7795_CLK_LB 19
#define R8A7795_CLK_CL 20
#define R8A7795_CLK_ZB3 21
#define R8A7795_CLK_ZB3D2 22
#define R8A7795_CLK_CR 23
#define R8A7795_CLK_CRD2 24
#define R8A7795_CLK_SD0H 25
#define R8A7795_CLK_SD0 26
#define R8A7795_CLK_SD1H 27
#define R8A7795_CLK_SD1 28
#define R8A7795_CLK_SD2H 29
#define R8A7795_CLK_SD2 30
#define R8A7795_CLK_SD3H 31
#define R8A7795_CLK_SD3 32
#define R8A7795_CLK_SSP2 33
#define R8A7795_CLK_SSP1 34
#define R8A7795_CLK_SSPRS 35
#define R8A7795_CLK_RPC 36
#define R8A7795_CLK_RPCD2 37
#define R8A7795_CLK_MSO 38
#define R8A7795_CLK_CANFD 39
#define R8A7795_CLK_HDMI 40
#define R8A7795_CLK_CSI0 41
#define R8A7795_CLK_CSIREF 42
#define R8A7795_CLK_CP 43
#define R8A7795_CLK_CPEX 44
#define R8A7795_CLK_R 45
#define R8A7795_CLK_OSC 46
/* r8a7795 ES2.0 CPG Core Clocks */
#define R8A7795_CLK_S0D2 47
#define R8A7795_CLK_S0D3 48
#define R8A7795_CLK_S0D6 49
#define R8A7795_CLK_S0D8 50
#define R8A7795_CLK_S0D12 51
#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */

69
include/dt-bindings/clock/r8a7796-cpg-mssr.h Normal file
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/*
* Copyright (C) 2016 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7796 CPG Core Clocks */
#define R8A7796_CLK_Z 0
#define R8A7796_CLK_Z2 1
#define R8A7796_CLK_ZR 2
#define R8A7796_CLK_ZG 3
#define R8A7796_CLK_ZTR 4
#define R8A7796_CLK_ZTRD2 5
#define R8A7796_CLK_ZT 6
#define R8A7796_CLK_ZX 7
#define R8A7796_CLK_S0D1 8
#define R8A7796_CLK_S0D2 9
#define R8A7796_CLK_S0D3 10
#define R8A7796_CLK_S0D4 11
#define R8A7796_CLK_S0D6 12
#define R8A7796_CLK_S0D8 13
#define R8A7796_CLK_S0D12 14
#define R8A7796_CLK_S1D1 15
#define R8A7796_CLK_S1D2 16
#define R8A7796_CLK_S1D4 17
#define R8A7796_CLK_S2D1 18
#define R8A7796_CLK_S2D2 19
#define R8A7796_CLK_S2D4 20
#define R8A7796_CLK_S3D1 21
#define R8A7796_CLK_S3D2 22
#define R8A7796_CLK_S3D4 23
#define R8A7796_CLK_LB 24
#define R8A7796_CLK_CL 25
#define R8A7796_CLK_ZB3 26
#define R8A7796_CLK_ZB3D2 27
#define R8A7796_CLK_ZB3D4 28
#define R8A7796_CLK_CR 29
#define R8A7796_CLK_CRD2 30
#define R8A7796_CLK_SD0H 31
#define R8A7796_CLK_SD0 32
#define R8A7796_CLK_SD1H 33
#define R8A7796_CLK_SD1 34
#define R8A7796_CLK_SD2H 35
#define R8A7796_CLK_SD2 36
#define R8A7796_CLK_SD3H 37
#define R8A7796_CLK_SD3 38
#define R8A7796_CLK_SSP2 39
#define R8A7796_CLK_SSP1 40
#define R8A7796_CLK_SSPRS 41
#define R8A7796_CLK_RPC 42
#define R8A7796_CLK_RPCD2 43
#define R8A7796_CLK_MSO 44
#define R8A7796_CLK_CANFD 45
#define R8A7796_CLK_HDMI 46
#define R8A7796_CLK_CSI0 47
#define R8A7796_CLK_CSIREF 48
#define R8A7796_CLK_CP 49
#define R8A7796_CLK_CPEX 50
#define R8A7796_CLK_R 51
#define R8A7796_CLK_OSC 52
#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */

15
include/dt-bindings/clock/renesas-cpg-mssr.h Normal file
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/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
#define CPG_CORE 0 /* Core Clock */
#define CPG_MOD 1 /* Module Clock */
#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */

42
include/dt-bindings/power/r8a7795-sysc.h Normal file
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/*
* Copyright (C) 2016 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7795_PD_CA57_CPU0 0
#define R8A7795_PD_CA57_CPU1 1
#define R8A7795_PD_CA57_CPU2 2
#define R8A7795_PD_CA57_CPU3 3
#define R8A7795_PD_CA53_CPU0 5
#define R8A7795_PD_CA53_CPU1 6
#define R8A7795_PD_CA53_CPU2 7
#define R8A7795_PD_CA53_CPU3 8
#define R8A7795_PD_A3VP 9
#define R8A7795_PD_CA57_SCU 12
#define R8A7795_PD_CR7 13
#define R8A7795_PD_A3VC 14
#define R8A7795_PD_3DG_A 17
#define R8A7795_PD_3DG_B 18
#define R8A7795_PD_3DG_C 19
#define R8A7795_PD_3DG_D 20
#define R8A7795_PD_CA53_SCU 21
#define R8A7795_PD_3DG_E 22
#define R8A7795_PD_A3IR 24
#define R8A7795_PD_A2VC0 25 /* ES1.x only */
#define R8A7795_PD_A2VC1 26
/* Always-on power area */
#define R8A7795_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */

36
include/dt-bindings/power/r8a7796-sysc.h Normal file
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/*
* Copyright (C) 2016 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7796_PD_CA57_CPU0 0
#define R8A7796_PD_CA57_CPU1 1
#define R8A7796_PD_CA53_CPU0 5
#define R8A7796_PD_CA53_CPU1 6
#define R8A7796_PD_CA53_CPU2 7
#define R8A7796_PD_CA53_CPU3 8
#define R8A7796_PD_CA57_SCU 12
#define R8A7796_PD_CR7 13
#define R8A7796_PD_A3VC 14
#define R8A7796_PD_3DG_A 17
#define R8A7796_PD_3DG_B 18
#define R8A7796_PD_CA53_SCU 21
#define R8A7796_PD_A3IR 24
#define R8A7796_PD_A2VC0 25
#define R8A7796_PD_A2VC1 26
/* Always-on power area */
#define R8A7796_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */