Merge tag 'u-boot-imx-20210125' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Changes for 2020.04 ------------------- - new board: Phytec phyCORE-i.MX8MP i.MX8MN Beacon EmbeddedWorks devkit - Fixes: several nanbcb fixes fix for imx8mm_beacon - further switch to distro boot commands - DM: DM Ether for MX6UL CI: https://gitlab.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6013
This commit is contained in:
Tom Rini
@@ -22,16 +22,9 @@
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_ENET_DEV 0
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#if (CONFIG_FEC_ENET_DEV == 0)
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "eth0"
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#elif (CONFIG_FEC_ENET_DEV == 1)
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#define IMX_FEC_BASE ENET2_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x3
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "eth1"
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#endif
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#endif
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@@ -36,11 +36,9 @@
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"image=Image\0" \
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"console=ttymxc1,115200\0" \
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"fdt_addr=0x43000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"boot_fit=try\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"initrd_addr=0x43800000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
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@@ -32,9 +32,20 @@
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#endif
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 2) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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BOOTENV \
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"scriptaddr=0x43500000\0" \
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"kernel_addr_r=0x40880000\0" \
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"image=Image\0" \
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"console=ttymxc1,115200\0" \
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"fdt_addr=0x43000000\0" \
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@@ -42,59 +53,8 @@
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"fdt_file=imx8mm-evk.dtb\0" \
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
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"bootm ${loadaddr}; " \
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"else " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi;\0" \
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"netargs=setenv bootargs console=${console} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
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"bootm ${loadaddr}; " \
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"else " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"fi;\0"
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"fi;"
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/* Link Definitions */
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#define CONFIG_LOADADDR 0x40480000
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155
include/configs/imx8mn_beacon.h
Normal file
155
include/configs/imx8mn_beacon.h
Normal file
@@ -0,0 +1,155 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 Compass Electronics Group, LLC
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*/
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#ifndef __IMX8MN_BEACON_H
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#define __IMX8MN_BEACON_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
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#define CONFIG_SYS_MONITOR_LEN SZ_512K
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_STACK 0x187FF0
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#define CONFIG_SPL_BSS_START_ADDR 0x0095e000
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#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x184000
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/* For RAW image gives a error info not panic */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#endif /* CONFIG_SPL_BUILD */
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#define CONFIG_REMAKE_ELF
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=Image\0" \
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"ramdiskimage=rootfs.cpio.uboot\0" \
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"console=ttymxc1,115200\0" \
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"fdt_addr=0x43000000\0" \
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"ramdisk_addr=0x44000000\0" \
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"boot_fdt=try\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"initrd_addr=0x43800000\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} " \
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" root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
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"ramargs=setenv bootargs console=${console} root=/dev/ram rw " \
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" ${optargs}\0" \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage}\0"\
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"mmcboot=echo Booting from mmc ...; " \
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"run finduuid; run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"else " \
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"echo wait for boot; " \
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"fi;\0" \
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"netargs=setenv bootargs console=${console} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"else " \
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"booti; " \
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"fi;\0" \
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"ramboot=echo Booting from RAMdisk...; "\
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"run loadimage; run loadfdt; fdt addr $fdt_addr; "\
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"run loadramdisk; run ramargs; " \
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"booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs}\0"
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else booti ${loadaddr} - ${fdt_addr}; fi"
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/* Link Definitions */
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#define CONFIG_LOADADDR 0x40480000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x200000
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_ENV_OVERWRITE
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN SZ_32M
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
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#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_CBSIZE 2048
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* USDHC */
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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/* ENET Config */
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#if defined(CONFIG_FEC_MXC)
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define FEC_QUIRK_ENET_MAC
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#define IMX_FEC_BASE 0x30BE0000
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#endif /* CONFIG_FEC_MXC */
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#endif
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@@ -20,16 +20,11 @@
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_STACK 0x95fff0
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#define CONFIG_SPL_BSS_START_ADDR 0x00950000
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#define CONFIG_SPL_STACK 0x980000
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#define CONFIG_SPL_BSS_START_ADDR 0x950000
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#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
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#define CONFIG_MALLOC_F_ADDR 0x00940000
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/* For RAW image gives a error info not panic */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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@@ -26,8 +26,6 @@
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#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
|
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#define CONFIG_SYS_ICACHE_OFF
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#define CONFIG_SYS_DCACHE_OFF
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|
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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|
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@@ -44,9 +42,35 @@
|
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|
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#endif
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|
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
|
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|
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#define CONFIG_FEC_XCV_TYPE RGMII
|
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#define CONFIG_FEC_MXC_PHYADDR 1
|
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#define FEC_QUIRK_ENET_MAC
|
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|
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#define DWC_NET_PHYADDR 1
|
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#ifdef CONFIG_DWC_ETH_QOS
|
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#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
|
||||
#endif
|
||||
|
||||
#define PHY_ANEG_TIMEOUT 20000
|
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|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 1) \
|
||||
func(MMC, mmc, 2)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
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#endif
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
BOOTENV \
|
||||
"scriptaddr=0x43500000\0" \
|
||||
"kernel_addr_r=0x40880000\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
|
||||
"fdt_addr=0x43000000\0" \
|
||||
@@ -54,59 +78,8 @@
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs ${jh_clk} console=${console} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x40480000
|
||||
|
||||
@@ -74,20 +74,20 @@
|
||||
#define IMX_FEC_BASE 0x30BE0000
|
||||
#endif
|
||||
|
||||
#define CONFIG_MFG_ENV_SETTINGS \
|
||||
"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
|
||||
"rdinit=/linuxrc " \
|
||||
"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
|
||||
"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
|
||||
"g_mass_storage.iSerialNumber=\"\" "\
|
||||
"clk_ignore_unused "\
|
||||
"\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 0) \
|
||||
func(MMC, mmc, 1) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#endif
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_MFG_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
BOOTENV \
|
||||
"scriptaddr=0x43500000\0" \
|
||||
"kernel_addr_r=0x40880000\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc0,115200\0" \
|
||||
"fdt_addr=0x43000000\0" \
|
||||
@@ -95,59 +95,8 @@
|
||||
"fdt_file=imx8mq-evk.dtb\0" \
|
||||
"initrd_addr=0x43800000\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x40480000
|
||||
|
||||
107
include/configs/phycore_imx8mp.h
Normal file
107
include/configs/phycore_imx8mp.h
Normal file
@@ -0,0 +1,107 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
|
||||
* Author: Teresa Remmet <t.remmet@phytec.de>
|
||||
*/
|
||||
|
||||
#ifndef __PHYCORE_IMX8MP_H
|
||||
#define __PHYCORE_IMX8MP_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN SZ_64M
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K)
|
||||
#define CONFIG_SYS_MONITOR_LEN SZ_512K
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
|
||||
#define CONFIG_SYS_UBOOT_BASE \
|
||||
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x960000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x98FC00
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
|
||||
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PCA9450
|
||||
|
||||
#undef CONFIG_DM_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc1,115200\0" \
|
||||
"fdt_addr=0x48000000\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=2\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi;\0 " \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi;"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x40480000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN SZ_32M
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0x80000000
|
||||
|
||||
/* UART */
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE SZ_2K
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/* USDHC */
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
#endif /* __PHYCORE_IMX8MP_H */
|
||||
@@ -122,8 +122,8 @@
|
||||
#define IMX8MN_CLK_I2C1 105
|
||||
#define IMX8MN_CLK_I2C2 106
|
||||
#define IMX8MN_CLK_I2C3 107
|
||||
#define IMX8MN_CLK_I2C4 118
|
||||
#define IMX8MN_CLK_UART1 119
|
||||
#define IMX8MN_CLK_I2C4 108
|
||||
#define IMX8MN_CLK_UART1 109
|
||||
#define IMX8MN_CLK_UART2 110
|
||||
#define IMX8MN_CLK_UART3 111
|
||||
#define IMX8MN_CLK_UART4 112
|
||||
@@ -209,7 +209,31 @@
|
||||
#define IMX8MN_CLK_ARM 191
|
||||
#define IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK 192
|
||||
#define IMX8MN_CLK_GPU_CORE_ROOT 193
|
||||
#define IMX8MN_CLK_GIC 194
|
||||
|
||||
#define IMX8MN_CLK_END 194
|
||||
#define IMX8MN_SYS_PLL1_40M_CG 195
|
||||
#define IMX8MN_SYS_PLL1_80M_CG 196
|
||||
#define IMX8MN_SYS_PLL1_100M_CG 197
|
||||
#define IMX8MN_SYS_PLL1_133M_CG 198
|
||||
#define IMX8MN_SYS_PLL1_160M_CG 199
|
||||
#define IMX8MN_SYS_PLL1_200M_CG 200
|
||||
#define IMX8MN_SYS_PLL1_266M_CG 201
|
||||
#define IMX8MN_SYS_PLL1_400M_CG 202
|
||||
#define IMX8MN_SYS_PLL2_50M_CG 203
|
||||
#define IMX8MN_SYS_PLL2_100M_CG 204
|
||||
#define IMX8MN_SYS_PLL2_125M_CG 205
|
||||
#define IMX8MN_SYS_PLL2_166M_CG 206
|
||||
#define IMX8MN_SYS_PLL2_200M_CG 207
|
||||
#define IMX8MN_SYS_PLL2_250M_CG 208
|
||||
#define IMX8MN_SYS_PLL2_333M_CG 209
|
||||
#define IMX8MN_SYS_PLL2_500M_CG 210
|
||||
|
||||
#define IMX8MN_CLK_SNVS_ROOT 211
|
||||
#define IMX8MN_CLK_GPU_CORE 212
|
||||
#define IMX8MN_CLK_GPU_SHADER 213
|
||||
|
||||
#define IMX8MN_CLK_A53_CORE 214
|
||||
|
||||
#define IMX8MN_CLK_END 215
|
||||
|
||||
#endif
|
||||
|
||||
@@ -173,14 +173,14 @@
|
||||
#define IMX8MP_CLK_IPP_DO_CLKO1 164
|
||||
#define IMX8MP_CLK_IPP_DO_CLKO2 165
|
||||
#define IMX8MP_CLK_HDMI_FDCC_TST 166
|
||||
#define IMX8MP_CLK_HDMI_27M 167
|
||||
#define IMX8MP_CLK_HDMI_24M 167
|
||||
#define IMX8MP_CLK_HDMI_REF_266M 168
|
||||
#define IMX8MP_CLK_USDHC3 169
|
||||
#define IMX8MP_CLK_MEDIA_CAM1_PIX 170
|
||||
#define IMX8MP_CLK_MEDIA_MIPI_PHY1_REF 171
|
||||
#define IMX8MP_CLK_MEDIA_DISP1_PIX 172
|
||||
#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
|
||||
#define IMX8MP_CLK_MEDIA_MIPI_PHY2_REF 174
|
||||
#define IMX8MP_CLK_MEDIA_LDB 174
|
||||
#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
|
||||
#define IMX8MP_CLK_PCIE2_CTRL 176
|
||||
#define IMX8MP_CLK_PCIE2_PHY 177
|
||||
@@ -294,7 +294,96 @@
|
||||
#define IMX8MP_CLK_DRAM_ALT_ROOT 285
|
||||
#define IMX8MP_CLK_DRAM_CORE 286
|
||||
#define IMX8MP_CLK_ARM 287
|
||||
#define IMX8MP_CLK_A53_CORE 288
|
||||
|
||||
#define IMX8MP_CLK_END 288
|
||||
#define IMX8MP_SYS_PLL1_40M_CG 289
|
||||
#define IMX8MP_SYS_PLL1_80M_CG 290
|
||||
#define IMX8MP_SYS_PLL1_100M_CG 291
|
||||
#define IMX8MP_SYS_PLL1_133M_CG 292
|
||||
#define IMX8MP_SYS_PLL1_160M_CG 293
|
||||
#define IMX8MP_SYS_PLL1_200M_CG 294
|
||||
#define IMX8MP_SYS_PLL1_266M_CG 295
|
||||
#define IMX8MP_SYS_PLL1_400M_CG 296
|
||||
#define IMX8MP_SYS_PLL2_50M_CG 297
|
||||
#define IMX8MP_SYS_PLL2_100M_CG 298
|
||||
#define IMX8MP_SYS_PLL2_125M_CG 299
|
||||
#define IMX8MP_SYS_PLL2_166M_CG 300
|
||||
#define IMX8MP_SYS_PLL2_200M_CG 301
|
||||
#define IMX8MP_SYS_PLL2_250M_CG 302
|
||||
#define IMX8MP_SYS_PLL2_333M_CG 303
|
||||
#define IMX8MP_SYS_PLL2_500M_CG 304
|
||||
|
||||
#define IMX8MP_CLK_M7_CORE 305
|
||||
#define IMX8MP_CLK_ML_CORE 306
|
||||
#define IMX8MP_CLK_GPU3D_CORE 307
|
||||
#define IMX8MP_CLK_GPU3D_SHADER_CORE 308
|
||||
#define IMX8MP_CLK_GPU2D_CORE 309
|
||||
#define IMX8MP_CLK_AUDIO_AXI 310
|
||||
#define IMX8MP_CLK_HSIO_AXI 311
|
||||
#define IMX8MP_CLK_MEDIA_ISP 312
|
||||
|
||||
#define IMX8MP_CLK_END 313
|
||||
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23
|
||||
#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24
|
||||
#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25
|
||||
#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26
|
||||
#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27
|
||||
#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28
|
||||
#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29
|
||||
#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30
|
||||
#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31
|
||||
#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32
|
||||
#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33
|
||||
#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34
|
||||
#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35
|
||||
#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36
|
||||
#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37
|
||||
#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38
|
||||
#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53
|
||||
#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57
|
||||
#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58
|
||||
|
||||
#define IMX8MP_CLK_AUDIOMIX_END 59
|
||||
|
||||
#endif
|
||||
|
||||
@@ -403,5 +403,34 @@
|
||||
#define IMX8MQ_CLK_SNVS_ROOT 264
|
||||
#define IMX8MQ_CLK_GIC 265
|
||||
|
||||
#define IMX8MQ_CLK_END 266
|
||||
#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266
|
||||
|
||||
#define IMX8MQ_SYS1_PLL_40M_CG 267
|
||||
#define IMX8MQ_SYS1_PLL_80M_CG 268
|
||||
#define IMX8MQ_SYS1_PLL_100M_CG 269
|
||||
#define IMX8MQ_SYS1_PLL_133M_CG 270
|
||||
#define IMX8MQ_SYS1_PLL_160M_CG 271
|
||||
#define IMX8MQ_SYS1_PLL_200M_CG 272
|
||||
#define IMX8MQ_SYS1_PLL_266M_CG 273
|
||||
#define IMX8MQ_SYS1_PLL_400M_CG 274
|
||||
#define IMX8MQ_SYS1_PLL_800M_CG 275
|
||||
#define IMX8MQ_SYS2_PLL_50M_CG 276
|
||||
#define IMX8MQ_SYS2_PLL_100M_CG 277
|
||||
#define IMX8MQ_SYS2_PLL_125M_CG 278
|
||||
#define IMX8MQ_SYS2_PLL_166M_CG 279
|
||||
#define IMX8MQ_SYS2_PLL_200M_CG 280
|
||||
#define IMX8MQ_SYS2_PLL_250M_CG 281
|
||||
#define IMX8MQ_SYS2_PLL_333M_CG 282
|
||||
#define IMX8MQ_SYS2_PLL_500M_CG 283
|
||||
#define IMX8MQ_SYS2_PLL_1000M_CG 284
|
||||
|
||||
#define IMX8MQ_CLK_GPU_CORE 285
|
||||
#define IMX8MQ_CLK_GPU_SHADER 286
|
||||
#define IMX8MQ_CLK_M4_CORE 287
|
||||
#define IMX8MQ_CLK_VPU_CORE 288
|
||||
|
||||
#define IMX8MQ_CLK_A53_CORE 289
|
||||
|
||||
#define IMX8MQ_CLK_END 290
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
||||
|
||||
Reference in New Issue
Block a user