This commit is contained in:
Tom Rini
2016-04-01 08:17:55 -04:00
64 changed files with 1275 additions and 103 deletions

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@@ -43,12 +43,8 @@
#define AXP221_ALDO1_CTRL 0x28
#define AXP221_ALDO2_CTRL 0x29
#define AXP221_ALDO3_CTRL 0x2a
#define AXP221_VBUS_IPSOUT 0x30
#define AXP221_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP221_SHUTDOWN 0x32
#define AXP221_SHUTDOWN_POWEROFF (1 << 7)
#define AXP221_MISC_CTRL 0x8f
#define AXP221_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP221_PAGE 0xff
/* Page 1 addresses */
@@ -57,6 +53,10 @@
/* For axp_gpio.c */
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP_MISC_CTRL 0x8f
#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */

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@@ -41,6 +41,7 @@
#define AXP818_ELDO3_CTRL 0x1b
#define AXP818_FLDO1_CTRL 0x1c
#define AXP818_FLDO2_3_CTRL 0x1d
#define AXP818_FLDO2_3_CTRL_FLDO3_VOL (1 << 4)
#define AXP818_DCDC1_CTRL 0x20
#define AXP818_DCDC2_CTRL 0x21
#define AXP818_DCDC3_CTRL 0x22
@@ -53,11 +54,13 @@
#define AXP818_ALDO2_CTRL 0x29
#define AXP818_ALDO3_CTRL 0x2a
int axp818_init(void);
/* For axp_gpio.c */
#define AXP_POWER_STATUS 0x00
#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5)
#define AXP_VBUS_IPSOUT 0x30
#define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2)
#define AXP_MISC_CTRL 0x8f
#define AXP_MISC_CTRL_N_VBUSEN_FUNC (1 << 4)
#define AXP_GPIO0_CTRL 0x90
#define AXP_GPIO1_CTRL 0x92
#define AXP_GPIO_CTRL_OUTPUT_LOW 0x00 /* Drive pin low */

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@@ -31,6 +31,7 @@ int axp_set_aldo3(unsigned int mvolt);
int axp_set_aldo4(unsigned int mvolt);
int axp_set_dldo(int dldo_num, unsigned int mvolt);
int axp_set_eldo(int eldo_num, unsigned int mvolt);
int axp_set_fldo(int fldo_num, unsigned int mvolt);
int axp_init(void);
int axp_get_sid(unsigned int *sid);

25
include/configs/sun50i.h Normal file
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@@ -0,0 +1,25 @@
/*
* Configuration settings for the Allwinner A64 (sun50i) CPU
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* A64 specific configuration
*/
#define CONFIG_SUNXI_USB_PHYS 1
#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ
#define GICD_BASE 0x1c81000
#define GICC_BASE 0x1c82000
/*
* Include common sunxi configuration where most the settings are
*/
#include <configs/sunxi-common.h>
#endif /* __CONFIG_H */

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@@ -25,7 +25,6 @@
#define CONFIG_ARMV7_PSCI 1
#define CONFIG_ARMV7_PSCI_NR_CPUS 4
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_TIMER_CLK_FREQ 24000000
/*
* Include common sunxi configuration where most the settings are

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@@ -22,7 +22,6 @@
#define CONFIG_ARMV7_PSCI 1
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_TIMER_CLK_FREQ 24000000
/*
* Include common sunxi configuration where most the settings are

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@@ -20,6 +20,8 @@
#ifdef CONFIG_MACH_SUN8I_H3
#define CONFIG_SUNXI_USB_PHYS 4
#elif defined CONFIG_MACH_SUN8I_A83T
#define CONFIG_SUNXI_USB_PHYS 3
#else
#define CONFIG_SUNXI_USB_PHYS 2
#endif
@@ -38,8 +40,6 @@
#endif
#endif
#define CONFIG_TIMER_CLK_FREQ 24000000
/*
* Include common sunxi configuration where most the settings are
*/

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@@ -56,6 +56,7 @@
/* CPU */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_TIMER_CLK_FREQ 24000000
/*
* The DRAM Base differs between some models. We cannot use macros for the
@@ -90,7 +91,7 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
#ifdef CONFIG_MACH_SUN9I
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
/*
* The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
* slightly bigger. Note that it is possible to map the first 32 KiB of the
@@ -99,7 +100,7 @@
* the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
#define CONFIG_SYS_INIT_RAM_SIZE 0x0a000 /* 40 KiB */
#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
@@ -188,8 +189,16 @@
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#if defined(CONFIG_MACH_SUN9I)
#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* ? KiB on sun9i */
#elif defined(CONFIG_MACH_SUN50I)
#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x7fe0 /* 32 KiB on sun50i */
#else
#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */
#endif
#define CONFIG_SPL_LIBDISK_SUPPORT
@@ -197,14 +206,22 @@
#define CONFIG_SPL_MMC_SUPPORT
#endif
#ifndef CONFIG_ARM64
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
#endif
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
/* FIXME: 40 KiB instead of 32 KiB ? */
#define LOW_LEVEL_SRAM_STACK 0x00018000
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#else
/* end of 32 KiB in sram */
#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
#endif
/* I2C */
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \