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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

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This commit is contained in:
Tom Rini
2013-05-02 19:54:32 -04:00
parent e3288e1d15 9e186857c7
commit 3fe0128540
28 changed files with 833 additions and 72 deletions
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3
arch/powerpc/cpu/mpc85xx/cmd_errata.c
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@@ -254,6 +254,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
puts("Work-around for Erratum PCIe-A003 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
return 0;
}

18
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@@ -281,14 +281,6 @@ unsigned long get_tbclk (void)
#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
int re_enable = disable_interrupts();
reset_85xx_watchdog();
if (re_enable) enable_interrupts();
}
void
reset_85xx_watchdog(void)
{
@@ -297,6 +289,16 @@ reset_85xx_watchdog(void)
*/
mtspr(SPRN_TSR, TSR_WIS);
}
void
watchdog_reset(void)
{
int re_enable = disable_interrupts();
reset_85xx_watchdog();
if (re_enable)
enable_interrupts();
}
#endif /* CONFIG_WATCHDOG */
/*

14
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@@ -623,6 +623,20 @@ skip_l2:
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
/* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
* multi-bit ECC errors which has impact on performance, so software
* should disable all ECC reporting from USB1 and USB2.
*/
if (IS_SVR_REV(get_svr(), 1, 0)) {
struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
(CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
setbits_be32(&dcfg->ecccr1,
(DCSR_DCFG_ECC_DISABLE_USB1 |
DCSR_DCFG_ECC_DISABLE_USB2));
}
#endif
#ifdef CONFIG_FMAN_ENET
fman_enet_init();
#endif

7
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@@ -663,6 +663,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_CORENET
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2",
"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
do_fixup_by_compat_u32(blob, "fsl,mpic",
"clock-frequency", get_bus_freq(0)/2, 1);
#else
do_fixup_by_compat_u32(blob, "fsl,mpic",
"clock-frequency", get_bus_freq(0), 1);
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);

4
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View File

@@ -103,6 +103,10 @@ static const struct {
{ 22, 168, FSL_SRDS_BANK_3 },
{ 23, 169, FSL_SRDS_BANK_3 },
#endif
#if SRDS_MAX_BANK > 3
{ 24, 175, FSL_SRDS_BANK_4 },
{ 25, 176, FSL_SRDS_BANK_4 },
#endif
};
int serdes_get_lane_idx(int lane)

20
arch/powerpc/cpu/mpc85xx/p2041_ids.c
View File

@@ -27,16 +27,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 2),
SET_QP_INFO(7, 8, 4, 3),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 1, 1),
SET_QP_INFO(13, 14, 2, 2),
SET_QP_INFO(15, 16, 3, 3),
SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 2),
SET_QP_INFO(7, 8, 4, 3),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 6, 1),
SET_QP_INFO(13, 14, 7, 2),
SET_QP_INFO(15, 16, 8, 3),
SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
};
#endif

20
arch/powerpc/cpu/mpc85xx/p3041_ids.c
View File

@@ -27,16 +27,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 2),
SET_QP_INFO(7, 8, 4, 3),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 1, 1),
SET_QP_INFO(13, 14, 2, 2),
SET_QP_INFO(15, 16, 3, 3),
SET_QP_INFO(17, 18, 4, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 5, 0), /* for now sdest to 0 */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 2),
SET_QP_INFO(7, 8, 4, 3),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(1, 12, 6, 1),
SET_QP_INFO(13, 14, 7, 2),
SET_QP_INFO(15, 16, 8, 3),
SET_QP_INFO(17, 18, 9, 0), /* for now sdest to 0 */
SET_QP_INFO(19, 20, 10, 0), /* for now sdest to 0 */
};
#endif

20
arch/powerpc/cpu/mpc85xx/p5020_ids.c
View File

@@ -27,16 +27,16 @@
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 0),
SET_QP_INFO(7, 8, 4, 1),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 1, 1),
SET_QP_INFO(13, 14, 2, 0),
SET_QP_INFO(15, 16, 3, 1),
SET_QP_INFO(17, 18, 4, 0),
SET_QP_INFO(19, 20, 5, 1),
SET_QP_INFO(1, 2, 1, 0),
SET_QP_INFO(3, 4, 2, 1),
SET_QP_INFO(5, 6, 3, 0),
SET_QP_INFO(7, 8, 4, 1),
SET_QP_INFO(9, 10, 5, 0),
SET_QP_INFO(11, 12, 6, 1),
SET_QP_INFO(13, 14, 7, 0),
SET_QP_INFO(15, 16, 8, 1),
SET_QP_INFO(17, 18, 9, 0),
SET_QP_INFO(19, 20, 10, 1),
};
#endif

20
arch/powerpc/cpu/mpc85xx/portals.c
View File

@@ -30,11 +30,9 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
static ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
void setup_portals(void)
{
ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
#ifdef CONFIG_FSL_CORENET
int i;
@@ -166,6 +164,20 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
num = get_dpaa_liodn(dev, &liodns[0], id);
ret = fdt_setprop(blob, childoff, "fsl,liodn",
&liodns[0], sizeof(u32) * num);
if (!strncmp(name, "pme", 3)) {
u32 pme_rev1, pme_rev2;
ccsr_pme_t *pme_regs =
(void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
ret = fdt_setprop(blob, childoff,
"fsl,pme-rev1", &pme_rev1, sizeof(u32));
if (ret < 0)
return ret;
ret = fdt_setprop(blob, childoff,
"fsl,pme-rev2", &pme_rev2, sizeof(u32));
}
#endif
} else {
return childoff;
@@ -183,6 +195,7 @@ void fdt_fixup_qportals(void *blob)
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
u32 rev_1 = in_be32(&qman->ip_rev_1);
u32 rev_2 = in_be32(&qman->ip_rev_2);
char compat[64];
@@ -272,6 +285,7 @@ void fdt_fixup_bportals(void *blob)
int off, err;
unsigned int maj, min;
unsigned int ip_cfg;
ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
u32 rev_1 = in_be32(&bman->ip_rev_1);
u32 rev_2 = in_be32(&bman->ip_rev_2);
char compat[64];

12
arch/powerpc/include/asm/config_mpc85xx.h
View File

@@ -333,7 +333,9 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -365,7 +367,9 @@
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -442,6 +446,8 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
@@ -473,7 +479,7 @@
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_USB138
#define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_ERRATUM_A004699
@@ -490,7 +496,6 @@
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#elif defined(CONFIG_BSC9132)
@@ -503,7 +508,6 @@
#define CONFIG_NUM_DDR_CONTROLLERS 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
@@ -560,6 +564,7 @@
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#elif defined(CONFIG_PPC_B4860)
@@ -585,6 +590,7 @@
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#else

4
arch/powerpc/include/asm/fsl_memac.h
View File

@@ -222,6 +222,10 @@ struct memac {
/* IF_MODE - Interface Mode Register */
#define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
#define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */
#define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */
#define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */
#define IF_MODE_SETSP_MASK 0x00006000 /* setsp mask bits */
#define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
#define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
#define IF_MODE_MASK 0x00000003 /* mask for mode interface mode */

12
arch/powerpc/include/asm/immap_85xx.h
View File

@@ -2914,7 +2914,8 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
&& !defined(CONFIG_PPC_B4420)
#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
@@ -3160,4 +3161,13 @@ struct ccsr_cluster_l2 {
#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
struct dcsr_dcfg_regs {
u8 res_0[0x520];
u32 ecccr1;
#define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
#endif /*__IMMAP_85xx__*/