From 336a27ab1d3659c7e1dd6a48e017f5074be70eca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 29 Jul 2022 13:29:06 +0200 Subject: [PATCH 01/25] arm: mvebu: turris_omnia: Show MCU type in show_board_info() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Different Turris Omnia HW board revisions contains different MCU. Show type in show_board_info() to easily identify which MCU is populated. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Reviewed-by: Marek Behún --- board/CZ.NIC/turris_omnia/turris_omnia.c | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 5921769f1e..dab5711cf0 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -62,13 +62,27 @@ enum mcu_commands { CMD_GET_STATUS_WORD = 0x01, CMD_GET_RESET = 0x09, CMD_WATCHDOG_STATE = 0x0b, + + /* available if STS_FEATURES_SUPPORTED bit set in status word */ + CMD_GET_FEATURES = 0x10, }; enum status_word_bits { + STS_MCU_TYPE_MASK = GENMASK(1, 0), + STS_MCU_TYPE_STM32 = 0, + STS_MCU_TYPE_GD32 = 1, + STS_MCU_TYPE_MKL = 2, + STS_MCU_TYPE_UNKN = 3, + STS_FEATURES_SUPPORTED = BIT(2), CARD_DET_STSBIT = 0x0010, MSATA_IND_STSBIT = 0x0020, }; +/* CMD_GET_FEATURES */ +enum features_e { + FEAT_PERIPH_MCU = BIT(0), +}; + /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-2014_T3.0" @@ -371,6 +385,36 @@ static int omnia_get_ram_size_gb(void) return ram_size; } +static const char * const omnia_get_mcu_type(void) +{ + static const char * const mcu_types[] = { + [STS_MCU_TYPE_STM32] = "STM32", + [STS_MCU_TYPE_GD32] = "GD32", + [STS_MCU_TYPE_MKL] = "MKL", + [STS_MCU_TYPE_UNKN] = "unknown", + }; + static const char * const mcu_types_with_perip_resets[] = { + [STS_MCU_TYPE_STM32] = "STM32 (with peripheral resets)", + [STS_MCU_TYPE_GD32] = "GD32 (with peripheral resets)", + [STS_MCU_TYPE_MKL] = "MKL (with peripheral resets)", + [STS_MCU_TYPE_UNKN] = "unknown (with peripheral resets)", + }; + u16 stsword, features; + int ret; + + ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword)); + if (ret) + return "unknown"; + + if (stsword & STS_FEATURES_SUPPORTED) { + ret = omnia_mcu_read(CMD_GET_FEATURES, &features, sizeof(features)); + if (ret == 0 && (features & FEAT_PERIPH_MCU)) + return mcu_types_with_perip_resets[stsword & STS_MCU_TYPE_MASK]; + } + + return mcu_types[stsword & STS_MCU_TYPE_MASK]; +} + /* * Define the DDR layout / topology here in the board file. This will * be used by the DDR3 init code in the SPL U-Boot version to configure @@ -688,6 +732,7 @@ int show_board_info(void) err = turris_atsha_otp_get_serial_number(&version_num, &serial_num); printf("Model: Turris Omnia\n"); + printf(" MCU type: %s\n", omnia_get_mcu_type()); printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024); if (err) printf(" Serial Number: unknown\n"); From 1da53ae26afc4f084cf35fea706090fa03dc8475 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 29 Jul 2022 13:29:07 +0200 Subject: [PATCH 02/25] arm: mvebu: turris_omnia: Add support for design with SW reset signals MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit New Turris Omnia HW board revision requires that software controls peripheral reset signals, namely PERST# signals on mPCIe slots, ethernet phy reset and lan switch reset. Those pins are connected to MCU controlled by MCU i2c API as GPIOs. On new HW board revision those pins stay in reset after board reset and software has to release these peripherals from reset manually. MCU announce this requirement by FEAT_PERIPH_MCU bit in CMD_GET_FEATURES command. On older HW board revisions when FEAT_PERIPH_MCU is not announced, all those reset signals are automatically released after board finish reset. Detect FEAT_PERIPH_MCU bit in board_fix_fdt() and ft_board_setup() functions and insert into device tree blob pcie "reset-gpios" and eth phy "phy-reset-gpios" properties with corresponding MCU gpio definitions. PCIe and eth PHY drivers then automatically release resets during device initialization. Both U-Boot and Linux kernel drivers support those device tree reset properties. Initialization of lan switch on new HW board revision is more complicated. Switch strapping pins are shared with switch RGMII pins. And strapping pins must be in specific configuration after releasing switch reset. Due to pin sharing, it is first required to switch A385 side of switch pins into GPIO mode, set strapping configuration, release switch from reset and after that switch A385 pins back to RGMII mode. Because this complicated setup is not supported by switch DSA drivers and cannot be expressed easily in device tree, implement it manually in SPL function spl_board_init(). So in proper U-Boot and OS/kernel would be lan switch initialized and be in same configuration like it was on old HW board revisions (where reset sequence did those steps at hardware level). Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Reviewed-by: Marek Behún --- board/CZ.NIC/turris_omnia/turris_omnia.c | 226 +++++++++++++++++++++++ 1 file changed, 226 insertions(+) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index dab5711cf0..a7c1c1fc79 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -19,9 +19,11 @@ #include #include #include +#include #include #include #include +#include #include #include "../drivers/ddr/marvell/a38x/ddr3_init.h" @@ -65,6 +67,9 @@ enum mcu_commands { /* available if STS_FEATURES_SUPPORTED bit set in status word */ CMD_GET_FEATURES = 0x10, + + /* available if EXT_CMD bit set in features */ + CMD_EXT_CONTROL = 0x12, }; enum status_word_bits { @@ -81,6 +86,16 @@ enum status_word_bits { /* CMD_GET_FEATURES */ enum features_e { FEAT_PERIPH_MCU = BIT(0), + FEAT_EXT_CMDS = BIT(1), +}; + +/* CMD_EXT_CONTROL */ +enum ext_ctl_e { + EXT_CTL_nRES_LAN = BIT(1), + EXT_CTL_nRES_PHY = BIT(2), + EXT_CTL_nPERST0 = BIT(3), + EXT_CTL_nPERST1 = BIT(4), + EXT_CTL_nPERST2 = BIT(5), }; /* @@ -543,6 +558,90 @@ static void handle_reset_button(void) } } +static void initialize_switch(void) +{ + u32 val, val04, val08, val10, val14; + u16 ctrl[2]; + int err; + + printf("Initializing LAN eth switch... "); + + /* Change RGMII pins to GPIO mode */ + + val = val04 = readl(MVEBU_MPP_BASE + 0x04); + val &= ~GENMASK(19, 16); /* MPP[12] := GPIO */ + val &= ~GENMASK(23, 20); /* MPP[13] := GPIO */ + val &= ~GENMASK(27, 24); /* MPP[14] := GPIO */ + val &= ~GENMASK(31, 28); /* MPP[15] := GPIO */ + writel(val, MVEBU_MPP_BASE + 0x04); + + val = val08 = readl(MVEBU_MPP_BASE + 0x08); + val &= ~GENMASK(3, 0); /* MPP[16] := GPIO */ + val &= ~GENMASK(23, 20); /* MPP[21] := GPIO */ + writel(val, MVEBU_MPP_BASE + 0x08); + + val = val10 = readl(MVEBU_MPP_BASE + 0x10); + val &= ~GENMASK(27, 24); /* MPP[38] := GPIO */ + val &= ~GENMASK(31, 28); /* MPP[39] := GPIO */ + writel(val, MVEBU_MPP_BASE + 0x10); + + val = val14 = readl(MVEBU_MPP_BASE + 0x14); + val &= ~GENMASK(3, 0); /* MPP[40] := GPIO */ + val &= ~GENMASK(7, 4); /* MPP[41] := GPIO */ + writel(val, MVEBU_MPP_BASE + 0x14); + + /* Set initial values for switch reset strapping pins */ + + val = readl(MVEBU_GPIO0_BASE + 0x00); + val |= BIT(12); /* GPIO[12] := 1 */ + val |= BIT(13); /* GPIO[13] := 1 */ + val |= BIT(14); /* GPIO[14] := 1 */ + val |= BIT(15); /* GPIO[15] := 1 */ + val &= ~BIT(16); /* GPIO[16] := 0 */ + val |= BIT(21); /* GPIO[21] := 1 */ + writel(val, MVEBU_GPIO0_BASE + 0x00); + + val = readl(MVEBU_GPIO1_BASE + 0x00); + val |= BIT(6); /* GPIO[38] := 1 */ + val |= BIT(7); /* GPIO[39] := 1 */ + val |= BIT(8); /* GPIO[40] := 1 */ + val &= ~BIT(9); /* GPIO[41] := 0 */ + writel(val, MVEBU_GPIO1_BASE + 0x00); + + val = readl(MVEBU_GPIO0_BASE + 0x04); + val &= ~BIT(12); /* GPIO[12] := Out Enable */ + val &= ~BIT(13); /* GPIO[13] := Out Enable */ + val &= ~BIT(14); /* GPIO[14] := Out Enable */ + val &= ~BIT(15); /* GPIO[15] := Out Enable */ + val &= ~BIT(16); /* GPIO[16] := Out Enable */ + val &= ~BIT(21); /* GPIO[21] := Out Enable */ + writel(val, MVEBU_GPIO0_BASE + 0x04); + + val = readl(MVEBU_GPIO1_BASE + 0x04); + val &= ~BIT(6); /* GPIO[38] := Out Enable */ + val &= ~BIT(7); /* GPIO[39] := Out Enable */ + val &= ~BIT(8); /* GPIO[40] := Out Enable */ + val &= ~BIT(9); /* GPIO[41] := Out Enable */ + writel(val, MVEBU_GPIO1_BASE + 0x04); + + /* Release switch reset */ + + ctrl[0] = EXT_CTL_nRES_LAN; + ctrl[1] = EXT_CTL_nRES_LAN; + err = omnia_mcu_write(CMD_EXT_CONTROL, ctrl, sizeof(ctrl)); + + mdelay(10); + + /* Change RGMII pins back to RGMII mode */ + + writel(val04, MVEBU_MPP_BASE + 0x04); + writel(val08, MVEBU_MPP_BASE + 0x08); + writel(val10, MVEBU_MPP_BASE + 0x10); + writel(val14, MVEBU_MPP_BASE + 0x14); + + puts(err ? "failed\n" : "done\n"); +} + int board_early_init_f(void) { /* Configure MPP */ @@ -572,6 +671,9 @@ int board_early_init_f(void) void spl_board_init(void) { + u16 val; + int ret; + /* * If booting from UART, disable MCU watchdog in SPL, since uploading * U-Boot proper can take too much time and trigger it. Instead enable @@ -581,6 +683,19 @@ void spl_board_init(void) enable_a385_watchdog(10); disable_mcu_watchdog(); } + + /* + * When MCU controls peripheral resets then release LAN eth switch from + * the reset and initialize it. When MCU does not control peripheral + * resets then LAN eth switch is initialized automatically by bootstrap + * pins when A385 is released from the reset. + */ + ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &val, sizeof(val)); + if (ret == 0 && (val & STS_FEATURES_SUPPORTED)) { + ret = omnia_mcu_read(CMD_GET_FEATURES, &val, sizeof(val)); + if (ret == 0 && (val & FEAT_PERIPH_MCU)) + initialize_switch(); + } } #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) || IS_ENABLED(CONFIG_OF_BOARD_SETUP) @@ -689,11 +804,109 @@ static void fixup_wwan_port_nodes(void *blob) disable_pcie_node(blob, 2); } +static int insert_mcu_gpio_prop(void *blob, int node, const char *prop, + unsigned int phandle, u32 bank, u32 gpio, + u32 flags) +{ + fdt32_t val[4] = { cpu_to_fdt32(phandle), cpu_to_fdt32(bank), + cpu_to_fdt32(gpio), cpu_to_fdt32(flags) }; + return fdt_setprop(blob, node, prop, &val, sizeof(val)); +} + +static int fixup_mcu_gpio_in_pcie_nodes(void *blob) +{ + unsigned int mcu_phandle; + int port, gpio; + int pcie_node; + int port_node; + int ret; + + ret = fdt_increase_size(blob, 128); + if (ret < 0) { + printf("Cannot increase FDT size!\n"); + return ret; + } + + mcu_phandle = fdt_create_phandle_by_compatible(blob, "cznic,turris-omnia-mcu"); + if (!mcu_phandle) + return -FDT_ERR_NOPHANDLES; + + fdt_for_each_node_by_compatible(pcie_node, blob, -1, "marvell,armada-370-pcie") { + if (!fdtdec_get_is_enabled(blob, pcie_node)) + continue; + + fdt_for_each_subnode(port_node, blob, pcie_node) { + if (!fdtdec_get_is_enabled(blob, port_node)) + continue; + + port = fdtdec_get_int(blob, port_node, "marvell,pcie-port", -1); + + if (port == 0) + gpio = ilog2(EXT_CTL_nPERST0); + else if (port == 1) + gpio = ilog2(EXT_CTL_nPERST1); + else if (port == 2) + gpio = ilog2(EXT_CTL_nPERST2); + else + continue; + + /* insert: reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */ + ret = insert_mcu_gpio_prop(blob, port_node, "reset-gpios", + mcu_phandle, 2, gpio, GPIO_ACTIVE_LOW); + if (ret < 0) + return ret; + } + } + + return 0; +} + +static int fixup_mcu_gpio_in_eth_wan_node(void *blob) +{ + unsigned int mcu_phandle; + int eth_wan_node; + int ret; + + ret = fdt_increase_size(blob, 64); + if (ret < 0) { + printf("Cannot increase FDT size!\n"); + return ret; + } + + eth_wan_node = fdt_path_offset(blob, "ethernet2"); + if (eth_wan_node < 0) + return eth_wan_node; + + mcu_phandle = fdt_create_phandle_by_compatible(blob, "cznic,turris-omnia-mcu"); + if (!mcu_phandle) + return -FDT_ERR_NOPHANDLES; + + /* insert: phy-reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */ + ret = insert_mcu_gpio_prop(blob, eth_wan_node, "phy-reset-gpios", + mcu_phandle, 2, ilog2(EXT_CTL_nRES_PHY), GPIO_ACTIVE_LOW); + if (ret < 0) + return ret; + + return 0; +} + #endif #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) int board_fix_fdt(void *blob) { + u16 val; + int ret; + + ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &val, sizeof(val)); + if (ret == 0 && (val & STS_FEATURES_SUPPORTED)) { + ret = omnia_mcu_read(CMD_GET_FEATURES, &val, sizeof(val)); + if (ret == 0 && (val & FEAT_PERIPH_MCU)) { + fixup_mcu_gpio_in_pcie_nodes(blob); + fixup_mcu_gpio_in_eth_wan_node(blob); + } + } + fixup_msata_port_nodes(blob); fixup_wwan_port_nodes(blob); @@ -840,6 +1053,19 @@ fail: int ft_board_setup(void *blob, struct bd_info *bd) { + int node; + + /* + * U-Boot's FDT blob contains phy-reset-gpios in ethernet2 + * node when MCU controls all peripherals resets. + * Fixup MCU GPIO nodes in PCIe and eth wan nodes in this case. + */ + node = fdt_path_offset(gd->fdt_blob, "ethernet2"); + if (node >= 0 && fdt_getprop(gd->fdt_blob, node, "phy-reset-gpios", NULL)) { + fixup_mcu_gpio_in_pcie_nodes(blob); + fixup_mcu_gpio_in_eth_wan_node(blob); + } + fixup_spi_nor_partitions(blob); fixup_msata_port_nodes(blob); fixup_wwan_port_nodes(blob); From 37af2c7b296c66bd463943a3193df3c5e085a738 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 1 Aug 2022 12:02:19 +0200 Subject: [PATCH 03/25] arm: mvebu: turris_omnia: Do not fail in fixup_mtd_partitions when partitions do not exist MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All partitions are created by fixup_mtd_partitions() function, so they do not have to exist just for their removal need. Fixes: 92f36c8e74c1 ("arm: mvebu: turris_omnia: fixup MTD partitions in Linux' DTB") Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Reviewed-by: Marek Behún --- board/CZ.NIC/turris_omnia/turris_omnia.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index a7c1c1fc79..796c55f3c6 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -974,11 +974,10 @@ static bool fixup_mtd_partitions(void *blob, int offset, struct mtd_info *mtd) int parts; parts = fdt_subnode_offset(blob, offset, "partitions"); - if (parts < 0) - return false; - - if (fdt_del_node(blob, parts) < 0) - return false; + if (parts >= 0) { + if (fdt_del_node(blob, parts) < 0) + return false; + } parts = fdt_add_subnode(blob, offset, "partitions"); if (parts < 0) From e6c5e975b53958f7780746648363187d23aea358 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 1 Aug 2022 12:02:20 +0200 Subject: [PATCH 04/25] arm: mvebu: turris_omnia: Increase fdt size in fixup_mtd_partitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sometimes fixup_mtd_partitions() prints during booting kernel error "Failed fixing SPI NOR partitions!" because it does not have enough space for creating all paritions nodes. So increase fdt size. Fixes: 92f36c8e74c1 ("arm: mvebu: turris_omnia: fixup MTD partitions in Linux' DTB") Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Reviewed-by: Marek Behún --- board/CZ.NIC/turris_omnia/turris_omnia.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 796c55f3c6..98bad11537 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -979,6 +979,9 @@ static bool fixup_mtd_partitions(void *blob, int offset, struct mtd_info *mtd) return false; } + if (fdt_increase_size(blob, 512) < 0) + return false; + parts = fdt_add_subnode(blob, offset, "partitions"); if (parts < 0) return false; From c959374e841de4c9d2317ff3f110f03574e7db79 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 1 Aug 2022 12:11:13 +0200 Subject: [PATCH 05/25] gpio: turris_omnia_mcu: Fix usage of CMD_EXT_CONTROL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CMD_GENERAL_CONTROL takes two 8-bit arguments but CMD_EXT_CONTROL takes two 16-bit arguments. Fix this issue and change CMD_EXT_CONTROL arguments to 16-bit. Fixes: 5e4d24ccc115 ("gpio: Add Turris Omnia MCU driver") Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/gpio/turris_omnia_mcu.c | 56 +++++++++++++++------------------ 1 file changed, 26 insertions(+), 30 deletions(-) diff --git a/drivers/gpio/turris_omnia_mcu.c b/drivers/gpio/turris_omnia_mcu.c index 3e5d74e62c..986ccde6bc 100644 --- a/drivers/gpio/turris_omnia_mcu.c +++ b/drivers/gpio/turris_omnia_mcu.c @@ -137,48 +137,44 @@ static int turris_omnia_mcu_get_value(struct udevice *dev, uint offset) static int turris_omnia_mcu_set_value(struct udevice *dev, uint offset, int value) { struct turris_omnia_mcu_info *info = dev_get_plat(dev); - u8 val[2]; - int ret; - u8 reg; + u8 val16[2]; + u8 val32[4]; switch (offset) { /* bank 0 */ - case ilog2(STS_USB30_PWRON): - reg = CMD_GENERAL_CONTROL; - val[1] = CTL_USB30_PWRON; - break; - case ilog2(STS_USB31_PWRON): - reg = CMD_GENERAL_CONTROL; - val[1] = CTL_USB31_PWRON; - break; - case ilog2(STS_ENABLE_4V5): - reg = CMD_GENERAL_CONTROL; - val[1] = CTL_ENABLE_4V5; - break; - case ilog2(STS_BUTTON_MODE): - reg = CMD_GENERAL_CONTROL; - val[1] = CTL_BUTTON_MODE; - break; + case 0 ... 15: + switch (offset) { + case ilog2(STS_USB30_PWRON): + val16[1] = CTL_USB30_PWRON; + break; + case ilog2(STS_USB31_PWRON): + val16[1] = CTL_USB31_PWRON; + break; + case ilog2(STS_ENABLE_4V5): + val16[1] = CTL_ENABLE_4V5; + break; + case ilog2(STS_BUTTON_MODE): + val16[1] = CTL_BUTTON_MODE; + break; + default: + return -EINVAL; + } + val16[0] = value ? val16[1] : 0; + return dm_i2c_write(dev, CMD_GENERAL_CONTROL, val16, sizeof(val16)); /* bank 2 - supported only when FEAT_EXT_CMDS is set */ case (16 + 32 + 0) ... (16 + 32 + 15): if (!(info->features & FEAT_EXT_CMDS)) return -EINVAL; - reg = CMD_EXT_CONTROL; - val[1] = BIT(offset - 16 - 32); - break; + val32[3] = BIT(offset - 16 - 32) >> 8; + val32[2] = BIT(offset - 16 - 32) & 0xff; + val32[1] = value ? val32[3] : 0; + val32[0] = value ? val32[2] : 0; + return dm_i2c_write(dev, CMD_EXT_CONTROL, val32, sizeof(val32)); default: return -EINVAL; } - - val[0] = value ? val[1] : 0; - - ret = dm_i2c_write(dev, reg, val, 2); - if (ret) - return ret; - - return 0; } static int turris_omnia_mcu_direction_input(struct udevice *dev, uint offset) From 7cd67018dd7f754c66cf08a76397bbee254b32aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 1 Aug 2022 23:58:42 +0200 Subject: [PATCH 06/25] arm: mvebu: turris_omnia: Remove hardcoded spi-nor device tree path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux kernel DTS files renamed spi-nor@0 node to flash@0 which effectively broke U-Boot to boot new Linux kernel versions correctly. So remove hardcoded spi-nor device tree path from Turris Omnia board code and replace it by searching for mtd node by compatible string. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- board/CZ.NIC/turris_omnia/turris_omnia.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 98bad11537..5ddd873d02 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -32,8 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define OMNIA_SPI_NOR_PATH "/soc/spi@10600/spi-nor@0" - #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0" #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a @@ -1030,14 +1028,22 @@ static bool fixup_mtd_partitions(void *blob, int offset, struct mtd_info *mtd) static void fixup_spi_nor_partitions(void *blob) { - struct mtd_info *mtd; + struct mtd_info *mtd = NULL; + char mtd_path[64]; int node; - mtd = get_mtd_device_nm(OMNIA_SPI_NOR_PATH); + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "jedec,spi-nor"); + if (node < 0) + goto fail; + + if (fdt_get_path(gd->fdt_blob, node, mtd_path, sizeof(mtd_path)) < 0) + goto fail; + + mtd = get_mtd_device_nm(mtd_path); if (IS_ERR_OR_NULL(mtd)) goto fail; - node = fdt_path_offset(blob, OMNIA_SPI_NOR_PATH); + node = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor"); if (node < 0) goto fail; From dfebc1b9087d003eea39fe2e641b75d1cbd23e89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 2 Aug 2022 11:55:19 +0200 Subject: [PATCH 07/25] arm: mvebu: spl: Always fallback to BootROM boot method MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BootROM boot method should always work so always add it as fallback method to spl_boot_list. In case U-Boot SPI driver fails it is better to try using BootROM than hanging as by default only one boot method is specified. Signed-off-by: Pali Rohár Tested-by: Tony Dinh Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/spl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 13c99913c3..bfcba2e73b 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -271,6 +271,13 @@ u32 spl_boot_device(void) } } +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + if (spl_boot_list[0] != BOOT_DEVICE_BOOTROM) + spl_boot_list[1] = BOOT_DEVICE_BOOTROM; +} + #else u32 spl_boot_device(void) From 46cd849851f80c6f14e66588745e0a1d713f63ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Wed, 3 Aug 2022 10:53:12 +0200 Subject: [PATCH 08/25] arm: mvebu: turris_omnia: Add Winbond SPI flash support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some new Omnia boards will come with Winbond SPI flash. Add to defconfig. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- configs/turris_omnia_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index ff16825fb4..0bf4b0a0d1 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -88,6 +88,7 @@ CONFIG_DM_MTD=y CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_MARVELL=y CONFIG_PHY_FIXED=y From 0e8b74addcde54ef154297d3bebd3d21f86c2199 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 5 Aug 2022 13:37:25 +0200 Subject: [PATCH 09/25] arm: mvebu: dts: Build only arch-compatible dts files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 64-bit Armada DTS files are not build correctly during compilation of 32-bit Armada boards and vice versa. So fix makefile build system to compile only those dts files which are compatible for the current build (64-bit Armada DTS files only for 64-bit builds and 32-bit Armada DTS files only for 32-bit builds). Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/dts/Makefile | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ceaa39e4b4..7330121dba 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -232,12 +232,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra210-p2571.dtb \ tegra210-p3450-0000.dtb +ifdef CONFIG_ARMADA_32BIT dtb-$(CONFIG_ARCH_MVEBU) += \ - armada-3720-db.dtb \ - armada-3720-espressobin.dtb \ - armada-3720-turris-mox.dtb \ - armada-3720-eDPU.dtb \ - armada-3720-uDPU.dtb \ armada-375-db.dtb \ armada-385-atl-x530.dtb \ armada-385-atl-x530DP.dtb \ @@ -247,12 +243,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-388-gp.dtb \ armada-388-helios4.dtb \ armada-38x-controlcenterdc.dtb \ - armada-7040-db-nand.dtb \ - armada-7040-db.dtb \ - armada-8040-clearfog-gt-8k.dtb \ - armada-8040-db.dtb \ - armada-8040-mcbin.dtb \ - armada-8040-puzzle-m801.dtb \ armada-xp-crs305-1g-4s.dtb \ armada-xp-crs305-1g-4s-bit.dtb \ armada-xp-crs326-24g-2s.dtb \ @@ -263,7 +253,20 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-gp.dtb \ armada-xp-maxbcm.dtb \ armada-xp-synology-ds414.dtb \ - armada-xp-theadorable.dtb \ + armada-xp-theadorable.dtb +else +dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-3720-db.dtb \ + armada-3720-espressobin.dtb \ + armada-3720-turris-mox.dtb \ + armada-3720-eDPU.dtb \ + armada-3720-uDPU.dtb \ + armada-7040-db-nand.dtb \ + armada-7040-db.dtb \ + armada-8040-clearfog-gt-8k.dtb \ + armada-8040-db.dtb \ + armada-8040-mcbin.dtb \ + armada-8040-puzzle-m801.dtb \ cn9130-db-A.dtb \ cn9130-db-B.dtb \ cn9131-db-A.dtb \ @@ -272,6 +275,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ cn9132-db-B.dtb \ cn9130-crb-A.dtb \ cn9130-crb-B.dtb +endif dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ From 8879258ec0d6856ee9af802c79bb906feff6a032 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 3 Aug 2022 13:00:50 +0200 Subject: [PATCH 10/25] arm: mvebu: Introduce mvebu-u-boot.dtsi for 32-bit Armada SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set u-boot,dm-pre-reloc for /soc/, /soc/internal-regs/ and &uart0 nodes as it is required on every 32-bit Armada SoCs. And set also u-boot,dm-pre-reloc for &spi0 when going to boot from SPI because otherwise SPL SPI drivers do not load. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Tested-by: Stefan Roese --- arch/arm/dts/mvebu-u-boot.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/arm/dts/mvebu-u-boot.dtsi diff --git a/arch/arm/dts/mvebu-u-boot.dtsi b/arch/arm/dts/mvebu-u-boot.dtsi new file mode 100644 index 0000000000..5538f95148 --- /dev/null +++ b/arch/arm/dts/mvebu-u-boot.dtsi @@ -0,0 +1,24 @@ +#include + +#ifdef CONFIG_ARMADA_32BIT + +/ { + soc { + u-boot,dm-pre-reloc; + internal-regs { + u-boot,dm-pre-reloc; + }; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +#ifdef CONFIG_SPL_SPI +&spi0 { + u-boot,dm-pre-reloc; +}; +#endif + +#endif From 5d4d1212f7a9bd179bad1774156ce5500316b2c6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 3 Aug 2022 13:00:51 +0200 Subject: [PATCH 11/25] arm: mvebu: Remove redundant u-boot, dm-pre-reloc from all 32-bit Armada SoCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace it by including of mvebu-u-boot.dtsi file. When board does not use -u-boot.dtsi then mvebu-u-boot.dtsi is included automatically by makefile scripts/Makefile.lib. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Tested-by: Stefan Roese --- arch/arm/dts/armada-370-xp.dtsi | 1 - arch/arm/dts/armada-375-db.dts | 3 --- arch/arm/dts/armada-375.dtsi | 2 -- arch/arm/dts/armada-385-atl-x530-u-boot.dtsi | 14 ++------------ arch/arm/dts/armada-385-db-88f6820-amc.dts | 3 --- .../dts/armada-385-turris-omnia-u-boot.dtsi | 8 +------- arch/arm/dts/armada-388-clearfog-u-boot.dtsi | 2 ++ arch/arm/dts/armada-388-gp.dts | 3 --- arch/arm/dts/armada-388-helios4-u-boot.dtsi | 2 ++ arch/arm/dts/armada-38x-controlcenterdc.dts | 4 ---- .../arm/dts/armada-38x-solidrun-microsom.dtsi | 1 - arch/arm/dts/armada-38x.dtsi | 2 -- .../dts/armada-xp-crs305-1g-4s-u-boot.dtsi | 13 ------------- arch/arm/dts/armada-xp-crs305-1g-4s.dtsi | 1 - .../dts/armada-xp-crs326-24g-2s-u-boot.dtsi | 13 ------------- arch/arm/dts/armada-xp-crs326-24g-2s.dtsi | 1 - .../armada-xp-crs328-4c-20s-4s-u-boot.dtsi | 13 ------------- arch/arm/dts/armada-xp-crs328-4c-20s-4s.dtsi | 1 - .../dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi | 12 +----------- arch/arm/dts/armada-xp-gp-u-boot.dtsi | 19 ------------------- arch/arm/dts/armada-xp-maxbcm.dts | 1 - .../dts/armada-xp-synology-ds414-u-boot.dtsi | 9 --------- arch/arm/dts/armada-xp-synology-ds414.dts | 1 - arch/arm/dts/armada-xp-theadorable.dts | 3 --- arch/arm/dts/armada-xp.dtsi | 1 - 25 files changed, 8 insertions(+), 125 deletions(-) delete mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi delete mode 100644 arch/arm/dts/armada-xp-crs326-24g-2s-u-boot.dtsi delete mode 100644 arch/arm/dts/armada-xp-crs328-4c-20s-4s-u-boot.dtsi delete mode 100644 arch/arm/dts/armada-xp-gp-u-boot.dtsi delete mode 100644 arch/arm/dts/armada-xp-synology-ds414-u-boot.dtsi diff --git a/arch/arm/dts/armada-370-xp.dtsi b/arch/arm/dts/armada-370-xp.dtsi index 4cd168c957..310f159cd5 100644 --- a/arch/arm/dts/armada-370-xp.dtsi +++ b/arch/arm/dts/armada-370-xp.dtsi @@ -102,7 +102,6 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; - u-boot,dm-pre-reloc; rtc: rtc@10300 { compatible = "marvell,orion-rtc"; diff --git a/arch/arm/dts/armada-375-db.dts b/arch/arm/dts/armada-375-db.dts index 343349b8fd..d778839006 100644 --- a/arch/arm/dts/armada-375-db.dts +++ b/arch/arm/dts/armada-375-db.dts @@ -86,10 +86,8 @@ * by default. */ status = "okay"; - u-boot,dm-pre-reloc; spi-flash@0 { - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; @@ -113,7 +111,6 @@ }; serial@12000 { - u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/armada-375.dtsi b/arch/arm/dts/armada-375.dtsi index fcb9245fd4..20a8c352b2 100644 --- a/arch/arm/dts/armada-375.dtsi +++ b/arch/arm/dts/armada-375.dtsi @@ -103,7 +103,6 @@ soc { compatible = "marvell,armada375-mbus", "simple-bus"; - u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <1>; controller = <&mbusc>; @@ -168,7 +167,6 @@ internal-regs { compatible = "simple-bus"; - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; diff --git a/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi b/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi index 79b694cb84..4a3fb2ce40 100644 --- a/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi +++ b/arch/arm/dts/armada-385-atl-x530-u-boot.dtsi @@ -1,17 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 -&spi1 { - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - }; -}; - -&uart0 { - u-boot,dm-pre-reloc; -}; - &watchdog { u-boot,dm-pre-reloc; }; + +#include "mvebu-u-boot.dtsi" diff --git a/arch/arm/dts/armada-385-db-88f6820-amc.dts b/arch/arm/dts/armada-385-db-88f6820-amc.dts index 59a425f6b1..1a2d79d758 100644 --- a/arch/arm/dts/armada-385-db-88f6820-amc.dts +++ b/arch/arm/dts/armada-385-db-88f6820-amc.dts @@ -53,7 +53,6 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; - u-boot,dm-pre-reloc; }; @@ -114,10 +113,8 @@ pinctrl-names = "default"; pinctrl-0 = <&spi1_pins>; status = "okay"; - u-boot,dm-pre-reloc; spi-flash@0 { - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi index ec12298fd4..3f1e761a95 100644 --- a/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi +++ b/arch/arm/dts/armada-385-turris-omnia-u-boot.dtsi @@ -37,11 +37,7 @@ #ifdef CONFIG_ENV_IS_IN_SPI_FLASH &spi0 { - u-boot,dm-pre-reloc; - flash@0 { - u-boot,dm-pre-reloc; - partitions { partition@0 { reg = <0x0 CONFIG_ENV_OFFSET>; @@ -56,6 +52,4 @@ }; #endif -&uart0 { - u-boot,dm-pre-reloc; -}; +#include "mvebu-u-boot.dtsi" diff --git a/arch/arm/dts/armada-388-clearfog-u-boot.dtsi b/arch/arm/dts/armada-388-clearfog-u-boot.dtsi index 20f5c8fb8c..96629294be 100644 --- a/arch/arm/dts/armada-388-clearfog-u-boot.dtsi +++ b/arch/arm/dts/armada-388-clearfog-u-boot.dtsi @@ -35,3 +35,5 @@ u-boot,dm-spl; }; }; + +#include "mvebu-u-boot.dtsi" diff --git a/arch/arm/dts/armada-388-gp.dts b/arch/arm/dts/armada-388-gp.dts index d59aa5f232..f5345fb1aa 100644 --- a/arch/arm/dts/armada-388-gp.dts +++ b/arch/arm/dts/armada-388-gp.dts @@ -71,12 +71,10 @@ pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; status = "okay"; - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <0>; spi-flash@0 { - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p128", "jedec,spi-nor"; @@ -132,7 +130,6 @@ pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; status = "okay"; - u-boot,dm-pre-reloc; }; /* GE1 CON15 */ diff --git a/arch/arm/dts/armada-388-helios4-u-boot.dtsi b/arch/arm/dts/armada-388-helios4-u-boot.dtsi index 1047c1af23..bac4b06058 100644 --- a/arch/arm/dts/armada-388-helios4-u-boot.dtsi +++ b/arch/arm/dts/armada-388-helios4-u-boot.dtsi @@ -42,3 +42,5 @@ u-boot,dm-spl; }; }; + +#include "mvebu-u-boot.dtsi" diff --git a/arch/arm/dts/armada-38x-controlcenterdc.dts b/arch/arm/dts/armada-38x-controlcenterdc.dts index 5063a798df..b5d76f8b22 100644 --- a/arch/arm/dts/armada-38x-controlcenterdc.dts +++ b/arch/arm/dts/armada-38x-controlcenterdc.dts @@ -24,10 +24,6 @@ u-boot,dm-pre-reloc; }; -&uart0 { - u-boot,dm-pre-reloc; -}; - &uart1 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi index 9bbeafc53b..f6ae784bed 100644 --- a/arch/arm/dts/armada-38x-solidrun-microsom.dtsi +++ b/arch/arm/dts/armada-38x-solidrun-microsom.dtsi @@ -96,7 +96,6 @@ pinctrl-0 = <&uart0_pins>; pinctrl-names = "default"; status = "okay"; - u-boot,dm-pre-reloc; }; &i2c0 { diff --git a/arch/arm/dts/armada-38x.dtsi b/arch/arm/dts/armada-38x.dtsi index 3e970097c8..cf7ac4a90c 100644 --- a/arch/arm/dts/armada-38x.dtsi +++ b/arch/arm/dts/armada-38x.dtsi @@ -35,7 +35,6 @@ soc { compatible = "marvell,armada380-mbus", "simple-bus"; - u-boot,dm-pre-reloc; #address-cells = <2>; #size-cells = <1>; controller = <&mbusc>; @@ -100,7 +99,6 @@ internal-regs { compatible = "simple-bus"; - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi b/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi deleted file mode 100644 index 8576a02730..0000000000 --- a/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -&uart0 { - u-boot,dm-pre-reloc; -}; - -&spi0 { - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - }; -}; diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s.dtsi b/arch/arm/dts/armada-xp-crs305-1g-4s.dtsi index 1a74ecd5b5..d09cd47742 100644 --- a/arch/arm/dts/armada-xp-crs305-1g-4s.dtsi +++ b/arch/arm/dts/armada-xp-crs305-1g-4s.dtsi @@ -19,7 +19,6 @@ /dts-v1/; #include "armada-xp-98dx3236.dtsi" -#include "armada-xp-crs305-1g-4s-u-boot.dtsi" / { model = "CRS305-1G-4S+"; diff --git a/arch/arm/dts/armada-xp-crs326-24g-2s-u-boot.dtsi b/arch/arm/dts/armada-xp-crs326-24g-2s-u-boot.dtsi deleted file mode 100644 index 8576a02730..0000000000 --- a/arch/arm/dts/armada-xp-crs326-24g-2s-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -&uart0 { - u-boot,dm-pre-reloc; -}; - -&spi0 { - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - }; -}; diff --git a/arch/arm/dts/armada-xp-crs326-24g-2s.dtsi b/arch/arm/dts/armada-xp-crs326-24g-2s.dtsi index e50f3ead13..35b432ffb5 100644 --- a/arch/arm/dts/armada-xp-crs326-24g-2s.dtsi +++ b/arch/arm/dts/armada-xp-crs326-24g-2s.dtsi @@ -19,7 +19,6 @@ /dts-v1/; #include "armada-xp-98dx3236.dtsi" -#include "armada-xp-crs326-24g-2s-u-boot.dtsi" / { model = "CRS326-24G-2S+"; diff --git a/arch/arm/dts/armada-xp-crs328-4c-20s-4s-u-boot.dtsi b/arch/arm/dts/armada-xp-crs328-4c-20s-4s-u-boot.dtsi deleted file mode 100644 index 8576a02730..0000000000 --- a/arch/arm/dts/armada-xp-crs328-4c-20s-4s-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -&uart0 { - u-boot,dm-pre-reloc; -}; - -&spi0 { - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - }; -}; diff --git a/arch/arm/dts/armada-xp-crs328-4c-20s-4s.dtsi b/arch/arm/dts/armada-xp-crs328-4c-20s-4s.dtsi index daff1af2a2..63586b63a8 100644 --- a/arch/arm/dts/armada-xp-crs328-4c-20s-4s.dtsi +++ b/arch/arm/dts/armada-xp-crs328-4c-20s-4s.dtsi @@ -19,7 +19,6 @@ /dts-v1/; #include "armada-xp-98dx3236.dtsi" -#include "armada-xp-crs328-4c-20s-4s-u-boot.dtsi" / { model = "CRS328-4C-20S-4S+"; diff --git a/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi b/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi index fdbe168a87..dc20643bfa 100644 --- a/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi +++ b/arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi @@ -1,9 +1,5 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -&uart0 { - u-boot,dm-pre-reloc; -}; - &nand_controller { compatible="marvell,armada370-nand-controller"; status = "okay"; @@ -15,10 +11,4 @@ nand-ecc-step-size = <512>; }; -&spi0 { - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - }; -}; +#include "mvebu-u-boot.dtsi" diff --git a/arch/arm/dts/armada-xp-gp-u-boot.dtsi b/arch/arm/dts/armada-xp-gp-u-boot.dtsi deleted file mode 100644 index 2422856616..0000000000 --- a/arch/arm/dts/armada-xp-gp-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -/ { - soc { - internal-regs { - serial@12000 { - u-boot,dm-pre-reloc; - }; - }; - }; -}; - -&spi0 { - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - }; -}; diff --git a/arch/arm/dts/armada-xp-maxbcm.dts b/arch/arm/dts/armada-xp-maxbcm.dts index d2b07f74cf..b0b04842cc 100644 --- a/arch/arm/dts/armada-xp-maxbcm.dts +++ b/arch/arm/dts/armada-xp-maxbcm.dts @@ -151,7 +151,6 @@ internal-regs { serial@12000 { status = "okay"; - u-boot,dm-pre-reloc; }; serial@12100 { status = "okay"; diff --git a/arch/arm/dts/armada-xp-synology-ds414-u-boot.dtsi b/arch/arm/dts/armada-xp-synology-ds414-u-boot.dtsi deleted file mode 100644 index 22fae16c9d..0000000000 --- a/arch/arm/dts/armada-xp-synology-ds414-u-boot.dtsi +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ - -&spi0 { - u-boot,dm-pre-reloc; - - spi-flash@0 { - u-boot,dm-pre-reloc; - }; -}; diff --git a/arch/arm/dts/armada-xp-synology-ds414.dts b/arch/arm/dts/armada-xp-synology-ds414.dts index 35909e3c69..fdc9b47bdd 100644 --- a/arch/arm/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/dts/armada-xp-synology-ds414.dts @@ -78,7 +78,6 @@ */ serial@12000 { status = "okay"; - u-boot,dm-pre-reloc; }; /* Connected to a Microchip PIC16F883 for power control */ diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts index a06a65af15..2f6aa194cf 100644 --- a/arch/arm/dts/armada-xp-theadorable.dts +++ b/arch/arm/dts/armada-xp-theadorable.dts @@ -88,7 +88,6 @@ internal-regs { serial@12000 { status = "okay"; - u-boot,dm-pre-reloc; }; serial@12100 { @@ -170,10 +169,8 @@ &spi0 { status = "okay"; - u-boot,dm-pre-reloc; spi-flash@0 { - u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "n25q128a13", "jedec,spi-nor"; diff --git a/arch/arm/dts/armada-xp.dtsi b/arch/arm/dts/armada-xp.dtsi index fb5640bbd9..3bd72f1739 100644 --- a/arch/arm/dts/armada-xp.dtsi +++ b/arch/arm/dts/armada-xp.dtsi @@ -29,7 +29,6 @@ soc { compatible = "marvell,armadaxp-mbus", "simple-bus"; - u-boot,dm-pre-reloc; bootrom { compatible = "marvell,bootrom"; From e49a55af8b6ad632520b4d625330ad8797ae98ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 3 Aug 2022 13:00:52 +0200 Subject: [PATCH 12/25] arm: mvebu: armada-xp-theadorable.dts: Move u-boot, dm-pre-reloc to -u-boot.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move U-Boot specific device tree property u-boot,dm-pre-reloc into U-Boot specific device tree include file armada-xp-theadorable-u-boot.dtsi. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Tested-by: Stefan Roese --- arch/arm/dts/armada-xp-theadorable-u-boot.dtsi | 5 +++++ arch/arm/dts/armada-xp-theadorable.dts | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/armada-xp-theadorable-u-boot.dtsi diff --git a/arch/arm/dts/armada-xp-theadorable-u-boot.dtsi b/arch/arm/dts/armada-xp-theadorable-u-boot.dtsi new file mode 100644 index 0000000000..c98bfa1e18 --- /dev/null +++ b/arch/arm/dts/armada-xp-theadorable-u-boot.dtsi @@ -0,0 +1,5 @@ +&lcd0 { + u-boot,dm-pre-reloc; +}; + +#include "mvebu-u-boot.dtsi" diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts index 2f6aa194cf..ba73386d4f 100644 --- a/arch/arm/dts/armada-xp-theadorable.dts +++ b/arch/arm/dts/armada-xp-theadorable.dts @@ -134,7 +134,6 @@ compatible = "marvell,armada-xp-lcd"; reg = <0xe0000 0x10000>; status = "okay"; - u-boot,dm-pre-reloc; display-timings { native-mode = <&timing0>; From c8ef618ae1ab00bb491c14449f44c92047ede3d7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 3 Aug 2022 13:00:53 +0200 Subject: [PATCH 13/25] arm: mvebu: armada-38x-controlcenterdc.dts: Move u-boot, dm-pre-reloc to -u-boot.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move U-Boot specific device tree property u-boot,dm-pre-reloc into U-Boot specific device tree include file armada-38x-controlcenterdc-u-boot.dtsi. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- .../armada-38x-controlcenterdc-u-boot.dtsi | 25 +++++++++++++++++++ arch/arm/dts/armada-38x-controlcenterdc.dts | 16 ------------ 2 files changed, 25 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/armada-38x-controlcenterdc-u-boot.dtsi diff --git a/arch/arm/dts/armada-38x-controlcenterdc-u-boot.dtsi b/arch/arm/dts/armada-38x-controlcenterdc-u-boot.dtsi new file mode 100644 index 0000000000..0a94df9230 --- /dev/null +++ b/arch/arm/dts/armada-38x-controlcenterdc-u-boot.dtsi @@ -0,0 +1,25 @@ +&gpio0 { + u-boot,dm-pre-reloc; +}; + +&gpio1 { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +&spi1 { + u-boot,dm-pre-reloc; +}; + +&I2C0 { + u-boot,dm-pre-reloc; +}; + +&PCA22 { + u-boot,dm-pre-reloc; +}; + +#include "mvebu-u-boot.dtsi" diff --git a/arch/arm/dts/armada-38x-controlcenterdc.dts b/arch/arm/dts/armada-38x-controlcenterdc.dts index b5d76f8b22..79ea6f0909 100644 --- a/arch/arm/dts/armada-38x-controlcenterdc.dts +++ b/arch/arm/dts/armada-38x-controlcenterdc.dts @@ -16,18 +16,6 @@ #include "armada-388.dtsi" -&gpio0 { - u-boot,dm-pre-reloc; -}; - -&gpio1 { - u-boot,dm-pre-reloc; -}; - -&uart1 { - u-boot,dm-pre-reloc; -}; - / { model = "Controlcenter Digital Compact"; compatible = "marvell,a385-db", "marvell,armada388", @@ -71,7 +59,6 @@ I2C0: i2c@11000 { status = "okay"; clock-frequency = <1000000>; - u-boot,dm-pre-reloc; PCA21: pca9698@21 { compatible = "nxp,pca9698"; reg = <0x21>; @@ -80,7 +67,6 @@ }; PCA22: pca9698@22 { compatible = "nxp,pca9698"; - u-boot,dm-pre-reloc; reg = <0x22>; #gpio-cells = <2>; gpio-controller; @@ -565,7 +551,6 @@ &spi1 { status = "okay"; - u-boot,dm-pre-reloc; spi-flash@0 { #address-cells = <1>; #size-cells = <1>; @@ -579,6 +564,5 @@ compatible = "n25q128a11", "jedec,spi-nor"; reg = <1>; /* Chip select 1 */ spi-max-frequency = <108000000>; - u-boot,dm-pre-reloc; }; }; From d1471948f336be8cd754cdc2d826e47e8d3e6c2c Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 4 Aug 2022 21:06:23 +1200 Subject: [PATCH 14/25] ARM: kirkwood: SBx81LIFKW: remove direct access of GPIO registers Replace code that accessed the GPIO registers directly with code that makes use of the LED_GPIO driver. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/dts/kirkwood-atl-sbx81lifkw.dts | 14 ++++++ board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 50 +++++---------------- configs/SBx81LIFKW_defconfig | 2 + 3 files changed, 27 insertions(+), 39 deletions(-) diff --git a/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts b/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts index 4ae74f4316..3837c8f77f 100644 --- a/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts +++ b/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts @@ -70,6 +70,20 @@ }; }; }; + + gpio-leds { + compatible = "gpio-leds"; + + ledn { + label = "status:ledn"; + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + ledp { + label = "status:ledp"; + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + }; + }; }; &spi0 { diff --git a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c index d8b9fdfe35..feb8b6b83f 100644 --- a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c +++ b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -41,41 +41,6 @@ DECLARE_GLOBAL_DATA_PTR; -struct led { - u32 reg; - u32 value; - u32 mask; -}; - -struct led amber_solid = { - MVEBU_GPIO0_BASE, - BIT(10), - BIT(18) | BIT(10) -}; - -struct led green_solid = { - MVEBU_GPIO0_BASE, - BIT(18) | BIT(10), - BIT(18) | BIT(10) -}; - -struct led amber_flash = { - MVEBU_GPIO0_BASE, - 0, - BIT(18) | BIT(10) -}; - -struct led green_flash = { - MVEBU_GPIO0_BASE, - BIT(18), - BIT(18) | BIT(10) -}; - -static void status_led_set(struct led *led) -{ - clrsetbits_le32(led->reg, led->mask, led->value); -} - int board_early_init_f(void) { /* @@ -165,8 +130,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - status_led_set(&amber_solid); - return 0; } @@ -196,7 +159,16 @@ int mv88e61xx_hw_reset(struct phy_device *phydev) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { - status_led_set(&green_flash); + struct udevice *dev; + int ret; + + ret = led_get_by_label("status:ledp", &dev); + if (!ret) + led_set_state(dev, LEDST_ON); + + ret = led_get_by_label("status:ledn", &dev); + if (!ret) + led_set_state(dev, LEDST_OFF); return 0; } diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index f186f247eb..90800e2dd3 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -46,6 +46,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y +CONFIG_LED=y +CONFIG_LED_GPIO=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y From 923d0a899344350ad3e1f53f95b3f9aa85307b2e Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 4 Aug 2022 21:06:24 +1200 Subject: [PATCH 15/25] ARM: kirkwood: SBx81LIFKW: update for DM_GPIO Update mv88e61xx_hw_reset() to use the DM_GPIO API to toggle the reset line for the linkstreet switch. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c index feb8b6b83f..e0a7f3fa89 100644 --- a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c +++ b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c @@ -17,7 +17,8 @@ #include #include #include -#include +#include +#include /* Note: GPIO differences between specific boards * @@ -37,8 +38,6 @@ #define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27)) #define SBX81LIFKW_OE_VAL_HIGH (BIT(0) | BIT(1)) -#define MV88E6097_RESET 27 - DECLARE_GLOBAL_DATA_PTR; int board_early_init_f(void) @@ -143,11 +142,23 @@ void reset_phy(void) #ifdef CONFIG_MV88E61XX_SWITCH int mv88e61xx_hw_reset(struct phy_device *phydev) { + struct gpio_desc desc; + int ret; + + ret = dm_gpio_lookup_name("mvebu0_27", &desc); + if (ret) + return ret; + + ret = dm_gpio_request(&desc, "linkstreet_rst"); + if (ret) + return ret; + /* Ensure the 88e6097 gets at least 10ms Reset */ - kw_gpio_set_value(MV88E6097_RESET, 0); + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); mdelay(20); - kw_gpio_set_value(MV88E6097_RESET, 1); + dm_gpio_set_value(&desc, 1); mdelay(20); phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; From d54d7b185d8caea519e10595e679ff9debc769dc Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 4 Aug 2022 21:06:25 +1200 Subject: [PATCH 16/25] ARM: kirkwood: SBx81LIFKW: enable CMD_GPIO For debugging it is convenient to query/access GPIOs from the command line. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- configs/SBx81LIFKW_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 90800e2dd3..ad7e2e976d 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_DM=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_NTPSERVER=y From 52b5bbcea6ff5b14793f64b79ab99fd1038d4ffa Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 4 Aug 2022 21:06:26 +1200 Subject: [PATCH 17/25] ARM: kirkwood: SBx81LIFKW: disable KIRKWOOD_GPIO DM_GPIO was already enabled so the MVEBU_GPIO was already available. Having updated the board code to use the DM_GPIO APIs the KIRKWOOD_GPIO driver became unnecessary. Disable it for SBx81LIFKW. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- configs/SBx81LIFKW_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index ad7e2e976d..ec940bd308 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -41,7 +41,6 @@ CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_DM=y -CONFIG_KIRKWOOD_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y From b95a3d29f856aa744c5df9385e269cac92c82664 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 4 Aug 2022 21:06:27 +1200 Subject: [PATCH 18/25] ARM: kirkwood: SBx81LIFKW: enable CONFIG_NET_RANDOM_ETHADDR When booting a fresh board having a random Ethernet address enables using the network device to program the board. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- configs/SBx81LIFKW_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index ec940bd308..a9f984239a 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -39,6 +39,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_DM_PCA953X=y From 0bae7bc2ee20846f121b923f123e8b62b61731c3 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 4 Aug 2022 21:06:28 +1200 Subject: [PATCH 19/25] ARM: kirkwood: SBx81LIFXCAT: disable KIRKWOOD_GPIO DM_GPIO was already enabled so the MVEBU_GPIO was already available. Disable KIRKWOOD_GPIO as it was unnecessary. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- configs/SBx81LIFXCAT_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 9d579091a8..cb80b7876f 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -42,7 +42,6 @@ CONFIG_ENV_SPI_MAX_HZ=20000000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NETCONSOLE=y CONFIG_DM=y -CONFIG_KIRKWOOD_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y From 65b3b24eba7558fa4085a0695b3ad3e7dbf7a3fb Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Thu, 4 Aug 2022 11:43:57 +1200 Subject: [PATCH 20/25] gpio: Remove mvgpio driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The last user of this driver was removed in commit dee08b1999e2 ("arm: Remove gplugd board"). Remove the unused driver. Signed-off-by: Chris Packham Acked-by: Pali Rohár --- drivers/gpio/Makefile | 1 - drivers/gpio/mvgpio.c | 97 ------------------------------------------- drivers/gpio/mvgpio.h | 53 ----------------------- 3 files changed, 151 deletions(-) delete mode 100644 drivers/gpio/mvgpio.c delete mode 100644 drivers/gpio/mvgpio.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 219f37e0e4..39762fa06c 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -24,7 +24,6 @@ obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o obj-$(CONFIG_KONA_GPIO) += kona_gpio.o -obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c deleted file mode 100644 index 12e7197daf..0000000000 --- a/drivers/gpio/mvgpio.c +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * eInfochips Ltd. - * Written-by: Ajay Bhargav - * - * (C) Copyright 2010 - * Marvell Semiconductor - */ - -#include -#include -#include -#include -#include "mvgpio.h" -#include - -#ifndef MV_MAX_GPIO -#define MV_MAX_GPIO 128 -#endif - -int gpio_request(unsigned gpio, const char *label) -{ - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO requested %d\n", __func__, gpio); - return -1; - } - return 0; -} - -int gpio_free(unsigned gpio) -{ - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - struct gpio_reg *gpio_reg_bank; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gcdr); - return 0; -} - -int gpio_direction_output(unsigned gpio, int value) -{ - struct gpio_reg *gpio_reg_bank; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gsdr); - gpio_set_value(gpio, value); - return 0; -} - -int gpio_get_value(unsigned gpio) -{ - struct gpio_reg *gpio_reg_bank; - u32 gpio_val; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - gpio_val = readl(&gpio_reg_bank->gplr); - - return GPIO_VAL(gpio, gpio_val); -} - -int gpio_set_value(unsigned gpio, int value) -{ - struct gpio_reg *gpio_reg_bank; - - if (gpio >= MV_MAX_GPIO) { - printf("%s: Invalid GPIO %d\n", __func__, gpio); - return -1; - } - - gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gpio)); - if (value) - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpsr); - else - writel(GPIO_TO_BIT(gpio), &gpio_reg_bank->gpcr); - - return 0; -} diff --git a/drivers/gpio/mvgpio.h b/drivers/gpio/mvgpio.h deleted file mode 100644 index d68c48e637..0000000000 --- a/drivers/gpio/mvgpio.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * eInfochips Ltd. - * Written-by: Ajay Bhargav - * - * (C) Copyright 2010 - * Marvell Semiconductor - */ - -#ifndef __MVGPIO_H__ -#define __MVGPIO_H__ - -#include - -/* - * GPIO Register map for Marvell SOCs - */ -struct gpio_reg { - u32 gplr; /* Pin Level Register - 0x0000 */ - u32 pad0[2]; - u32 gpdr; /* Pin Direction Register - 0x000C */ - u32 pad1[2]; - u32 gpsr; /* Pin Output Set Register - 0x0018 */ - u32 pad2[2]; - u32 gpcr; /* Pin Output Clear Register - 0x0024 */ - u32 pad3[2]; - u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ - u32 pad4[2]; - u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ - u32 pad5[2]; - u32 gedr; /* Edge Detect Status Register - 0x0048 */ - u32 pad6[2]; - u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ - u32 pad7[2]; - u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ - u32 pad8[2]; - u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable - Register - 0x006C */ - u32 pad9[2]; - u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable - Register - 0x0078 */ - u32 pad10[2]; - u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable - Register - 0x0084 */ - u32 pad11[2]; - u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable - Register - 0x0090 */ - u32 pad12[2]; - u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ -}; - -#endif /* __MVGPIO_H__ */ From 7a1c07117372c746258f79e035dc188fe52c1b48 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 4 Aug 2022 12:41:54 +0200 Subject: [PATCH 21/25] arm64: a37xx: pinctrl: Fix definitions for MPP pins 20-22 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All 3 MPP pins (20, 21 and 22) can be configured individually and also can be configured to GPIO functions. Fix definitions for these MPP pins in existing pin groups. After this change GPIO function can be enabled just for one of these 3 pins. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index bb7a76baed..a5407a16ee 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -200,9 +200,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), - PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), - PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), - PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"), + PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), + PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), + "ptp", "mii"), + PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), + "ptp", "mii"), PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), "mii", "mii_err"), }; From 361cf5c7e1ec01c8660fa549edac86ecb435913a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 4 Aug 2022 12:41:55 +0200 Subject: [PATCH 22/25] arm64: a37xx: pinctrl: Remove unused macro PIN_GRP() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Macro PIN_GRP() is not used, remove it. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index a5407a16ee..32b49f167c 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -99,16 +99,6 @@ struct armada_37xx_pinctrl { unsigned int nfuncs; }; -#define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \ - { \ - .name = _name, \ - .start_pin = _start, \ - .npins = _nr, \ - .reg_mask = _mask, \ - .val = {0, _mask}, \ - .funcs = {_func1, _func2} \ - } - #define PIN_GRP_GPIO_0(_name, _start, _nr) \ { \ .name = _name, \ From 019090647cab4eb0e9a3ab99e64adde3b65e631e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 4 Aug 2022 12:41:56 +0200 Subject: [PATCH 23/25] arm64: a37xx: pinctrl: Improve description for pinmux command MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In more cases group name consist of function name followed by function number. So if function name is just prefix of group name, show group name. So in 'pinmux status -a' command output would be visible also extended function number, which is useful for debugging. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 32b49f167c..25fbe39abd 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -406,7 +406,17 @@ static int armada_37xx_pmx_get_pin_muxing(struct udevice *dev, unsigned int sele for (f = 0; f < NB_FUNCS && grp->funcs[f]; f++) { if (grp->val[f] == val) { - strlcpy(buf, grp->funcs[f], size); + /* + * In more cases group name consist of + * function name followed by function + * number. So if function name is just + * prefix of group name, show group name. + */ + if (strncmp(grp->name, grp->funcs[f], + strlen(grp->funcs[f])) == 0) + strlcpy(buf, grp->name, size); + else + strlcpy(buf, grp->funcs[f], size); return 0; } } From ca3756c86b0ae997699abac7c5371550dd4842a0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 5 Aug 2022 16:03:41 +0200 Subject: [PATCH 24/25] pci: pci_mvebu: Add support for reset-gpios MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Release PERST# signal via GPIO when "reset-gpios" is defined in device tree. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Reviewed-by: Stefan Roese --- drivers/pci/Kconfig | 1 + drivers/pci/pci_mvebu.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 436acca898..22f4995453 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -301,6 +301,7 @@ config PCI_MVEBU depends on (ARCH_KIRKWOOD || ARCH_MVEBU) select MISC select DM_RESET + select DM_GPIO help Say Y here if you want to enable PCIe controller support on Kirkwood and Armada 370/XP/375/38x SoCs. diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index d80f87e0cf..5bd340a421 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -60,6 +61,7 @@ struct mvebu_pcie { struct resource mem; void __iomem *iobase; struct resource io; + struct gpio_desc reset_gpio; u32 intregs; u32 port; u32 lane; @@ -416,6 +418,14 @@ static int mvebu_pcie_probe(struct udevice *dev) struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *hose = dev_get_uclass_priv(ctlr); u32 reg; + int ret; + + /* Request for optional PERST# GPIO */ + ret = gpio_request_by_name(dev, "reset-gpios", 0, &pcie->reset_gpio, GPIOD_IS_OUT); + if (ret && ret != -ENOENT) { + printf("%s: unable to request reset-gpios: %d\n", pcie->name, ret); + return ret; + } /* * Change Class Code of PCI Bridge device to PCI Bridge (0x600400) @@ -537,6 +547,10 @@ static int mvebu_pcie_probe(struct udevice *dev) pcie->cfgcache[(PCI_PREF_MEMORY_BASE - 0x10) / 4] = PCI_PREF_RANGE_TYPE_64 | (PCI_PREF_RANGE_TYPE_64 << 16); + /* Release PERST# via GPIO when it was defined */ + if (dm_gpio_is_valid(&pcie->reset_gpio)) + dm_gpio_set_value(&pcie->reset_gpio, 0); + mvebu_pcie_wait_for_link(pcie); return 0; From ca514d0267f92d8aac2eb5f92ff7d150078df423 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 4 Aug 2022 13:03:44 +0200 Subject: [PATCH 25/25] misc: atsha204a: Don't check for error when waking up the device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The device ignores any levels or transitions on the SCL pin when the device is idle, asleep or during waking up. Linux kernel driver for atsha204a (atmel-sha204a.ko) also ignores return value from i2c wakeup send command, see: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/crypto/atmel-i2c.c?h=v5.19#n174 And also userspace Turris libatsha204 library ignores return value from wakeup send command, see: https://gitlab.nic.cz/turris/libatsha204/-/blob/v29.2/src/libatsha204/layer_ni2c.c#L75-76 U-Boot driver should do same thing. Fixes waking up ATSHA204 on Turris 1.x boards. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Tested-by: Paweł Anikiel Reviewed-by: Marek Behún --- drivers/misc/atsha204a-i2c.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index e7c6be593d..d3c515828f 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -103,12 +103,13 @@ int atsha204a_wakeup(struct udevice *dev) for (try = 1; try <= 10; ++try) { debug("Try %i... ", try); + /* + * The device ignores any levels or transitions on the SCL pin + * when the device is idle, asleep or during waking up. + * Don't check for error when waking up the device. + */ memset(req, 0, 4); - res = atsha204a_send(dev, req, 4); - if (res) { - debug("failed on I2C send, trying again\n"); - continue; - } + atsha204a_send(dev, req, 4); udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);