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Convert CONFIG_PCIE1 et al to Kconfig

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This converts the following to Kconfig:
   CONFIG_PCIE1
   CONFIG_PCIE2
   CONFIG_PCIE3
   CONFIG_PCIE4
   CONFIG_PCI1

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2022-06-20 08:07:45 -04:00
parent a552ffc9d2
commit 3dc2987f5c
171 changed files with 512 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
include/configs/MPC8548CDS.h
View File

@@ -16,10 +16,6 @@
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
#ifndef __ASSEMBLY__

3
include/configs/P1010RDB.h
View File

@@ -63,9 +63,6 @@
/* High Level Configuration Options */
#if defined(CONFIG_PCI)
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
/*
* PCI Windows
* Memory space is mapped 1-1, but I/O space must start from 0.

3
include/configs/P2041RDB.h
View File

@@ -33,9 +33,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */

2
include/configs/P3041DS.h
View File

@@ -9,8 +9,6 @@
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_SYS_SRIO

2
include/configs/P4080DS.h
View File

@@ -9,8 +9,6 @@
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_PCIE3
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */

1
include/configs/P5040DS.h
View File

@@ -9,7 +9,6 @@
*/
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_PCIE3
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */

3
include/configs/T102xRDB.h
View File

@@ -352,9 +352,6 @@
* General PCIe
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#ifdef CONFIG_PCI
/* controller 1, direct to uli, tgtid 3, Base address 20000 */

4
include/configs/T104xRDB.h
View File

@@ -61,10 +61,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
/*
* These can be toggled for performance analysis, otherwise use default.

4
include/configs/T208xQDS.h
View File

@@ -368,10 +368,6 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull

4
include/configs/T208xRDB.h
View File

@@ -321,10 +321,6 @@
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#define CONFIG_PCIE4 /* PCIE controller 4 */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull

5
include/configs/T4240RDB.h
View File

@@ -12,8 +12,6 @@
#include <linux/stringify.h>
#define CONFIG_PCIE4
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#ifdef CONFIG_RAMBOOT_PBL
@@ -44,9 +42,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
/*
* These can be toggled for performance analysis, otherwise use default.

2
include/configs/corenet_ds.h
View File

@@ -36,8 +36,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
/*
* These can be toggled for performance analysis, otherwise use default.

1
include/configs/kmcent2.h
View File

@@ -140,7 +140,6 @@
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
#define CONFIG_PCIE1 /* PCIE controller 1 */
/* Environment in parallel NOR-Flash */
#define CONFIG_ENV_TOTAL_SIZE 0x040000

2
include/configs/ls1012afrwy.h
View File

@@ -25,8 +25,6 @@
func(USB, usb, 0) \
func(DHCP, dhcp, na)
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS

2
include/configs/ls1012aqds.h
View File

@@ -82,8 +82,6 @@
DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
DSPI_CTAR_DT(0))
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS

2
include/configs/ls1012ardb.h
View File

@@ -36,8 +36,6 @@
#define __PHY_ETH2_MASK 0xFB
#define __PHY_ETH1_MASK 0xFD
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCI_SCAN_SHOW
#undef CONFIG_EXTRA_ENV_SETTINGS

4
include/configs/ls1021aiot.h
View File

@@ -97,10 +97,6 @@
#define TSEC2_PHYIDX 0
#endif
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controler 1 */
#define CONFIG_PCIE2 /* PCIE controler 2 */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#ifdef CONFIG_PCI

4
include/configs/ls1021aqds.h
View File

@@ -301,10 +301,6 @@
#endif
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

2
include/configs/ls1021atsn.h
View File

@@ -80,8 +80,6 @@
#define FSL_QSPI_FLASH_NUM 2
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW

4
include/configs/ls1021atwr.h
View File

@@ -171,10 +171,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 1
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

4
include/configs/ls1043a_common.h
View File

@@ -110,10 +110,6 @@
/* PCIe */
#ifndef SPL_NO_PCIE
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

5
include/configs/ls1046a_common.h
View File

@@ -76,11 +76,6 @@
/* I2C */
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define CONFIG_PCIE3 /* PCIE controller 3 */
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif

3
include/configs/p1_p2_rdb_pc.h
View File

@@ -102,9 +102,6 @@
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
#define CONFIG_HWCONFIG
/*
* These can be toggled for performance analysis, otherwise use default.