Merge commit 'remotes/wd/master'
This commit is contained in:
Jon Loeliger
@@ -49,7 +49,7 @@
|
||||
cannot access physical memory directly from core */
|
||||
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
|
||||
#else /* !CONFIG_AU1X00 */
|
||||
#define UNCACHED_SDRAM(a) PHYSADDR(a)
|
||||
#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
|
||||
#endif /* CONFIG_AU1X00 */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
/*
|
||||
|
||||
@@ -19,21 +19,21 @@
|
||||
extern char *strcpy(char *__dest, __const__ char *__src);
|
||||
|
||||
#undef __HAVE_ARCH_STRNCPY
|
||||
extern char *strncpy(char *__dest, __const__ char *__src, size_t __n);
|
||||
extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n);
|
||||
|
||||
#undef __HAVE_ARCH_STRCMP
|
||||
extern int strcmp(__const__ char *__cs, __const__ char *__ct);
|
||||
|
||||
#undef __HAVE_ARCH_STRNCMP
|
||||
extern int strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count);
|
||||
extern int strncmp(__const__ char *__cs, __const__ char *__ct, __kernel_size_t __count);
|
||||
|
||||
#undef __HAVE_ARCH_MEMSET
|
||||
extern void *memset(void *__s, int __c, size_t __count);
|
||||
extern void *memset(void *__s, int __c, __kernel_size_t __count);
|
||||
|
||||
#undef __HAVE_ARCH_MEMCPY
|
||||
extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
|
||||
extern void *memcpy(void *__to, __const__ void *__from, __kernel_size_t __n);
|
||||
|
||||
#undef __HAVE_ARCH_MEMMOVE
|
||||
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
|
||||
extern void *memmove(void *__dest, __const__ void *__src, __kernel_size_t __n);
|
||||
|
||||
#endif /* _ASM_STRING_H */
|
||||
|
||||
@@ -146,7 +146,7 @@
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
|
||||
#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
|
||||
|
||||
#ifdef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CFG_MONITOR_BASE 0x20000
|
||||
|
||||
@@ -163,7 +163,7 @@
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_SDRAM_SIZE 8 /* SDRAM size in MB */
|
||||
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
|
||||
#define CFG_FLASH_BASE 0xffe00000
|
||||
#define CFG_INT_FLASH_BASE 0xf0000000
|
||||
#define CFG_INT_FLASH_ENABLE 0x21
|
||||
|
||||
@@ -175,7 +175,7 @@
|
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CFG_SDRAM_BASE 0x40000000
|
||||
#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
|
||||
#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */
|
||||
#define CFG_SDRAM_CFG1 0x53722730
|
||||
#define CFG_SDRAM_CFG2 0x56670000
|
||||
#define CFG_SDRAM_CTRL 0xE1092000
|
||||
|
||||
@@ -27,8 +27,8 @@
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef _JAMICA54455_H
|
||||
#define _JAMICA54455_H
|
||||
#ifndef _M54455EVB_H
|
||||
#define _M54455EVB_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
@@ -75,7 +75,7 @@
|
||||
#define CONFIG_CMD_MISC
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PCI
|
||||
#undef CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_REGINFO
|
||||
|
||||
@@ -129,8 +129,8 @@
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"load=tftp ${loadaddr) ${u-boot}\0" \
|
||||
"upd=run load; run prog\0" \
|
||||
"prog=prot off 0 2ffff;" \
|
||||
"era 0 2ffff;" \
|
||||
"prog=prot off 4000000 402ffff;" \
|
||||
"era 4000000 402ffff;" \
|
||||
"cp.b ${loadaddr} 0 ${filesize};" \
|
||||
"save\0" \
|
||||
""
|
||||
@@ -174,6 +174,7 @@
|
||||
#define CFG_IMMR CFG_MBAR
|
||||
|
||||
/* PCI */
|
||||
#ifdef CONFIG_CMD_PCI
|
||||
#define CONFIG_PCI 1
|
||||
|
||||
#define CFG_PCI_MEM_BUS 0xA0000000
|
||||
@@ -187,6 +188,7 @@
|
||||
#define CFG_PCI_CFG_BUS 0xB0000000
|
||||
#define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
|
||||
#define CFG_PCI_CFG_SIZE 0x01000000
|
||||
#endif
|
||||
|
||||
/* FPGA - Spartan 2 */
|
||||
/* experiment
|
||||
@@ -268,8 +270,6 @@
|
||||
/* Configuration for environment
|
||||
* Environment is embedded in u-boot in the second sector of the flash
|
||||
*/
|
||||
#define CFG_ENV_OFFSET 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x2000
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#undef CFG_ENV_IS_EMBEDDED
|
||||
@@ -278,13 +278,17 @@
|
||||
* FLASH organization
|
||||
*/
|
||||
#ifdef CFG_ATMEL_BOOT
|
||||
# define CFG_FLASH_BASE 0
|
||||
# define CFG_FLASH_BASE CFG_CS0_BASE
|
||||
# define CFG_FLASH0_BASE CFG_CS0_BASE
|
||||
# define CFG_FLASH1_BASE CFG_CS1_BASE
|
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
|
||||
# define CFG_ENV_SECT_SIZE 0x2000
|
||||
#else
|
||||
# define CFG_FLASH_BASE CFG_FLASH0_BASE
|
||||
# define CFG_FLASH0_BASE CFG_CS1_BASE
|
||||
# define CFG_FLASH1_BASE CFG_CS0_BASE
|
||||
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
|
||||
# define CFG_ENV_SECT_SIZE 0x20000
|
||||
#endif
|
||||
|
||||
/* M54455EVB has one non CFI flash, defined CFG_FLASH_CFI will cause the system
|
||||
@@ -328,9 +332,9 @@
|
||||
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
|
||||
*/
|
||||
#ifdef CFG_ATMEL_BOOT
|
||||
# define CONFIG_JFFS2_DEV "nor0"
|
||||
# define CONFIG_JFFS2_DEV "nor1"
|
||||
# define CONFIG_JFFS2_PART_SIZE 0x01000000
|
||||
# define CONFIG_JFFS2_PART_OFFSET CFG_FLASH1_BASE
|
||||
# define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000)
|
||||
#else
|
||||
# define CONFIG_JFFS2_DEV "nor0"
|
||||
# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
|
||||
@@ -356,20 +360,20 @@
|
||||
|
||||
#ifdef CFG_ATMEL_BOOT
|
||||
/* Atmel Flash */
|
||||
#define CFG_CS0_BASE 0
|
||||
#define CFG_CS0_BASE 0x04000000
|
||||
#define CFG_CS0_MASK 0x00070001
|
||||
#define CFG_CS0_CTRL 0x00001140
|
||||
/* Intel Flash */
|
||||
#define CFG_CS1_BASE 0x04000000
|
||||
#define CFG_CS1_BASE 0x00000000
|
||||
#define CFG_CS1_MASK 0x01FF0001
|
||||
#define CFG_CS1_CTRL 0x003F3D60
|
||||
#define CFG_CS1_CTRL 0x00000D60
|
||||
|
||||
#define CFG_ATMEL_BASE CFG_CS0_BASE
|
||||
#else
|
||||
/* Intel Flash */
|
||||
#define CFG_CS0_BASE 0
|
||||
#define CFG_CS0_BASE 0x00000000
|
||||
#define CFG_CS0_MASK 0x01FF0001
|
||||
#define CFG_CS0_CTRL 0x003F3D60
|
||||
#define CFG_CS0_CTRL 0x00000D60
|
||||
/* Atmel Flash */
|
||||
#define CFG_CS1_BASE 0x04000000
|
||||
#define CFG_CS1_MASK 0x00070001
|
||||
@@ -388,4 +392,4 @@
|
||||
#define CFG_CS3_MASK 0x00070001
|
||||
#define CFG_CS3_CTRL 0x00000020
|
||||
|
||||
#endif /* _JAMICA54455_H */
|
||||
#endif /* _M54455EVB_H */
|
||||
|
||||
@@ -146,37 +146,26 @@
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_all.h>
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_BEDBUG
|
||||
#undef CONFIG_CMD_BMP
|
||||
#undef CONFIG_CMD_BSP
|
||||
#undef CONFIG_CMD_DATE
|
||||
#undef CONFIG_CMD_DHCP
|
||||
#undef CONFIG_CMD_DISPLAY
|
||||
#undef CONFIG_CMD_DOC
|
||||
#undef CONFIG_CMD_DTT
|
||||
#undef CONFIG_CMD_EEPROM
|
||||
#undef CONFIG_CMD_ELF
|
||||
#undef CONFIG_CMD_EXT2
|
||||
#undef CONFIG_CMD_FDC
|
||||
#undef CONFIG_CMD_FDOS
|
||||
#undef CONFIG_CMD_HWFLOW
|
||||
#undef CONFIG_CMD_IDE
|
||||
#undef CONFIG_CMD_JFFS2
|
||||
#undef CONFIG_CMD_KGDB
|
||||
#undef CONFIG_CMD_MFSL
|
||||
#undef CONFIG_CMD_MMC
|
||||
#undef CONFIG_CMD_NAND
|
||||
#undef CONFIG_CMD_PCMCIA
|
||||
#undef CONFIG_CMD_REISER
|
||||
#undef CONFIG_CMD_SCSI
|
||||
#undef CONFIG_CMD_SPI
|
||||
#undef CONFIG_CMD_SNTP
|
||||
#undef CONFIG_CMD_VFD
|
||||
#undef CONFIG_CMD_UNIVERSE
|
||||
#undef CONFIG_CMD_USB
|
||||
#undef CONFIG_CMD_XIMG
|
||||
/* Commands we want, that are not part of default set */
|
||||
#define CONFIG_CMD_ASKENV /* ask for env variable */
|
||||
#define CONFIG_CMD_CACHE /* icache, dcache */
|
||||
#define CONFIG_CMD_DHCP /* DHCP Support */
|
||||
#define CONFIG_CMD_DIAG /* Diagnostics */
|
||||
#define CONFIG_CMD_IMMAP /* IMMR dump support */
|
||||
#define CONFIG_CMD_IRQ /* irqinfo */
|
||||
#define CONFIG_CMD_MII /* MII support */
|
||||
#define CONFIG_CMD_PCI /* pciinfo */
|
||||
#define CONFIG_CMD_PING /* ping support */
|
||||
#define CONFIG_CMD_PORTIO /* Port I/O */
|
||||
#define CONFIG_CMD_REGINFO /* Register dump */
|
||||
#define CONFIG_CMD_SAVES /* save S record dump */
|
||||
#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
|
||||
|
||||
/* Commands from default set we don't need */
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
|
||||
#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
|
||||
|
||||
/* Define a command string that is automatically executed when no character
|
||||
* is read on the console interface withing "Boot Delay" after reset.
|
||||
|
||||
@@ -316,6 +316,7 @@ extern unsigned long get_clock_freq(void);
|
||||
#define OF_SOC "soc8541@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
|
||||
#define OF_PCI "pci@e0008000"
|
||||
|
||||
/*
|
||||
* I2C
|
||||
|
||||
@@ -340,6 +340,7 @@ extern unsigned long get_clock_freq(void);
|
||||
#define OF_SOC "soc8548@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
|
||||
#define OF_PCI "pci@e0008000"
|
||||
|
||||
/*
|
||||
* I2C
|
||||
|
||||
@@ -316,6 +316,7 @@ extern unsigned long get_clock_freq(void);
|
||||
#define OF_SOC "soc8555@e0000000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
|
||||
#define OF_PCI "pci@e0008000"
|
||||
|
||||
/*
|
||||
* I2C
|
||||
|
||||
@@ -297,7 +297,7 @@ extern unsigned long get_clock_freq(void);
|
||||
#define OF_SOC "soc8568@e0000000"
|
||||
#define OF_QE "qe@e0080000"
|
||||
#define OF_TBCLK (bd->bi_busfreq / 8)
|
||||
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
|
||||
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500"
|
||||
|
||||
/*
|
||||
* I2C
|
||||
|
||||
@@ -257,8 +257,8 @@
|
||||
"fdt_addr=FC0A0000\0" \
|
||||
"kernel_addr=FC0C0000\0" \
|
||||
"ramdisk_addr=FC300000\0" \
|
||||
"kernel_addr_r=200000\0" \
|
||||
"fdt_addr_r=400000\0" \
|
||||
"kernel_addr_r=400000\0" \
|
||||
"fdt_addr_r=600000\0" \
|
||||
"rootpath=/opt/eldk/ppc_6xx\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
@@ -547,7 +547,7 @@
|
||||
# if defined (CONFIG_TQM5200_REV100)
|
||||
# error TQM5200 REV100 not supported on STK52XX REV200 or above
|
||||
# else/* TQM5200 REV200 and above */
|
||||
# define CFG_GPS_PORT_CONFIG 0x91500004
|
||||
# define CFG_GPS_PORT_CONFIG 0x91500404
|
||||
# endif
|
||||
# endif
|
||||
#elif defined (CONFIG_FO300)
|
||||
|
||||
@@ -69,9 +69,14 @@
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"bootfile=/tftpboot/TQM860M/uImage\0" \
|
||||
"fdt_addr=40080000\0" \
|
||||
"kernel_addr=400A0000\0" \
|
||||
"fdt_addr=400C0000\0" \
|
||||
"kernel_addr=40100000\0" \
|
||||
"ramdisk_addr=40280000\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"update=protect off 40000000 +${filesize};" \
|
||||
"erase 40000000 +${filesize};" \
|
||||
"cp.b 200000 40000000 ${filesize};" \
|
||||
"protect on 40000000 +${filesize}\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
@@ -172,7 +177,7 @@
|
||||
#define CFG_FLASH_BASE 0x40000000
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
@@ -193,7 +198,7 @@
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
|
||||
|
||||
@@ -81,9 +81,14 @@
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||
"bootfile=/tftpboot/TQM866M/uImage\0" \
|
||||
"fdt_addr=40080000\0" \
|
||||
"kernel_addr=400A0000\0" \
|
||||
"fdt_addr=400C0000\0" \
|
||||
"kernel_addr=40100000\0" \
|
||||
"ramdisk_addr=40280000\0" \
|
||||
"load=tftp 200000 ${u-boot}\0" \
|
||||
"update=protect off 40000000 +${filesize};" \
|
||||
"erase 40000000 +${filesize};" \
|
||||
"cp.b 200000 40000000 ${filesize};" \
|
||||
"protect on 40000000 +${filesize}\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
@@ -215,7 +220,7 @@
|
||||
#define CFG_FLASH_BASE 0x40000000
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
@@ -236,7 +241,7 @@
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
|
||||
@@ -421,26 +426,30 @@
|
||||
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
* Periodic timer for refresh, start with refresh rate for 40 MHz clock
|
||||
* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
|
||||
* Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
|
||||
*
|
||||
* CPUclock(MHz) * 31.2
|
||||
* CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0
|
||||
* 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
|
||||
*
|
||||
* CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us
|
||||
* CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us
|
||||
* CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us
|
||||
* CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us
|
||||
*
|
||||
* Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
|
||||
* be met also in the default configuration, i.e. if environment variable
|
||||
* 'cpuclk' is not set.
|
||||
*/
|
||||
#define CFG_MAMR_PTA 39
|
||||
#define CFG_MAMR_PTA 97
|
||||
|
||||
/*
|
||||
* For 16 MBit, refresh rates could be 31.3 us
|
||||
* (= 64 ms / 2K = 125 / quad bursts).
|
||||
* For a simpler initialization, 15.6 us is used instead.
|
||||
*
|
||||
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
|
||||
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
|
||||
* Memory Periodic Timer Prescaler Register (MPTPR) values.
|
||||
*/
|
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
|
||||
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16
|
||||
/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
|
||||
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
|
||||
@@ -114,15 +114,10 @@
|
||||
#define CONFIG_AUTOBOOT_STOP_STR " "
|
||||
|
||||
/*
|
||||
* These are "locally administered ethernet addresses" generated by
|
||||
* ./tools/gen_eth_addr
|
||||
*
|
||||
* After booting the board for the first time, new addresses should be
|
||||
* generated and assigned to the environment variables "ethaddr" and
|
||||
* "eth1addr".
|
||||
* After booting the board for the first time, new ethernet addresses
|
||||
* should be generated and assigned to the environment variables
|
||||
* "ethaddr" and "eth1addr". This is normally done during production.
|
||||
*/
|
||||
#define CONFIG_ETHADDR 6a:87:71:14:cd:cb
|
||||
#define CONFIG_ETH1ADDR ca:f8:15:e6:3e:e6
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
|
||||
#define CONFIG_NET_MULTI 1
|
||||
|
||||
|
||||
@@ -123,6 +123,8 @@
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
|
||||
#include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
|
||||
|
||||
#undef CFG_USB_OHCI_BOARD_INIT
|
||||
#define CFG_USB_OHCI_CPU_INIT 1
|
||||
#define CFG_USB_OHCI_REGS_BASE OHCI_REGS_BASE
|
||||
|
||||
@@ -42,6 +42,7 @@
|
||||
#endif
|
||||
#define CONFIG_MMC 1
|
||||
#define BOARD_LATE_INIT 1
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
|
||||
@@ -163,9 +163,9 @@
|
||||
|
||||
|
||||
/*
|
||||
* Clock configuration: SYS_XTALIN = 25MHz
|
||||
* Clock configuration: SYS_XTALIN = 33MHz
|
||||
*/
|
||||
#define CFG_MPC5XXX_CLKIN 25000000
|
||||
#define CFG_MPC5XXX_CLKIN 33000000
|
||||
|
||||
|
||||
/*
|
||||
@@ -211,7 +211,7 @@
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */
|
||||
#define CFG_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
|
||||
|
||||
|
||||
@@ -221,7 +221,7 @@
|
||||
/* Boot Chipselect */
|
||||
#define CFG_BOOTCS_START CFG_FLASH_BASE
|
||||
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
|
||||
#define CFG_BOOTCS_CFG 0x03035D00
|
||||
#define CFG_BOOTCS_CFG 0x00045D00
|
||||
|
||||
/* Flash memory addressing */
|
||||
#define CFG_CS0_START CFG_FLASH_BASE
|
||||
@@ -251,11 +251,11 @@
|
||||
/*
|
||||
* SDRAM configuration
|
||||
*/
|
||||
/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 2, 32 bit data bus */
|
||||
#define SDRAM_CONFIG1 0x52222600
|
||||
#define SDRAM_CONFIG2 0x88b70000
|
||||
#define SDRAM_CONTROL 0x50570000
|
||||
#define SDRAM_MODE 0x008d0000
|
||||
/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */
|
||||
#define SDRAM_CONFIG1 0x62322900
|
||||
#define SDRAM_CONFIG2 0x88c70000
|
||||
#define SDRAM_CONTROL 0x504f0000
|
||||
#define SDRAM_MODE 0x00cd0000
|
||||
|
||||
|
||||
/*
|
||||
@@ -267,7 +267,7 @@
|
||||
#define CFG_FLASH_SIZE 0x01000000
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
|
||||
#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
|
||||
#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
|
||||
|
||||
/*
|
||||
@@ -277,8 +277,8 @@
|
||||
#define MTDIDS_DEFAULT "nor0=motionpro-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \
|
||||
"13m(fs),2m(kernel),256k(uboot)," \
|
||||
"64k(env),64k(redund_env),64k(dtb)," \
|
||||
"-(user_data)"
|
||||
"128k(env),128k(redund_env)," \
|
||||
"128k(dtb),-(user_data)"
|
||||
|
||||
/*
|
||||
* IDE/ATA configuration
|
||||
@@ -356,7 +356,7 @@ extern void __led_set(led_id_t id, int state);
|
||||
/* This has to be a multiple of the Flash sector size */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
#define CFG_ENV_SIZE 0x1000
|
||||
#define CFG_ENV_SECT_SIZE 0x10000
|
||||
#define CFG_ENV_SECT_SIZE 0x20000
|
||||
|
||||
/* Configuration of redundant environment */
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
|
||||
@@ -394,7 +394,8 @@ extern void __led_set(led_id_t id, int state);
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x03f00000 /* 1 ... 64 MiB in DRAM */
|
||||
#define CFG_MEMTEST_END 0x03e00000 /* 1 ... 62 MiB in DRAM */
|
||||
#define CFG_ALT_MEMTEST
|
||||
|
||||
#define CFG_LOAD_ADDR 0x200000 /* default kernel load addr */
|
||||
|
||||
|
||||
@@ -38,10 +38,11 @@
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram
|
||||
* If we are developing, we might want to start U-Boot from RAM
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
|
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */
|
||||
|
||||
/*
|
||||
* define the following to enable debug blinks. A debug blink function
|
||||
@@ -62,6 +63,7 @@
|
||||
#endif
|
||||
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define BOARD_LATE_INIT 1
|
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
@@ -121,7 +123,6 @@
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_DHCP
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTCOMMAND "bootm 40000"
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
|
||||
@@ -332,7 +333,7 @@
|
||||
#define CFG_FLASH_CFI_DRIVER 1
|
||||
|
||||
#define CFG_MONITOR_BASE 0
|
||||
#define CFG_MONITOR_LEN 0x40000
|
||||
#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
@@ -347,7 +348,7 @@
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
/* Addr of Environment Sector */
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
|
||||
#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x40000
|
||||
#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
|
||||
#define CONFIG_XSENGINE 1
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define BOARD_POST_INIT 1
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
||||
|
||||
@@ -38,9 +38,9 @@ typedef struct block_dev_desc {
|
||||
#endif
|
||||
lbaint_t lba; /* number of blocks */
|
||||
unsigned long blksz; /* block size */
|
||||
unsigned char vendor [40+1]; /* IDE model, SCSI Vendor */
|
||||
unsigned char product[20+1]; /* IDE Serial no, SCSI product */
|
||||
unsigned char revision[8+1]; /* firmware revision */
|
||||
char vendor [40+1]; /* IDE model, SCSI Vendor */
|
||||
char product[20+1]; /* IDE Serial no, SCSI product */
|
||||
char revision[8+1]; /* firmware revision */
|
||||
unsigned long (*block_read)(int dev,
|
||||
unsigned long start,
|
||||
lbaint_t blkcnt,
|
||||
|
||||
Reference in New Issue
Block a user