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Merge commit 'remotes/wd/master'

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This commit is contained in:
Jon Loeliger
2007-11-02 15:22:01 -05:00
parent 3c89d75409 e60adeac2d
commit 3cac27c1d4
73 changed files with 757 additions and 342 deletions
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8
cpu/arm920t/at91rm9200/usb.c
View File

@@ -28,7 +28,7 @@
#include <asm/arch/hardware.h>
int usb_cpu_init()
int usb_cpu_init(void)
{
/* Enable USB host clock. */
*AT91C_PMC_SCER = AT91C_PMC_UHP; /* 48MHz clock enabled for UHP */
@@ -36,7 +36,7 @@ int usb_cpu_init()
return 0;
}
int usb_cpu_stop()
int usb_cpu_stop(void)
{
/* Initialization failed */
*AT91C_PMC_PCDR = 1 << AT91C_ID_UHP; /* Peripheral Clock Disable Register */
@@ -44,9 +44,9 @@ int usb_cpu_stop()
return 0;
}
int usb_cpu_init_fail()
int usb_cpu_init_fail(void)
{
usb_cpu_stop();
return usb_cpu_stop();
}
# endif /* CONFIG_AT91RM9200 */

6
cpu/mcf52x2/start.S
View File

@@ -58,7 +58,7 @@ _vectors:
.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
#if defined(CONFIG_R5200)
.long 0x400
#elif defined(CONFIG_M5282)
#elif defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
.long _start - TEXT_BASE
#else
.long _START
@@ -177,7 +177,11 @@ _after_flashbar_copy:
* therefore no VBR to set
*/
#if !defined(CONFIG_MONITOR_IS_IN_RAM)
#if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
move.l #CFG_INT_FLASH_BASE, %d0
#else
move.l #CFG_FLASH_BASE, %d0
#endif
movec %d0, %VBR
#endif

4
cpu/mcf532x/start.S
View File

@@ -131,7 +131,7 @@ _start:
movec %d0, %VBR
move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
movec %d0, %RAMBAR0
movec %d0, %RAMBAR1
/* invalidate and disable cache */
move.l #0x01000000, %d0 /* Invalidate cache cmd */
@@ -268,7 +268,7 @@ _int_handler:
icache_enable:
move.l #0x01000000, %d0 /* Invalidate cache cmd */
movec %d0, %CACR /* Invalidate cache */
move.l #(CFG_SDRAM_BASE + 0xc000 + ((CFG_SDRAM_SIZE & 0x1fe0) << 11)), %d0
move.l #(CFG_SDRAM_BASE + 0x1c000), %d0
movec %d0, %ACR0 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */

2
cpu/mips/config.mk
View File

@@ -35,6 +35,6 @@ else
ENDIANNESS = -EB
endif
MIPSFLAGS += $(ENDIANNESS) -mabicalls
MIPSFLAGS += $(ENDIANNESS)
PLATFORM_CPPFLAGS += $(MIPSFLAGS)

19
cpu/mips/start.S
View File

@@ -234,11 +234,11 @@ reset:
li t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
/* Initialize GOT pointer.
/* Initialize $gp.
*/
bal 1f
nop
.word _GLOBAL_OFFSET_TABLE_
.word _gp
1:
move gp, ra
lw t1, 0(ra)
@@ -306,9 +306,9 @@ relocate_code:
move t1, a2
/*
* Fix GOT pointer:
* Fix $gp:
*
* New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
* New $gp = (Old $gp - CFG_MONITOR_BASE) + Destination Address
*/
move t6, gp
sub gp, CFG_MONITOR_BASE
@@ -341,15 +341,22 @@ relocate_code:
j t0
nop
.gpword _GLOBAL_OFFSET_TABLE_ /* _GLOBAL_OFFSET_TABLE_ - _gp */
.word uboot_end_data
.word uboot_end
.word num_got_entries
in_ram:
/* Now we want to update GOT.
/*
* Now we want to update GOT.
*
* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) /* t3 <-- num_got_entries */
addi t4, gp, 8 /* Skipping first two entries. */
lw t4, -16(t0) /* t4 <-- (_GLOBAL_OFFSET_TABLE_ - _gp) */
add t4, t4, gp /* t4 now holds _GLOBAL_OFFSET_TABLE_ */
addi t4, t4, 8 /* Skipping first two entries. */
li t2, 2
1:
lw t1, 0(t4)

7
cpu/mpc85xx/cpu.c
View File

@@ -163,7 +163,12 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
* Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1
*/
unsigned long val;
unsigned long val, msr;
msr = mfmsr ();
msr |= MSR_DE;
mtmsr (msr);
val = mfspr(DBCR0);
val |= 0x70000000;
mtspr(DBCR0,val);

24
cpu/mpc85xx/start.S
View File

@@ -218,6 +218,8 @@ _start_e500:
bdnz 0b
/* Clear and set up some registers. */
li r0,0
mtmsr r0
li r0,0x0000
lis r1,0xffff
mtspr DEC,r0 /* prevent dec exceptions */
@@ -266,18 +268,17 @@ _start_e500:
*/
lis r3,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
li r2,512 /* 512*32=16K */
li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
mtctr r2
li r0,0
1:
dcbz r0,r3
dcbtls 0,r0,r3
addi r3,r3,32
addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
/* Jump out the last 4K page and continue to 'normal' start */
#ifdef CFG_RAMBOOT
bl 3f
b _start_cont
#else
/* Calculate absolute address in FLASH and jump there */
@@ -286,15 +287,9 @@ _start_e500:
ori r3,r3,CFG_MONITOR_BASE@l
addi r3,r3,_start_cont - _start + _START_OFFSET
mtlr r3
blr
#endif
3: li r0,0
mtspr SRR1,r0 /* Keep things disabled for now */
mflr r1
mtspr SRR0,r1
rfi
isync
.text
.globl _start
_start:
@@ -701,6 +696,7 @@ in8:
.globl out8
out8:
stb r4,0x0000(r3)
sync
blr
/*------------------------------------------------------------------------------- */
@@ -710,6 +706,7 @@ out8:
.globl out16
out16:
sth r4,0x0000(r3)
sync
blr
/*------------------------------------------------------------------------------- */
@@ -719,6 +716,7 @@ out16:
.globl out16r
out16r:
sthbrx r4,r0,r3
sync
blr
/*------------------------------------------------------------------------------- */
@@ -728,6 +726,7 @@ out16r:
.globl out32
out32:
stw r4,0x0000(r3)
sync
blr
/*------------------------------------------------------------------------------- */
@@ -737,6 +736,7 @@ out32:
.globl out32r
out32r:
stwbrx r4,r0,r3
sync
blr
/*------------------------------------------------------------------------------- */
@@ -1061,11 +1061,11 @@ unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
li r4,512
li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
mtctr r4
1: icbi r0,r3
dcbi r0,r3
addi r3,r3,32
addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
sync /* Wait for all icbi to complete on bus */
isync

3
cpu/pxa/config.mk
View File

@@ -25,8 +25,7 @@
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-msoft-float
#PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale
PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale
# =========================================================================
#
# Supply options according to compiler version

72
cpu/pxa/serial.c
View File

@@ -35,17 +35,17 @@
DECLARE_GLOBAL_DATA_PTR;
#define FFUART 0
#define BTUART 1
#define STUART 2
#define FFUART_INDEX 0
#define BTUART_INDEX 1
#define STUART_INDEX 2
#ifndef CONFIG_SERIAL_MULTI
#if defined (CONFIG_FFUART)
#define UART_INDEX FFUART
#define UART_INDEX FFUART_INDEX
#elif defined (CONFIG_BTUART)
#define UART_INDEX BTUART
#define UART_INDEX BTUART_INDEX
#elif defined (CONFIG_STUART)
#define UART_INDEX STUART
#define UART_INDEX STUART_INDEX
#else
#error "Bad: you didn't configure serial ..."
#endif
@@ -71,7 +71,7 @@ void pxa_setbrg_dev (unsigned int uart_index)
hang ();
switch (uart_index) {
case FFUART:
case FFUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_22_FFUART;
#else
@@ -90,7 +90,7 @@ void pxa_setbrg_dev (unsigned int uart_index)
FFIER = IER_UUE; /* Enable FFUART */
break;
case BTUART:
case BTUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_21_BTUART;
#else
@@ -110,7 +110,7 @@ void pxa_setbrg_dev (unsigned int uart_index)
break;
case STUART:
case STUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
CKENA |= CKENA_23_STUART;
#else
@@ -154,20 +154,20 @@ int pxa_init_dev (unsigned int uart_index)
void pxa_putc_dev (unsigned int uart_index,const char c)
{
switch (uart_index) {
case FFUART:
case FFUART_INDEX:
/* wait for room in the tx FIFO on FFUART */
while ((FFLSR & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
FFTHR = c;
break;
case BTUART:
case BTUART_INDEX:
while ((BTLSR & LSR_TEMT ) == 0 )
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
BTTHR = c;
break;
case STUART:
case STUART_INDEX:
while ((STLSR & LSR_TEMT ) == 0 )
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
STTHR = c;
@@ -187,11 +187,11 @@ void pxa_putc_dev (unsigned int uart_index,const char c)
int pxa_tstc_dev (unsigned int uart_index)
{
switch (uart_index) {
case FFUART:
case FFUART_INDEX:
return FFLSR & LSR_DR;
case BTUART:
case BTUART_INDEX:
return BTLSR & LSR_DR;
case STUART:
case STUART_INDEX:
return STLSR & LSR_DR;
}
return -1;
@@ -205,16 +205,16 @@ int pxa_tstc_dev (unsigned int uart_index)
int pxa_getc_dev (unsigned int uart_index)
{
switch (uart_index) {
case FFUART:
case FFUART_INDEX:
while (!(FFLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) FFRBR & 0xff;
case BTUART:
case BTUART_INDEX:
while (!(BTLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) BTRBR & 0xff;
case STUART:
case STUART_INDEX:
while (!(STLSR & LSR_DR))
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
return (char) STRBR & 0xff;
@@ -233,32 +233,32 @@ pxa_puts_dev (unsigned int uart_index,const char *s)
#if defined (CONFIG_FFUART)
static int ffuart_init(void)
{
return pxa_init_dev(FFUART);
return pxa_init_dev(FFUART_INDEX);
}
static void ffuart_setbrg(void)
{
return pxa_setbrg_dev(FFUART);
return pxa_setbrg_dev(FFUART_INDEX);
}
static void ffuart_putc(const char c)
{
return pxa_putc_dev(FFUART,c);
return pxa_putc_dev(FFUART_INDEX,c);
}
static void ffuart_puts(const char *s)
{
return pxa_puts_dev(FFUART,s);
return pxa_puts_dev(FFUART_INDEX,s);
}
static int ffuart_getc(void)
{
return pxa_getc_dev(FFUART);
return pxa_getc_dev(FFUART_INDEX);
}
static int ffuart_tstc(void)
{
return pxa_tstc_dev(FFUART);
return pxa_tstc_dev(FFUART_INDEX);
}
struct serial_device serial_ffuart_device =
@@ -277,32 +277,32 @@ struct serial_device serial_ffuart_device =
#if defined (CONFIG_BTUART)
static int btuart_init(void)
{
return pxa_init_dev(BTUART);
return pxa_init_dev(BTUART_INDEX);
}
static void btuart_setbrg(void)
{
return pxa_setbrg_dev(BTUART);
return pxa_setbrg_dev(BTUART_INDEX);
}
static void btuart_putc(const char c)
{
return pxa_putc_dev(BTUART,c);
return pxa_putc_dev(BTUART_INDEX,c);
}
static void btuart_puts(const char *s)
{
return pxa_puts_dev(BTUART,s);
return pxa_puts_dev(BTUART_INDEX,s);
}
static int btuart_getc(void)
{
return pxa_getc_dev(BTUART);
return pxa_getc_dev(BTUART_INDEX);
}
static int btuart_tstc(void)
{
return pxa_tstc_dev(BTUART);
return pxa_tstc_dev(BTUART_INDEX);
}
struct serial_device serial_btuart_device =
@@ -321,32 +321,32 @@ struct serial_device serial_btuart_device =
#if defined (CONFIG_STUART)
static int stuart_init(void)
{
return pxa_init_dev(STUART);
return pxa_init_dev(STUART_INDEX);
}
static void stuart_setbrg(void)
{
return pxa_setbrg_dev(STUART);
return pxa_setbrg_dev(STUART_INDEX);
}
static void stuart_putc(const char c)
{
return pxa_putc_dev(STUART,c);
return pxa_putc_dev(STUART_INDEX,c);
}
static void stuart_puts(const char *s)
{
return pxa_puts_dev(STUART,s);
return pxa_puts_dev(STUART_INDEX,s);
}
static int stuart_getc(void)
{
return pxa_getc_dev(STUART);
return pxa_getc_dev(STUART_INDEX);
}
static int stuart_tstc(void)
{
return pxa_tstc_dev(STUART);
return pxa_tstc_dev(STUART_INDEX);
}
struct serial_device serial_stuart_device =

6
cpu/pxa/start.S
View File

@@ -166,13 +166,17 @@ _start_armboot: .word start_armboot
/* */
/****************************************************************************/
/* mk@tbd: Fix this! */
#ifdef CONFIG_CPU_MONAHANS
#if defined(CONFIG_PXA250) || defined(CONFIG_CPU_MONAHANS)
#undef ICMR
#undef OSMR3
#undef OSCR
#undef OWER
#undef OIER
#endif
#ifdef CONFIG_PXA250
#undef RCSR
#undef CCCR
#endif
/* Interrupt-Controller base address */
IC_BASE: .word 0x40d00000

7
cpu/pxa/usb.c
View File

@@ -27,8 +27,9 @@
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
#include <asm/arch/pxa-regs.h>
#include <usb.h>
int usb_cpu_init()
int usb_cpu_init(void)
{
#if defined(CONFIG_CPU_MONAHANS)
/* Enable USB host clock. */
@@ -65,7 +66,7 @@ int usb_cpu_init()
return 0;
}
int usb_cpu_stop()
int usb_cpu_stop(void)
{
UHCHR |= UHCHR_FHR;
udelay(11);
@@ -86,7 +87,7 @@ int usb_cpu_stop()
return 0;
}
int usb_cpu_init_fail()
int usb_cpu_init_fail(void)
{
return 0;
}