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Merge git://www.denx.de/git/u-boot

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Conflicts:

	include/asm-microblaze/microblaze_intc.h
	include/linux/stat.h
This commit is contained in:
Michal Simek
2007-05-08 00:32:35 +02:00
parent fb05f6da35 ac4cd59d59
commit 3c4bd60de1
499 changed files with 50807 additions and 9483 deletions
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2
include/74xx_7xx.h
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@@ -111,7 +111,7 @@ typedef enum __cpu_t {
CPU_750CX, CPU_750FX, CPU_750GX,
CPU_7400,
CPU_7410,
CPU_7448,
CPU_7447A, CPU_7448,
CPU_7450, CPU_7455, CPU_7457,
CPU_UNKNOWN} cpu_t;

70
include/asm-avr32/arch-at32ap7000/clk.h Normal file
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@@ -0,0 +1,70 @@
/*
* Copyright (C) 2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_AVR32_ARCH_CLK_H__
#define __ASM_AVR32_ARCH_CLK_H__
#ifdef CONFIG_PLL
#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
#else
#define MAIN_CLK_RATE (CFG_OSC0_HZ)
#endif
static inline unsigned long get_cpu_clk_rate(void)
{
return MAIN_CLK_RATE >> CFG_CLKDIV_CPU;
}
static inline unsigned long get_hsb_clk_rate(void)
{
return MAIN_CLK_RATE >> CFG_CLKDIV_HSB;
}
static inline unsigned long get_pba_clk_rate(void)
{
return MAIN_CLK_RATE >> CFG_CLKDIV_PBA;
}
static inline unsigned long get_pbb_clk_rate(void)
{
return MAIN_CLK_RATE >> CFG_CLKDIV_PBB;
}
/* Accessors for specific devices. More will be added as needed. */
static inline unsigned long get_sdram_clk_rate(void)
{
return get_hsb_clk_rate();
}
static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
{
return get_pba_clk_rate();
}
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
return get_pbb_clk_rate();
}
static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
{
return get_hsb_clk_rate();
}
static inline unsigned long get_mci_clk_rate(void)
{
return get_pbb_clk_rate();
}
#endif /* __ASM_AVR32_ARCH_CLK_H__ */

212
include/asm-avr32/arch-at32ap7000/gpio.h Normal file
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@@ -0,0 +1,212 @@
/*
* Copyright (C) 2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_AVR32_ARCH_GPIO_H__
#define __ASM_AVR32_ARCH_GPIO_H__
#include <asm/arch/memory-map.h>
#define NR_GPIO_CONTROLLERS 5
/*
* Pin numbers identifying specific GPIO pins on the chip.
*/
#define GPIO_PIOA_BASE (0)
#define GPIO_PIN_PA0 (GPIO_PIOA_BASE + 0)
#define GPIO_PIN_PA1 (GPIO_PIOA_BASE + 1)
#define GPIO_PIN_PA2 (GPIO_PIOA_BASE + 2)
#define GPIO_PIN_PA3 (GPIO_PIOA_BASE + 3)
#define GPIO_PIN_PA4 (GPIO_PIOA_BASE + 4)
#define GPIO_PIN_PA5 (GPIO_PIOA_BASE + 5)
#define GPIO_PIN_PA6 (GPIO_PIOA_BASE + 6)
#define GPIO_PIN_PA7 (GPIO_PIOA_BASE + 7)
#define GPIO_PIN_PA8 (GPIO_PIOA_BASE + 8)
#define GPIO_PIN_PA9 (GPIO_PIOA_BASE + 9)
#define GPIO_PIN_PA10 (GPIO_PIOA_BASE + 10)
#define GPIO_PIN_PA11 (GPIO_PIOA_BASE + 11)
#define GPIO_PIN_PA12 (GPIO_PIOA_BASE + 12)
#define GPIO_PIN_PA13 (GPIO_PIOA_BASE + 13)
#define GPIO_PIN_PA14 (GPIO_PIOA_BASE + 14)
#define GPIO_PIN_PA15 (GPIO_PIOA_BASE + 15)
#define GPIO_PIN_PA16 (GPIO_PIOA_BASE + 16)
#define GPIO_PIN_PA17 (GPIO_PIOA_BASE + 17)
#define GPIO_PIN_PA18 (GPIO_PIOA_BASE + 18)
#define GPIO_PIN_PA19 (GPIO_PIOA_BASE + 19)
#define GPIO_PIN_PA20 (GPIO_PIOA_BASE + 20)
#define GPIO_PIN_PA21 (GPIO_PIOA_BASE + 21)
#define GPIO_PIN_PA22 (GPIO_PIOA_BASE + 22)
#define GPIO_PIN_PA23 (GPIO_PIOA_BASE + 23)
#define GPIO_PIN_PA24 (GPIO_PIOA_BASE + 24)
#define GPIO_PIN_PA25 (GPIO_PIOA_BASE + 25)
#define GPIO_PIN_PA26 (GPIO_PIOA_BASE + 26)
#define GPIO_PIN_PA27 (GPIO_PIOA_BASE + 27)
#define GPIO_PIN_PA28 (GPIO_PIOA_BASE + 28)
#define GPIO_PIN_PA29 (GPIO_PIOA_BASE + 29)
#define GPIO_PIN_PA30 (GPIO_PIOA_BASE + 30)
#define GPIO_PIN_PA31 (GPIO_PIOA_BASE + 31)
#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
#define GPIO_PIN_PB0 (GPIO_PIOB_BASE + 0)
#define GPIO_PIN_PB1 (GPIO_PIOB_BASE + 1)
#define GPIO_PIN_PB2 (GPIO_PIOB_BASE + 2)
#define GPIO_PIN_PB3 (GPIO_PIOB_BASE + 3)
#define GPIO_PIN_PB4 (GPIO_PIOB_BASE + 4)
#define GPIO_PIN_PB5 (GPIO_PIOB_BASE + 5)
#define GPIO_PIN_PB6 (GPIO_PIOB_BASE + 6)
#define GPIO_PIN_PB7 (GPIO_PIOB_BASE + 7)
#define GPIO_PIN_PB8 (GPIO_PIOB_BASE + 8)
#define GPIO_PIN_PB9 (GPIO_PIOB_BASE + 9)
#define GPIO_PIN_PB10 (GPIO_PIOB_BASE + 10)
#define GPIO_PIN_PB11 (GPIO_PIOB_BASE + 11)
#define GPIO_PIN_PB12 (GPIO_PIOB_BASE + 12)
#define GPIO_PIN_PB13 (GPIO_PIOB_BASE + 13)
#define GPIO_PIN_PB14 (GPIO_PIOB_BASE + 14)
#define GPIO_PIN_PB15 (GPIO_PIOB_BASE + 15)
#define GPIO_PIN_PB16 (GPIO_PIOB_BASE + 16)
#define GPIO_PIN_PB17 (GPIO_PIOB_BASE + 17)
#define GPIO_PIN_PB18 (GPIO_PIOB_BASE + 18)
#define GPIO_PIN_PB19 (GPIO_PIOB_BASE + 19)
#define GPIO_PIN_PB20 (GPIO_PIOB_BASE + 20)
#define GPIO_PIN_PB21 (GPIO_PIOB_BASE + 21)
#define GPIO_PIN_PB22 (GPIO_PIOB_BASE + 22)
#define GPIO_PIN_PB23 (GPIO_PIOB_BASE + 23)
#define GPIO_PIN_PB24 (GPIO_PIOB_BASE + 24)
#define GPIO_PIN_PB25 (GPIO_PIOB_BASE + 25)
#define GPIO_PIN_PB26 (GPIO_PIOB_BASE + 26)
#define GPIO_PIN_PB27 (GPIO_PIOB_BASE + 27)
#define GPIO_PIN_PB28 (GPIO_PIOB_BASE + 28)
#define GPIO_PIN_PB29 (GPIO_PIOB_BASE + 29)
#define GPIO_PIN_PB30 (GPIO_PIOB_BASE + 30)
#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
#define GPIO_PIN_PC0 (GPIO_PIOC_BASE + 0)
#define GPIO_PIN_PC1 (GPIO_PIOC_BASE + 1)
#define GPIO_PIN_PC2 (GPIO_PIOC_BASE + 2)
#define GPIO_PIN_PC3 (GPIO_PIOC_BASE + 3)
#define GPIO_PIN_PC4 (GPIO_PIOC_BASE + 4)
#define GPIO_PIN_PC5 (GPIO_PIOC_BASE + 5)
#define GPIO_PIN_PC6 (GPIO_PIOC_BASE + 6)
#define GPIO_PIN_PC7 (GPIO_PIOC_BASE + 7)
#define GPIO_PIN_PC8 (GPIO_PIOC_BASE + 8)
#define GPIO_PIN_PC9 (GPIO_PIOC_BASE + 9)
#define GPIO_PIN_PC10 (GPIO_PIOC_BASE + 10)
#define GPIO_PIN_PC11 (GPIO_PIOC_BASE + 11)
#define GPIO_PIN_PC12 (GPIO_PIOC_BASE + 12)
#define GPIO_PIN_PC13 (GPIO_PIOC_BASE + 13)
#define GPIO_PIN_PC14 (GPIO_PIOC_BASE + 14)
#define GPIO_PIN_PC15 (GPIO_PIOC_BASE + 15)
#define GPIO_PIN_PC16 (GPIO_PIOC_BASE + 16)
#define GPIO_PIN_PC17 (GPIO_PIOC_BASE + 17)
#define GPIO_PIN_PC18 (GPIO_PIOC_BASE + 18)
#define GPIO_PIN_PC19 (GPIO_PIOC_BASE + 19)
#define GPIO_PIN_PC20 (GPIO_PIOC_BASE + 20)
#define GPIO_PIN_PC21 (GPIO_PIOC_BASE + 21)
#define GPIO_PIN_PC22 (GPIO_PIOC_BASE + 22)
#define GPIO_PIN_PC23 (GPIO_PIOC_BASE + 23)
#define GPIO_PIN_PC24 (GPIO_PIOC_BASE + 24)
#define GPIO_PIN_PC25 (GPIO_PIOC_BASE + 25)
#define GPIO_PIN_PC26 (GPIO_PIOC_BASE + 26)
#define GPIO_PIN_PC27 (GPIO_PIOC_BASE + 27)
#define GPIO_PIN_PC28 (GPIO_PIOC_BASE + 28)
#define GPIO_PIN_PC29 (GPIO_PIOC_BASE + 29)
#define GPIO_PIN_PC30 (GPIO_PIOC_BASE + 30)
#define GPIO_PIN_PC31 (GPIO_PIOC_BASE + 31)
#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
#define GPIO_PIN_PD0 (GPIO_PIOD_BASE + 0)
#define GPIO_PIN_PD1 (GPIO_PIOD_BASE + 1)
#define GPIO_PIN_PD2 (GPIO_PIOD_BASE + 2)
#define GPIO_PIN_PD3 (GPIO_PIOD_BASE + 3)
#define GPIO_PIN_PD4 (GPIO_PIOD_BASE + 4)
#define GPIO_PIN_PD5 (GPIO_PIOD_BASE + 5)
#define GPIO_PIN_PD6 (GPIO_PIOD_BASE + 6)
#define GPIO_PIN_PD7 (GPIO_PIOD_BASE + 7)
#define GPIO_PIN_PD8 (GPIO_PIOD_BASE + 8)
#define GPIO_PIN_PD9 (GPIO_PIOD_BASE + 9)
#define GPIO_PIN_PD10 (GPIO_PIOD_BASE + 10)
#define GPIO_PIN_PD11 (GPIO_PIOD_BASE + 11)
#define GPIO_PIN_PD12 (GPIO_PIOD_BASE + 12)
#define GPIO_PIN_PD13 (GPIO_PIOD_BASE + 13)
#define GPIO_PIN_PD14 (GPIO_PIOD_BASE + 14)
#define GPIO_PIN_PD15 (GPIO_PIOD_BASE + 15)
#define GPIO_PIN_PD16 (GPIO_PIOD_BASE + 16)
#define GPIO_PIN_PD17 (GPIO_PIOD_BASE + 17)
#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
#define GPIO_PIN_PE0 (GPIO_PIOE_BASE + 0)
#define GPIO_PIN_PE1 (GPIO_PIOE_BASE + 1)
#define GPIO_PIN_PE2 (GPIO_PIOE_BASE + 2)
#define GPIO_PIN_PE3 (GPIO_PIOE_BASE + 3)
#define GPIO_PIN_PE4 (GPIO_PIOE_BASE + 4)
#define GPIO_PIN_PE5 (GPIO_PIOE_BASE + 5)
#define GPIO_PIN_PE6 (GPIO_PIOE_BASE + 6)
#define GPIO_PIN_PE7 (GPIO_PIOE_BASE + 7)
#define GPIO_PIN_PE8 (GPIO_PIOE_BASE + 8)
#define GPIO_PIN_PE9 (GPIO_PIOE_BASE + 9)
#define GPIO_PIN_PE10 (GPIO_PIOE_BASE + 10)
#define GPIO_PIN_PE11 (GPIO_PIOE_BASE + 11)
#define GPIO_PIN_PE12 (GPIO_PIOE_BASE + 12)
#define GPIO_PIN_PE13 (GPIO_PIOE_BASE + 13)
#define GPIO_PIN_PE14 (GPIO_PIOE_BASE + 14)
#define GPIO_PIN_PE15 (GPIO_PIOE_BASE + 15)
#define GPIO_PIN_PE16 (GPIO_PIOE_BASE + 16)
#define GPIO_PIN_PE17 (GPIO_PIOE_BASE + 17)
#define GPIO_PIN_PE18 (GPIO_PIOE_BASE + 18)
#define GPIO_PIN_PE19 (GPIO_PIOE_BASE + 19)
#define GPIO_PIN_PE20 (GPIO_PIOE_BASE + 20)
#define GPIO_PIN_PE21 (GPIO_PIOE_BASE + 21)
#define GPIO_PIN_PE22 (GPIO_PIOE_BASE + 22)
#define GPIO_PIN_PE23 (GPIO_PIOE_BASE + 23)
#define GPIO_PIN_PE24 (GPIO_PIOE_BASE + 24)
#define GPIO_PIN_PE25 (GPIO_PIOE_BASE + 25)
#define GPIO_PIN_PE26 (GPIO_PIOE_BASE + 26)
static inline void *gpio_pin_to_addr(unsigned int pin)
{
switch (pin >> 5) {
case 0:
return (void *)PIOA_BASE;
case 1:
return (void *)PIOB_BASE;
case 2:
return (void *)PIOC_BASE;
case 3:
return (void *)PIOD_BASE;
case 4:
return (void *)PIOE_BASE;
default:
return NULL;
}
}
void gpio_select_periph_A(unsigned int pin, int use_pullup);
void gpio_select_periph_B(unsigned int pin, int use_pullup);
void gpio_enable_ebi(void);
void gpio_enable_usart0(void);
void gpio_enable_usart1(void);
void gpio_enable_usart2(void);
void gpio_enable_usart3(void);
void gpio_enable_macb0(void);
void gpio_enable_macb1(void);
void gpio_enable_mmci(void);
#endif /* __ASM_AVR32_ARCH_GPIO_H__ */

8
include/asm-avr32/arch-at32ap7000/hmatrix2.h
View File

@@ -224,9 +224,9 @@
| HMATRIX2_BF(name,value))
/* Register access macros */
#define hmatrix2_readl(port,reg) \
readl((port)->regs + HMATRIX2_##reg)
#define hmatrix2_writel(port,reg,value) \
writel((value), (port)->regs + HMATRIX2_##reg)
#define hmatrix2_readl(reg) \
readl((void *)HMATRIX_BASE + HMATRIX2_##reg)
#define hmatrix2_writel(reg,value) \
writel((value), (void *)HMATRIX_BASE + HMATRIX2_##reg)
#endif /* __ASM_AVR32_HMATRIX2_H__ */

81
include/asm-avr32/arch-at32ap7000/memory-map.h
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@@ -19,43 +19,48 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__
#define __ASM_AVR32_PART_MEMORY_MAP_H__
#ifndef __AT32AP7000_MEMORY_MAP_H__
#define __AT32AP7000_MEMORY_MAP_H__
#define AUDIOC_BASE 0xFFF02800
#define DAC_BASE 0xFFF02000
#define DMAC_BASE 0xFF200000
#define ECC_BASE 0xFFF03C00
#define HISI_BASE 0xFFF02C00
#define HMATRIX_BASE 0xFFF00800
#define HSDRAMC_BASE 0xFFF03800
#define HSMC_BASE 0xFFF03400
#define LCDC_BASE 0xFF000000
#define MACB0_BASE 0xFFF01800
#define MACB1_BASE 0xFFF01C00
#define MMCI_BASE 0xFFF02400
#define PIOA_BASE 0xFFE02800
#define PIOB_BASE 0xFFE02C00
#define PIOC_BASE 0xFFE03000
#define PIOD_BASE 0xFFE03400
#define PIOE_BASE 0xFFE03800
#define PSIF_BASE 0xFFE03C00
#define PWM_BASE 0xFFF01400
#define SM_BASE 0xFFF00000
#define INTC_BASE 0XFFF00400
#define SPI0_BASE 0xFFE00000
#define SPI1_BASE 0xFFE00400
#define SSC0_BASE 0xFFE01C00
#define SSC1_BASE 0xFFE02000
#define SSC2_BASE 0xFFE02400
#define TIMER0_BASE 0xFFF00C00
#define TIMER1_BASE 0xFFF01000
#define TWI_BASE 0xFFE00800
#define USART0_BASE 0xFFE00C00
#define USART1_BASE 0xFFE01000
#define USART2_BASE 0xFFE01400
#define USART3_BASE 0xFFE01800
#define USB_FIFO 0xFF300000
#define USB_BASE 0xFFF03000
/* Devices on the High Speed Bus (HSB) */
#define LCDC_BASE 0xFF000000
#define DMAC_BASE 0xFF200000
#define USB_FIFO 0xFF300000
#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */
/* Devices on Peripheral Bus A (PBA) */
#define SPI0_BASE 0xFFE00000
#define SPI1_BASE 0xFFE00400
#define TWI_BASE 0xFFE00800
#define USART0_BASE 0xFFE00C00
#define USART1_BASE 0xFFE01000
#define USART2_BASE 0xFFE01400
#define USART3_BASE 0xFFE01800
#define SSC0_BASE 0xFFE01C00
#define SSC1_BASE 0xFFE02000
#define SSC2_BASE 0xFFE02400
#define PIOA_BASE 0xFFE02800
#define PIOB_BASE 0xFFE02C00
#define PIOC_BASE 0xFFE03000
#define PIOD_BASE 0xFFE03400
#define PIOE_BASE 0xFFE03800
#define PSIF_BASE 0xFFE03C00
/* Devices on Peripheral Bus B (PBB) */
#define SM_BASE 0xFFF00000
#define INTC_BASE 0xFFF00400
#define HMATRIX_BASE 0xFFF00800
#define TIMER0_BASE 0xFFF00C00
#define TIMER1_BASE 0xFFF01000
#define PWM_BASE 0xFFF01400
#define MACB0_BASE 0xFFF01800
#define MACB1_BASE 0xFFF01C00
#define DAC_BASE 0xFFF02000
#define MMCI_BASE 0xFFF02400
#define AUDIOC_BASE 0xFFF02800
#define HISI_BASE 0xFFF02C00
#define USB_BASE 0xFFF03000
#define HSMC_BASE 0xFFF03400
#define HSDRAMC_BASE 0xFFF03800
#define ECC_BASE 0xFFF03C00
#endif /* __AT32AP7000_MEMORY_MAP_H__ */

96
include/asm-avr32/arch-at32ap7000/mmc.h Normal file
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@@ -0,0 +1,96 @@
/*
* Copyright (C) 2004-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_AVR32_MMC_H
#define __ASM_AVR32_MMC_H
struct mmc_cid {
unsigned long psn;
unsigned short oid;
unsigned char mid;
unsigned char prv;
unsigned char mdt;
char pnm[7];
};
struct mmc_csd
{
u8 csd_structure:2,
spec_vers:4,
rsvd1:2;
u8 taac;
u8 nsac;
u8 tran_speed;
u16 ccc:12,
read_bl_len:4;
u64 read_bl_partial:1,
write_blk_misalign:1,
read_blk_misalign:1,
dsr_imp:1,
rsvd2:2,
c_size:12,
vdd_r_curr_min:3,
vdd_r_curr_max:3,
vdd_w_curr_min:3,
vdd_w_curr_max:3,
c_size_mult:3,
sector_size:5,
erase_grp_size:5,
wp_grp_size:5,
wp_grp_enable:1,
default_ecc:2,
r2w_factor:3,
write_bl_len:4,
write_bl_partial:1,
rsvd3:5;
u8 file_format_grp:1,
copy:1,
perm_write_protect:1,
tmp_write_protect:1,
file_format:2,
ecc:2;
u8 crc:7;
u8 one:1;
};
/* MMC Command numbers */
#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
#define MMC_CMD_ALL_SEND_CID 2
#define MMC_CMD_SET_RELATIVE_ADDR 3
#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3
#define MMC_CMD_SET_DSR 4
#define MMC_CMD_SELECT_CARD 7
#define MMC_CMD_SEND_CSD 9
#define MMC_CMD_SEND_CID 10
#define MMC_CMD_SEND_STATUS 13
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
#define MMC_CMD_WRITE_BLOCK 24
#define MMC_CMD_APP_CMD 55
#define MMC_ACMD_SD_SEND_OP_COND 41
#define R1_ILLEGAL_COMMAND (1 << 22)
#define R1_APP_CMD (1 << 5)
#endif /* __ASM_AVR32_MMC_H */

146
include/asm-avr32/arch-at32ap7000/platform.h
View File

@@ -1,146 +0,0 @@
/*
* Copyright (C) 2005-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_AVR32_ARCH_PM_H
#define _ASM_AVR32_ARCH_PM_H
#include <config.h>
enum clock_domain_id {
CLOCK_CPU,
CLOCK_HSB,
CLOCK_PBA,
CLOCK_PBB,
NR_CLOCK_DOMAINS,
};
enum resource_type {
RESOURCE_GPIO,
RESOURCE_CLOCK,
};
enum gpio_func {
GPIO_FUNC_GPIO,
GPIO_FUNC_A,
GPIO_FUNC_B,
};
enum device_id {
DEVICE_HEBI,
DEVICE_PBA_BRIDGE,
DEVICE_PBB_BRIDGE,
DEVICE_HRAMC,
/* GPIO controllers must be kept together */
DEVICE_PIOA,
DEVICE_PIOB,
DEVICE_PIOC,
DEVICE_PIOD,
DEVICE_PIOE,
DEVICE_SM,
DEVICE_INTC,
DEVICE_HMATRIX,
#if defined(CFG_HPDC)
DEVICE_HPDC,
#endif
#if defined(CFG_MACB0)
DEVICE_MACB0,
#endif
#if defined(CFG_MACB1)
DEVICE_MACB1,
#endif
#if defined(CFG_LCDC)
DEVICE_LCDC,
#endif
#if defined(CFG_USART0)
DEVICE_USART0,
#endif
#if defined(CFG_USART1)
DEVICE_USART1,
#endif
#if defined(CFG_USART2)
DEVICE_USART2,
#endif
#if defined(CFG_USART3)
DEVICE_USART3,
#endif
#if defined(CFG_MMCI)
DEVICE_MMCI,
#endif
#if defined(CFG_DMAC)
DEVICE_DMAC,
#endif
NR_DEVICES,
NO_DEVICE = -1,
};
struct resource {
enum resource_type type;
union {
struct {
unsigned long base;
} iomem;
struct {
unsigned char nr_pins;
enum device_id gpio_dev;
enum gpio_func func;
unsigned short start;
} gpio;
struct {
enum clock_domain_id id;
unsigned char index;
} clock;
} u;
};
struct device {
void *regs;
unsigned int nr_resources;
const struct resource *resource;
};
struct clock_domain {
unsigned short reg;
enum clock_domain_id id;
enum device_id bridge;
};
extern const struct device chip_device[NR_DEVICES];
extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS];
/**
* Set up PIO, clock management and I/O memory for a device.
*/
const struct device *get_device(enum device_id devid);
void put_device(const struct device *dev);
int gpio_set_func(enum device_id gpio_devid, unsigned int start,
unsigned int nr_pins, enum gpio_func func);
void gpio_free(enum device_id gpio_devid, unsigned int start,
unsigned int nr_pins);
void pm_init(void);
int pm_enable_clock(enum clock_domain_id id, unsigned int index);
void pm_disable_clock(enum clock_domain_id id, unsigned int index);
unsigned long pm_get_clock_freq(enum clock_domain_id domain);
void cpu_enable_sdram(void);
#endif /* _ASM_AVR32_ARCH_PM_H */

4
include/asm-avr32/global_data.h
View File

@@ -35,10 +35,8 @@
typedef struct global_data {
bd_t *bd;
unsigned long flags;
const struct device *console_uart;
const struct device *sm;
unsigned long baudrate;
unsigned long sdram_size;
unsigned long stack_end; /* highest stack address */
unsigned long have_console; /* serial_init() was called */
unsigned long reloc_off; /* Relocation Offset */
unsigned long env_addr; /* Address of env struct */

2
include/asm-avr32/initcalls.h
View File

@@ -26,8 +26,6 @@
extern int cpu_init(void);
extern int timer_init(void);
extern void board_init_memories(void);
extern void board_init_pio(void);
extern void board_init_info(void);
#endif /* __ASM_AVR32_INITCALLS_H__ */

172
include/asm-blackfin/arch-bf533/anomaly.h Normal file
View File

@@ -0,0 +1,172 @@
/*
* File: include/asm-blackfin/arch-bf533/anomaly.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* This file shoule be up to date with:
* - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
* - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
* - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* We do not support 0.1 or 0.2 silicon - sorry */
#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
#error Kernel will not work on BF533 Version 0.1 or 0.2
#endif
/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
slot1 and store of a P register in slot 2 is not
supported */
#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
every corresponding match */
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
Channel DMA stops */
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
registers. */
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
upper bits*/
#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
syncs */
#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
functional */
#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
state */
#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
VDDint <=0.9V */
#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
an edge is detected may clear interrupt */
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
DMA system instability */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
not restored */
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
control */
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
killed in a particular stage*/
#endif
/* These issues only occur on 0.3 or 0.4 BF533 */
#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
updated at the same time. */
#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
Cache Fill can be corrupted after or during
Instruction DMA if certain core stalls exist */
#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
Purpose TX or RX modes */
#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
preceding memory read */
#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
inactive channels in certain conditions */
#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
situation */
#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
data*/
#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
Differences in certain Conditions */
#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
hardware reset */
#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
IDLE around a Change of Control causes
unpredictable results */
#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
shadow of a conditional branch */
#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
errors */
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
interrupt not functional */
#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
loops may cause the instruction fetch unit to
malfunction */
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
the ICPLB Data registers differ */
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
#define ANOMALY_05000262 /* Stores to data cache may be lost */
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
instruction will cause an infinite stall in the
second to last instruction in a hardware loop */
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
SPORT external receive and transmit clocks. */
#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
internal voltage regulator (VDDint) to increase. */
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
internal voltage regulator (VDDint) to decrease */
#endif
/* These issues are only on 0.4 silicon */
#if (defined(CONFIG_BF_REV_0_4))
#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
(TDM) */
#endif
/* These issues are only on 0.3 silicon */
#if defined(CONFIG_BF_REV_0_3)
#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
External Frame Syncs */
#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
Instruction or Data Fetches, or by Fetches at the
boundary of reserved memory space */
#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
when polarity setting is changed */
#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
corruption */
#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
fix */
#define ANOMALY_05000201 /* Receive frame sync not ignored during active
frames in sport MCM */
#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
stopping */
#if defined(CONFIG_BF533)
#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
allocate cache lines on reads only mode */
#endif /* CONFIG_BF533 */
#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
instructions */
#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
Sync Transmit Mode */
#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
#endif
#endif /* _MACH_ANOMALY_H_ */

7
include/asm-blackfin/cpu/bf533_serial.h → include/asm-blackfin/arch-bf533/bf533_serial.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot bf533_serial.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,11 +18,10 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF533_SERIAL_H_
#define _BF533_SERIAL_H_

6
include/asm-blackfin/cpu/bf533_rtc.h → include/asm-blackfin/arch-bf533/bf5xx_rtc.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - bf533_rtc.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF533_RTC_H_

2
include/asm-blackfin/cpu/cdefBF531.h → include/asm-blackfin/arch-bf533/cdefBF531.h
View File

@@ -19,6 +19,6 @@
#ifndef _CDEFBF531_H
#define _CDEFBF531_H
#include <cdefBF532.h>
#include <asm/arch-bf533/cdefBF532.h>
#endif /* _CDEFBF531_H */

4
include/asm-blackfin/cpu/cdefBF532.h → include/asm-blackfin/arch-bf533/cdefBF532.h
View File

@@ -26,10 +26,10 @@
*/
/* include all Core registers and bit definitions */
#include <asm/cpu/defBF532.h>
#include <asm/arch-bf533/defBF532.h>
/* include core specific register pointer definitions */
#include <asm/cpu/cdef_LPBlackfin.h>
#include <asm/arch-common/cdef_LPBlackfin.h>
/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)

2
include/asm-blackfin/cpu/cdefBF533.h → include/asm-blackfin/arch-bf533/cdefBF533.h
View File

@@ -19,6 +19,6 @@
#ifndef _CDEFBF533_H
#define _CDEFBF533_H
#include <asm/cpu/cdefBF532.h>
#include <asm/arch-bf533/cdefBF532.h>
#endif /* _CDEFBF533_H */

0
include/asm-blackfin/cpu/defBF531.h → include/asm-blackfin/arch-bf533/defBF531.h
View File

146
include/asm-blackfin/cpu/defBF532.h → include/asm-blackfin/arch-bf533/defBF532.h
View File

@@ -28,7 +28,7 @@
*/
/* include all Core registers and bit definitions */
#include <asm/cpu/def_LPBlackfin.h>
#include <asm/arch-common/def_LPBlackfin.h>
/* Helper macros
* usage:
@@ -51,7 +51,7 @@
#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */
#define CHIPID 0xFFC00014 /* Chip ID register (32-bit) */
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
#define SYSCR 0xFFC00104 /* System Configuration register */
@@ -88,7 +88,7 @@
#define UART_LCR 0xFFC0040C /* Line Control Register */
#define UART_MCR 0xFFC00410 /* Modem Control Register */
#define UART_LSR 0xFFC00414 /* Line Status Register */
/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */
/* #define UART_MSR 0xFFC00418 */ /* Modem Status Register (UNUSED in ADSP-BF532) */
#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
#define UART_GCTL 0xFFC00424 /* Global Control Register */
@@ -405,7 +405,7 @@
#define BYPASS 0x00000100 /* Bypass the PLL */
/* PLL_DIV Masks */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
@@ -420,7 +420,7 @@
*/
/* SIC_IAR0 Masks */
#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
#define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
#define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
#define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
#define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
@@ -430,7 +430,7 @@
#define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
/* SIC_IAR1 Masks */
#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
#define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
#define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
#define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
#define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
@@ -440,7 +440,7 @@
#define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
/* SIC_IAR2 Masks */
#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
#define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
#define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
#define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
#define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
@@ -486,25 +486,25 @@
#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
/* RTC_ICTL register */
#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
#define AIE 0x0002 /* Alarm Interrupt Enable */
#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
#define MIE 0x0008 /* Minutes Interrupt Enable */
#define HIE 0x0010 /* Hours Interrupt Enable */
#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
#define WCIE 0x8000 /* Write Complete Interrupt Enable */
#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
#define AIE 0x0002 /* Alarm Interrupt Enable */
#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
#define MIE 0x0008 /* Minutes Interrupt Enable */
#define HIE 0x0010 /* Hours Interrupt Enable */
#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
#define WCIE 0x8000 /* Write Complete Interrupt Enable */
/* RTC_ISTAT register */
#define SWEF 0x0001 /* Stopwatch Event Flag */
#define AEF 0x0002 /* Alarm Event Flag */
#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
#define MEF 0x0008 /* Minutes Event Flag */
#define HEF 0x0010 /* Hours Event Flag */
#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
#define WPS 0x4000 /* Write Pending Status (RO) */
#define WCOM 0x8000 /* Write Complete */
#define SWEF 0x0001 /* Stopwatch Event Flag */
#define AEF 0x0002 /* Alarm Event Flag */
#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
#define MEF 0x0008 /* Minutes Event Flag */
#define HEF 0x0010 /* Hours Event Flag */
#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
#define WPS 0x4000 /* Write Pending Status (RO) */
#define WCOM 0x8000 /* Write Complete */
/* RTC_FAST Mask (RTC_PREN Mask) */
#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
@@ -588,50 +588,50 @@
* SERIAL PORT MASKS
*/
/* SPORTx_TCR1 Masks */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
#define TSPEN 0x0001 /* TX enable */
#define ITCLK 0x0002 /* Internal TX Clock Select */
#define TDTYPE 0x000C /* TX Data Formatting Select */
#define TLSBIT 0x0010 /* TX Bit Order */
#define ITFS 0x0200 /* Internal TX Frame Sync Select */
#define TFSR 0x0400 /* TX Frame Sync Required Select */
#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
#define LTFS 0x1000 /* Low TX Frame Sync Select */
#define LATFS 0x2000 /* Late TX Frame Sync Select */
#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
/* SPORTx_TCR2 Masks */
#define SLEN 0x001F /*TX Word Length */
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
#define SLEN 0x001F /*TX Word Length */
#define TXSE 0x0100 /*TX Secondary Enable */
#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
#define TRFST 0x0400 /*TX Right-First Data Order */
/* SPORTx_RCR1 Masks */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define RULAW 0x0008 /* u-Law enable */
#define RALAW 0x000C /* A-Law enable */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
#define RSPEN 0x0001 /* RX enable */
#define IRCLK 0x0002 /* Internal RX Clock Select */
#define RDTYPE 0x000C /* RX Data Formatting Select */
#define RULAW 0x0008 /* u-Law enable */
#define RALAW 0x000C /* A-Law enable */
#define RLSBIT 0x0010 /* RX Bit Order */
#define IRFS 0x0200 /* Internal RX Frame Sync Select */
#define RFSR 0x0400 /* RX Frame Sync Required Select */
#define LRFS 0x1000 /* Low RX Frame Sync Select */
#define LARFS 0x2000 /* Late RX Frame Sync Select */
#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
/* SPORTx_RCR2 Masks */
#define SLEN 0x001F /* RX Word Length */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
#define SLEN 0x001F /* RX Word Length */
#define RXSE 0x0100 /* RX Secondary Enable */
#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
#define RRFST 0x0400 /* Right-First Data Order */
/* SPORTx_STAT Masks */
#define RXNE 0x0001 /* RX FIFO Not Empty Status */
#define RUVF 0x0002 /* RX Underflow Status */
#define ROVF 0x0004 /* RX Overflow Status */
#define TXF 0x0008 /* TX FIFO Full Status */
#define TUVF 0x0010 /* TX Underflow Status */
#define TOVF 0x0020 /* TX Overflow Status */
#define TXHRE 0x0040 /* TX Hold Register Empty */
#define RXNE 0x0001 /* RX FIFO Not Empty Status */
#define RUVF 0x0002 /* RX Underflow Status */
#define ROVF 0x0004 /* RX Overflow Status */
#define TXF 0x0008 /* TX FIFO Full Status */
#define TUVF 0x0010 /* TX Underflow Status */
#define TOVF 0x0020 /* TX Overflow Status */
#define TXHRE 0x0040 /* TX Hold Register Empty */
/* SPORTx_MCMC1 Masks */
#define WSIZE 0x0000F000 /* Multichannel Window Size Field */
@@ -660,7 +660,7 @@
#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
#define DLENGTH 0x00003800 /* PPI Data Length */
#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
#define POL 0x0000C000 /* PPI Signal Polarities */
@@ -689,12 +689,12 @@
#define NDSIZE 0x00000900 /* Next Descriptor Size */
#define FLOW 0x00007000 /* Flow Control */
#define DMAEN_P 0 /* Channel Enable */
#define WNR_P 1 /* Channel Direction (W/R*) */
#define DMA2D_P 4 /* 2D/1D* Mode */
#define RESTART_P 5 /* Restart */
#define DI_SEL_P 6 /* Data Interrupt Select */
#define DI_EN_P 7 /* Data Interrupt Enable */
#define DMAEN_P 0 /* Channel Enable */
#define WNR_P 1 /* Channel Direction (W/R*) */
#define DMA2D_P 4 /* 2D/1D* Mode */
#define RESTART_P 5 /* Restart */
#define DI_SEL_P 6 /* Data Interrupt Select */
#define DI_EN_P 7 /* Data Interrupt Enable */
/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
#define DMA_DONE 0x00000001 /* DMA Done Indicator */
@@ -702,14 +702,14 @@
#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
#define DMA_RUN 0x00000008 /* DMA Running Indicator */
#define DMA_DONE_P 0 /* DMA Done Indicator */
#define DMA_ERR_P 1 /* DMA Error Indicator */
#define DFETCH_P 2 /* Descriptor Fetch Indicator */
#define DMA_RUN_P 3 /* DMA Running Indicator */
#define DMA_DONE_P 0 /* DMA Done Indicator */
#define DMA_ERR_P 1 /* DMA Error Indicator */
#define DFETCH_P 2 /* Descriptor Fetch Indicator */
#define DMA_RUN_P 3 /* DMA Running Indicator */
/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
@@ -1156,4 +1156,4 @@
#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
#define BGSTAT 0x00000020 /* Bus granted */
#endif /* _DEF_BF532_H */
#endif /* _DEF_BF532_H */

0
include/asm-blackfin/cpu/defBF533.h → include/asm-blackfin/arch-bf533/defBF533.h
View File

5
include/asm-blackfin/cpu/defBF533_extn.h → include/asm-blackfin/arch-bf533/defBF533_extn.h
View File

@@ -19,9 +19,10 @@
#ifndef _DEF_BF533_EXTN_H
#define _DEF_BF533_EXTN_H
#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
/* define macro for offset */
#define OFFSET_( x ) ((x) & 0x0000FFFF)
/* Delay inserted for PLL transition */
#define DELAY 0x1000
#define PLL_DELAY 0x1000
#define L1_ISRAM 0xFFA00000
#define L1_ISRAM_END 0xFFA10000

6
include/asm-blackfin/cpu/bf533_irq.h → include/asm-blackfin/arch-bf533/irq.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot bf533_irq.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
@@ -33,8 +33,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF533_IRQ_H_

116
include/asm-blackfin/arch-bf537/anomaly.h Normal file
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@@ -0,0 +1,116 @@
/*
* File: include/asm-blackfin/arch-bf537/anomaly.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/* This file shoule be up to date with:
* - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
* - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
* - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* We do not support 0.1 silicon - sorry */
#if (defined(CONFIG_BF_REV_0_1))
#error Kernel will not work on BF537/6/4 Version 0.1
#endif
#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
slot1 and store of a P register in slot 2 is not
supported */
#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
Channel DMA stops */
#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
registers. */
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
upper bits */
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
syncs */
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
Changed */
#endif
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
SPORT external receive and transmit clocks. */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
VDDint <=0.9V */
#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
an edge is detected may clear interrupt */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
not restored */
#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
control */
#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
killed in a particular stage */
#endif
#if defined(CONFIG_BF_REV_0_2)
#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
IDLE around a Change of Control causes
unpredictable results */
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
(TDM) */
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
#endif
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
interrupt not functional */
#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
#endif
#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
loops may cause the instruction fetch unit to
malfunction */
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
the ICPLB Data registers differ */
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
#define ANOMALY_05000262 /* Stores to data cache may be lost */
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
instruction will cause an infinite stall in the
second to last instruction in a hardware loop */
#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
and non-zero DEB_TRAFFIC_PERIOD value */
#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
internal voltage regulator (VDDint) to decrease */
#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
an edge is detected may clear interrupt */
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
DMA system instability */
#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
Atmel Dataflash devices */
#endif /* CONFIG_BF_REV_0_2 */
#endif /* _MACH_ANOMALY_H_ */

78
include/asm-blackfin/arch-bf537/bf537_serial.h Normal file
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@@ -0,0 +1,78 @@
/*
* U-boot bf537_serial.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF537_SERIAL_H_
#define _BF537_SERIAL_H_
#define BYTE_REF(addr) (*((volatile char*)addr))
#define HALFWORD_REF(addr) (*((volatile short*)addr))
#define WORD_REF(addr) (*((volatile long*)addr))
#define UART_THR_LO HALFWORD_REF(UART_THR)
#define UART_RBR_LO HALFWORD_REF(UART_RBR)
#define UART_DLL_LO HALFWORD_REF(UART_DLL)
#define UART_IER_LO HALFWORD_REF(UART_IER)
#define UART_IER_ERBFI 0x01
#define UART_IER_ETBEI 0x02
#define UART_IER_ELSI 0x04
#define UART_IER_EDDSI 0x08
#define UART_DLH_LO HALFWORD_REF(UART_DLH)
#define UART_IIR_LO HALFWORD_REF(UART_IIR)
#define UART_IIR_NOINT 0x01
#define UART_IIR_STATUS 0x06
#define UART_IIR_LSR 0x06
#define UART_IIR_RBR 0x04
#define UART_IIR_THR 0x02
#define UART_IIR_MSR 0x00
#define UART_LCR_LO HALFWORD_REF(UART_LCR)
#define UART_LCR_WLS5 0
#define UART_LCR_WLS6 0x01
#define UART_LCR_WLS7 0x02
#define UART_LCR_WLS8 0x03
#define UART_LCR_STB 0x04
#define UART_LCR_PEN 0x08
#define UART_LCR_EPS 0x10
#define UART_LCR_SP 0x20
#define UART_LCR_SB 0x40
#define UART_LCR_DLAB 0x80
#define UART_MCR_LO HALFWORD_REF(UART_MCR)
#define UART_LSR_LO HALFWORD_REF(UART_LSR)
#define UART_LSR_DR 0x01
#define UART_LSR_OE 0x02
#define UART_LSR_PE 0x04
#define UART_LSR_FE 0x08
#define UART_LSR_BI 0x10
#define UART_LSR_THRE 0x20
#define UART_LSR_TEMT 0x40
#define UART_MSR_LO HALFWORD_REF(UART_MSR)
#define UART_SCR_LO HALFWORD_REF(UART_SCR)
#define UART_GCTL_LO HALFWORD_REF(UART_GCTL)
#define UART_GCTL_UCEN 0x01
#endif

46
include/asm-blackfin/arch-bf537/bf5xx_rtc.h Normal file
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@@ -0,0 +1,46 @@
/*
* U-boot - bf537_rtc.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF537_RTC_H_
#define _BF537_RTC_H_
void rtc_init(void);
void wait_for_complete(void);
void rtc_reset(void);
#define MIN_TO_SECS(_x_) (60 * _x_)
#define HRS_TO_SECS(_x_) (60 * 60 * _x_)
#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_)
#define NUM_SECS_IN_DAY (24 * 3600)
#define NUM_SECS_IN_HOUR (3600)
#define NUM_SECS_IN_MIN (60)
/* Shift values for RTC_STAT register */
#define DAY_BITS_OFF 17
#define HOUR_BITS_OFF 12
#define MIN_BITS_OFF 6
#define SEC_BITS_OFF 0
#endif

1009
include/asm-blackfin/arch-bf537/cdefBF534.h Normal file
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File diff suppressed because it is too large Load Diff

186
include/asm-blackfin/arch-bf537/cdefBF537.h Normal file
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@@ -0,0 +1,186 @@
/*
* Copyright (C) 2004 Analog Devices Inc., All Rights Reserved.
*
***********************************************************************************
*
* This include file contains a list of macro "defines" to enable the programmer
* to use symbolic names for register-access.
*
* ----------------------------
* revision 0.1
* date: 2004/03/01 21:23:01; author: joeb
* Initial revision
*
* ----------------------------
* revision 0.2
* date: 2004/05/15 16:30:00; author: joeb
* comments: removed I2C/IIC references to TWI, changed GPIO sections
*
* ----------------------------
* revision 0.3
* date: 2004/06/08 12:25:00; author: joeb
* comments: renamed some TWI and GPIO registers
*
* ----------------------------
* revision 0.4
* date: 2004/06/09 14:25:00; author: joeb
* comments: changed Timer status register to 32-bit, renamed EMAC count registers
*
* ----------------------------
* revision 0.5
* date: 2004/08/10 10:25:00; author: joeb
* comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
*
* ----------------------------
* revision 0.6
* date: 2004/08/17 16:25:00; author: joeb
* comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
*
* ----------------------------
* revision 0.7
* date: 2004/08/18 13:21:00; author: joeb
* comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
*
* ----------------------------
* revision 0.8
* date: 2004/08/20 10:27:00; author: joeb
* comments: Renamed External DMA to Handshake DMA
*
* ----------------------------
* revision 0.9
* date: 2004/08/23 13:42:00; author: joeb
* comments: Renamed Handshake DMA Register Set
*
* ----------------------------
* revision 0.10
* date: 2004/10/28 15:40:00; author: joeb
* comments: Shortened EMAC Count Register Names
*
* ----------------------------
* revision 0.11
* date: 2004/12/13 11:05:00; author: joeb
* comments: Fixed address pointers - (volatile void **) to (void * volatile *)
*
* ----------------------------
* revision 0.12
* date: 2004/12/17 14:25:00; author: joeb
* comments: Replaced C++ Single-Line Comments w/C-standard Comments
* Changed EMAC EQ1024 TX/RX References to GE1024
*
* ----------------------------
* revision 0.13
* date: 2005/01/05 10:50:00; author: joeb
* comments: Removed excess white space in CAN_AM section
* Added support for CAN Macros to Index AM and Mailbox Areas
*
* ----------------------------
* revision 0.14
* date: 2005/01/26 14:10:00; author: joeb
* comments: Fixed Typo In EMAC_RXC_PAUSE register
*
* ----------------------------
* revision 0.15
* date: 2005/01/27 14:41:00; author: joeb
* comments: Moved Common MMRs to cdefBF534.h
*/
/*
* System MMR Register Map
*/
#ifndef _CDEF_BF537_H
#define _CDEF_BF537_H
/* Include MMRs Common to BF534 */
#include <asm/arch-bf537/cdefBF534.h>
/* Include all Core registers and bit definitions */
#include <asm/arch-bf537/defBF537.h>
/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
#endif /* _CDEF_BF537_H */

2627
include/asm-blackfin/arch-bf537/defBF534.h Normal file
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File diff suppressed because it is too large Load Diff

488
include/asm-blackfin/arch-bf537/defBF537.h Normal file
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@@ -0,0 +1,488 @@
/*
* Copyright (C) 2004-2005 Analog Devices Inc., All Rights Reserved.
*
***********************************************************************************
*
* This include file contains a list of macro "defines" to enable the programmer
* to use symbolic names for register-access and bit-manipulation.
*
* ----------------------------
* revision 0.1
* date: 2004/03/01 21:23:01; author: joeb
* Initial revision
*
* ----------------------------
* revision 0.2
* date: 2004/05/15 16:30:00; author: joeb
* comments: removed I2C/IIC references, changed GPIO sections
*
* ----------------------------
* revision 0.3
* date: 2004/06/08 12:25:00; author: joeb
* comments: fixed mis-mapped TIMER registers, changed TWI register names, fixed
* FLAG references in GPIO register names
*
* ----------------------------
* revision 0.4
* date: 2004/06/09 2:25:00; author: joeb
* comments: fixed bit-defines for EMAC section, renamed EMAC count registers,
* combined 2 Timer status registers into one
*
* ----------------------------
* revision 0.5
* date: 2004/08/10 10:25:00; author: joeb
* comments: Renamed EMAC wake-up registers, changed bit-names in EMAC registers
*
* ----------------------------
* revision 0.6
* date: 2004/08/17 16:25:00; author: joeb
* comments: Renamed TWI_INT_ENABLE to TWI_INT_MASK
*
* ----------------------------
* revision 0.7
* date: 2004/08/18 13:21:00; author: joeb
* comments: Renamed GPIO registers to remove _D, _S, _C, _T suffixes
*
* ----------------------------
* revision 0.8
* date: 2004/08/20 10:24:00; author: joeb
* comments: Renamed External DMA to Handshake MDMA
*
* ----------------------------
* revision 0.9
* date: 2004/08/23 13:42:00; author: joeb
* comments: Renamed Handshake DMA Register Set
*
* ----------------------------
* revision 0.10
* date: 2004/09/07 11:21:00; author: joeb
* comments: Fixed EMAC TX/RX DMA Priority (DMA and SIC Bit Names)
*
* ----------------------------
* revision 0.11
* date: 2004/09/28 15:14:00; author: joeb
* comments: Fixed CAN Mailbox Area
*
* ----------------------------
* revision 0.12
* date: 2004/10/27 13:18:00; author: joeb
* comments: Added IEEE EMAC Register Support
*
* ----------------------------
* revision 0.13
* date: 2004/10/28 15:40:00; author: joeb
* comments: Shortened EMAC Count Register Names
*
* ----------------------------
* revision 0.14
* date: 2004/11/09 10:45:00; author: joeb
* comments: Fixed WDSIZE macros
*
* ----------------------------
* revision 0.15
* date: 2004/11/18 07:45:00; author: joeb
* comments: Fixed TIMER_STATUS register, added EMAC macros
*
* ----------------------------
* revision 0.16
* date: 2004/12/13 11:05:00; author: joeb
* comments: Removed HI/LO macros (now Assembler mnemonics)
* Renamed enable bit for HMDMA from EN to HMDMAEN
*
* ----------------------------
* revision 0.17
* date: 2004/12/17 14:25:00; author: joeb
* comments: Replaced C++ Single-Line Comments w/C-standard Comments
* Changed EMAC EQ1024 TX/RX References to GE1024
*
* ----------------------------
* revision 0.18
* date: 2005/01/05 10:50:00; author: joeb
* comments: Added CAN Macros To Index Mailbox Area and Acceptance Masks
* Added mask values for field deposit protection
*
* ----------------------------
* revision 0.19
* date: 2005/01/10 10:30:00; author: joeb
* comments: Made all Macro argument syntax compliant to MISRA-C 2004 rule 19.10.
*
* ----------------------------
* revision 0.20
* date: 2005/01/27 14:25:15; author: joeb
* comments: Moved MMRs common to BF534 to BF534 header.
*/
#ifndef _DEF_BF537_H
#define _DEF_BF537_H
/* Include all Core registers and bit definitions */
#include <asm/arch-common/def_LPBlackfin.h>
/* Include all MMR and bit defines common to BF534 */
#include <asm/arch-bf537/defBF534.h>
/*
* Define EMAC Section Unique to BF536/BF537
*/
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 <= x < 128 */
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
/* Listing for IEEE-Supported Count Registers */
#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 <= x < 128 */
#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 <= x < 128 */
#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
/*
* System MMR Register Bits And Macros
*
* Disclaimer: All macros are intended to make C and Assembly code more readable.
* Use these macros carefully, as any that do left shifts for field
* depositing will result in the lower order bits being destroyed. Any
* macro that shifts left to properly position the bit-field should be
* used as part of an OR to initialize a register and NOT as a dynamic
* modifier UNLESS the lower order bits are saved and ORed back in when
* the macro is used.
*/
/*
* ETHERNET 10/100 CONTROLLER MASKS
*/
/* EMAC_OPMODE Masks */
#define RE 0x00000001 /* Receiver Enable */
#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
#define HU 0x00000010 /* Hash Filter Unicast Address */
#define HM 0x00000020 /* Hash Filter Multicast Address */
#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
#define PR 0x00000080 /* Promiscuous Mode Enable */
#define IFE 0x00000100 /* Inverse Filtering Enable */
#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
#define PBF 0x00000400 /* Pass Bad Frames Enable */
#define PSF 0x00000800 /* Pass Short Frames Enable */
#define RAF 0x00001000 /* Receive-All Mode */
#define TE 0x00010000 /* Transmitter Enable */
#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
#define DC 0x00080000 /* Deferral Check */
#define BOLMT 0x00300000 /* Back-Off Limit */
#define BOLMT_10 0x00000000 /* 10-bit range */
#define BOLMT_8 0x00100000 /* 8-bit range */
#define BOLMT_4 0x00200000 /* 4-bit range */
#define BOLMT_1 0x00300000 /* 1-bit range */
#define DRTY 0x00400000 /* Disable TX Retry On Collision */
#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
#define RMII 0x01000000 /* RMII/MII* Mode */
#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
#define LB 0x08000000 /* Internal Loopback Enable */
#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
/* EMAC_STAADD Masks */
#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
#define STADISPRE 0x00000004 /* Disable Preamble Generation */
#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
#define REGAD 0x000007C0 /* STA Register Address */
#define PHYAD 0x0000F800 /* PHY Device Address */
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
/* EMAC_STADAT Mask */
#define STADATA 0x0000FFFF /* Station Management Data */
/* EMAC_FLC Masks */
#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
#define FLCE 0x00000002 /* Flow Control Enable */
#define PCF 0x00000004 /* Pass Control Frames */
#define BKPRSEN 0x00000008 /* Enable Backpressure */
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
/* EMAC_WKUP_CTL Masks */
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
#define MPKE 0x00000002 /* Magic Packet Enable */
#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
#define MPKS 0x00000020 /* Magic Packet Received Status */
#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
/* EMAC_WKUP_FFCMD Masks */
#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
/* EMAC_WKUP_FFOFF Masks */
#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
/* Set ALL Offsets */
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
/* EMAC_WKUP_FFCRC0 Masks */
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 0 Target CRC */
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 1 Target CRC */
/* EMAC_WKUP_FFCRC1 Masks */
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0) /* Set Wake-Up Filter 2 Target CRC */
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16) /* Set Wake-Up Filter 3 Target CRC */
/* EMAC_SYSCTL Masks */
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
/* EMAC_SYSTAT Masks */
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
#define RX_COMP 0x00001000 /* RX Frame Complete */
#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
#define RX_CRC 0x00010000 /* RX Frame CRC Error */
#define RX_LEN 0x00020000 /* RX Frame Length Error */
#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
#define RX_PHY 0x00200000 /* RX Frame PHY Error */
#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
#define TX_COMP 0x00000001 /* TX Frame Complete */
#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
/* EMAC_MMC_CTL Masks */
#define RSTC 0x00000001 /* Reset All Counters */
#define CROLL 0x00000002 /* Counter Roll-Over Enable */
#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
#define MMCE 0x00000008 /* Enable MMC Counter Operation */
/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
#endif /* _DEF_BF537_H */

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/*
* defBF537_extn.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
#ifndef _DEF_BF537_EXTN_H
#define _DEF_BF537_EXTN_H
#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
/* Delay inserted for PLL transition */
#define PLL_DELAY 0x1000
#define L1_ISRAM 0xFFA00000
#define L1_ISRAM_END 0xFFA10000
#define DATA_BANKA_SRAM 0xFF800000
#define DATA_BANKA_SRAM_END 0xFF808000
#define DATA_BANKB_SRAM 0xFF900000
#define DATA_BANKB_SRAM_END 0xFF908000
#define SYSMMR_BASE 0xFFC00000
#define WDSIZE16 0x00000004
/* Event Vector Table Address */
#define EVT_EMULATION_ADDR 0xffe02000
#define EVT_RESET_ADDR 0xffe02004
#define EVT_NMI_ADDR 0xffe02008
#define EVT_EXCEPTION_ADDR 0xffe0200c
#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
#define EVT_TIMER_ADDR 0xffe02018
#define EVT_IVG7_ADDR 0xffe0201c
#define EVT_IVG8_ADDR 0xffe02020
#define EVT_IVG9_ADDR 0xffe02024
#define EVT_IVG10_ADDR 0xffe02028
#define EVT_IVG11_ADDR 0xffe0202c
#define EVT_IVG12_ADDR 0xffe02030
#define EVT_IVG13_ADDR 0xffe02034
#define EVT_IVG14_ADDR 0xffe02038
#define EVT_IVG15_ADDR 0xffe0203c
#define EVT_OVERRIDE_ADDR 0xffe02100
/* IMASK Bit values */
#define IVG15_POS 0x00008000
#define IVG14_POS 0x00004000
#define IVG13_POS 0x00002000
#define IVG12_POS 0x00001000
#define IVG11_POS 0x00000800
#define IVG10_POS 0x00000400
#define IVG9_POS 0x00000200
#define IVG8_POS 0x00000100
#define IVG7_POS 0x00000080
#define IVGTMR_POS 0x00000040
#define IVGHW_POS 0x00000020
#define WDOG_TMR_DISABLE (0xAD << 4)
#define ICTL_RST 0x00000000
#define ICTL_NMI 0x00000002
#define ICTL_GP 0x00000004
#define ICTL_DISABLE 0x00000003
/* Watch Dog timer values setup */
#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE
#endif /* _DEF_BF537_EXTN_H */

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/*
* U-boot bf537_irq.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
* Changed by HuTao Apr18, 2003
*
* Copyright was missing when I got the code so took from MIPS arch ...MaTed---
* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
* Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
*
* Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
* Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
* Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
*
* Adapted for BlackFin BF537 by Bas Vermeulen <bas@buyways.nl>
* Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF537_IRQ_H_
#define _BF537_IRQ_H_
/*
* Interrupt source definitions
* Event Source Core Event Name Number
* EMU 0
* Reset RST 1
* NMI NMI 2
* Exception EVX 3
* Reserved -- 4
* Hardware Error IVHW 5
* Core Timer IVTMR 6
* PLL Wakeup Interrupt IVG7 7
* DMA Error (generic) IVG7 8
* PPI Error Interrupt IVG7 9
* SPORT0 Error Interrupt IVG7 10
* SPORT1 Error Interrupt IVG7 11
* SPI Error Interrupt IVG7 12
* UART Error Interrupt IVG7 13
* RTC Interrupt IVG8 14
* DMA0 Interrupt (PPI) IVG8 15
* DMA1 (SPORT0 RX) IVG9 16
* DMA2 (SPORT0 TX) IVG9 17
* DMA3 (SPORT1 RX) IVG9 18
* DMA4 (SPORT1 TX) IVG9 19
* DMA5 (PPI) IVG10 20
* DMA6 (UART RX) IVG10 21
* DMA7 (UART TX) IVG10 22
* Timer0 IVG11 23
* Timer1 IVG11 24
* Timer2 IVG11 25
* PF Interrupt A IVG12 26
* PF Interrupt B IVG12 27
* DMA8/9 Interrupt IVG13 28
* DMA10/11 Interrupt IVG13 29
* Watchdog Timer IVG13 30
* Software Interrupt 1 IVG14 31
* Software Interrupt 2 --
* (lowest priority) IVG15 32
*/
#define IRQ_EMU 0 /* Emulation */
#define IRQ_RST 1 /* reset */
#define IRQ_NMI 2 /* Non Maskable */
#define IRQ_EVX 3 /* Exception */
#define IRQ_UNUSED 4 /* - unused interrupt */
#define IRQ_HWERR 5 /* Hardware Error */
#define IRQ_CORETMR 6 /* Core timer */
#define IRQ_UART_RX_BIT 0x0800
#define IRQ_UART_TX_BIT 0x1000
#define IRQ_UART_ERROR_BIT 0x40
#endif

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include/asm-blackfin/arch-bf561/anomaly.h Normal file
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/*
* File: include/asm-blackfin/arch-bf561/anomaly.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
/*
* This file shoule be up to date with:
* - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* We do not support 0.1 or 0.4 silicon - sorry */
#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4))
#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4
#endif
/* Issues that are common to 0.5 and 0.3 silicon */
#if (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
slot1 and store of a P register in slot 2 is not
supported */
#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
updated at the same time. */
#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned
memory locations */
#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR
registers */
#define ANOMALY_05000127 /* Signbits instruction not functional under certain
conditions */
#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */
#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
upper bits */
#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
syncs */
#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz
and higher devices */
#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */
#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */
#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
functional */
#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
shadow of a conditional branch */
#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop
may cause bad instruction fetches */
#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
external SPORT TX and RX clocks */
#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */
#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal
voltage regulator (VDDint) to increase */
#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal
voltage regulator (VDDint) to decrease */
#define ANOMALY_05000272 /* Certain data cache write through modes fail for
VDDint <=0.9V */
#define ANOMALY_05000274 /* Data cache write back to external synchronous memory
may be lost */
#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */
#endif /* (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */
#if (defined(CONFIG_BF_REV_0_5))
#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
mode with external clock */
#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
using IMDMA */
#endif
#if (defined(CONFIG_BF_REV_0_3))
#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
Mode with 0 Frame Syncs */
#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
cache data writes */
#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
accumulator saturation */
#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
Purpose TX or RX modes */
#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
registers */
#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
External Frame Syncs */
#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
(not a meaningful mode) */
#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
Placement in Memory */
#define ANOMALY_05000189 /* False Protection Exception */
#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
when polarity setting is changed */
#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
corruption */
#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
memory read */
#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
fix */
#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
inactive channels in certain conditions */
#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
situation */
#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
allocate cache lines on reads only mode */
#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
stopping */
#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
instructions */
#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
state */
#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
Non-Cached On-Chip L2 Memory */
#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
data */
#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
Differences in certain Conditions */
#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
multichannel mode */
#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
hardware reset */
#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
Control causes failures */
#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
(TDM) mode in certain conditions */
#define ANOMALY_05000251 /* Exception not generated for MMR accesses in
reserved region */
#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
of the ICPLB Data registers differ */
#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
#define ANOMALY_05000262 /* Stores to data cache may be lost */
#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
exception */
#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
to last instruction in hardware loop */
#define ANOMALY_05000276 /* Timing requirements change for External Frame
Sync PPI Modes with non-zero PPI_DELAY */
#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
DMA system instability */
#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
not restored */
#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
in a particular stage */
#define ANOMALY_05000287 /* A read will receive incorrect data under certain
conditions */
#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
#endif
#endif /* _MACH_ANOMALY_H_ */

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/*
* U-boot bf561_serial.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF561_SERIAL_H_
#define _BF561_SERIAL_H_
#define BYTE_REF(addr) (*((volatile char*)addr))
#define HALFWORD_REF(addr) (*((volatile short*)addr))
#define WORD_REF(addr) (*((volatile long*)addr))
#define UART_THR_LO HALFWORD_REF(UART_THR)
#define UART_RBR_LO HALFWORD_REF(UART_RBR)
#define UART_DLL_LO HALFWORD_REF(UART_DLL)
#define UART_IER_LO HALFWORD_REF(UART_IER)
#define UART_IER_ERBFI 0x01
#define UART_IER_ETBEI 0x02
#define UART_IER_ELSI 0x04
#define UART_IER_EDDSI 0x08
#define UART_DLH_LO HALFWORD_REF(UART_DLH)
#define UART_IIR_LO HALFWORD_REF(UART_IIR)
#define UART_IIR_NOINT 0x01
#define UART_IIR_STATUS 0x06
#define UART_IIR_LSR 0x06
#define UART_IIR_RBR 0x04
#define UART_IIR_THR 0x02
#define UART_IIR_MSR 0x00
#define UART_LCR_LO HALFWORD_REF(UART_LCR)
#define UART_LCR_WLS5 0
#define UART_LCR_WLS6 0x01
#define UART_LCR_WLS7 0x02
#define UART_LCR_WLS8 0x03
#define UART_LCR_STB 0x04
#define UART_LCR_PEN 0x08
#define UART_LCR_EPS 0x10
#define UART_LCR_SP 0x20
#define UART_LCR_SB 0x40
#define UART_LCR_DLAB 0x80
#define UART_MCR_LO HALFWORD_REF(UART_MCR)
#define UART_LSR_LO HALFWORD_REF(UART_LSR)
#define UART_LSR_DR 0x01
#define UART_LSR_OE 0x02
#define UART_LSR_PE 0x04
#define UART_LSR_FE 0x08
#define UART_LSR_BI 0x10
#define UART_LSR_THRE 0x20
#define UART_LSR_TEMT 0x40
#define UART_MSR_LO HALFWORD_REF(UART_MSR)
#define UART_SCR_LO HALFWORD_REF(UART_SCR)
#define UART_GCTL_LO HALFWORD_REF(UART_GCTL)
#define UART_GCTL_UCEN 0x01
#endif

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include/asm-blackfin/arch-bf561/cdefBF561.h Normal file
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/*
* cdefBF561.h
*
* (c) Copyright 2001-2004 Analog Devices, Inc. All rights reserved.
*
*/
/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
#ifndef _CDEF_BF561_H
#define _CDEF_BF561_H
/*
* #if !defined(__ADSPBF561__)
* #warning cdefBF561.h should only be included for BF561 chip.
* #endif
*/
/* include all Core registers and bit definitions */
#include <asm/arch-bf561/defBF561.h>
#include <asm/arch-common/cdef_LPBlackfin.h>
/*
* System MMR Register Map
*/
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define pPLL_CTL (volatile unsigned short *)PLL_CTL
#define pPLL_DIV (volatile unsigned short *)PLL_DIV
#define pVR_CTL (volatile unsigned short *)VR_CTL
#define pPLL_STAT (volatile unsigned short *)PLL_STAT
#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT
/*
* System Reset and Interrupt Controller registers for
* core A (0xFFC0 0100-0xFFC0 01FF)
*/
#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST
#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR
#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT
#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK
#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0
#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1
#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0
#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1
#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2
#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3
#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4
#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5
#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6
#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7
#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0
#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1
#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0
#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1
/*
* System Reset and Interrupt Controller registers for
* Core B (0xFFC0 1100-0xFFC0 11FF)
*/
#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST
#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR
#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT
#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0
#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1
#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0
#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1
#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2
#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3
#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4
#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5
#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6
#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7
#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0
#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1
#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0
#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1
/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL
#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT
#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT
/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL
#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT
#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT
/* UART Controller (0xFFC00400 - 0xFFC004FF) */
#define pUART_THR (volatile unsigned short *)UART_THR
#define pUART_RBR (volatile unsigned short *)UART_RBR
#define pUART_DLL (volatile unsigned short *)UART_DLL
#define pUART_IER (volatile unsigned short *)UART_IER
#define pUART_DLH (volatile unsigned short *)UART_DLH
#define pUART_IIR (volatile unsigned short *)UART_IIR
#define pUART_LCR (volatile unsigned short *)UART_LCR
#define pUART_MCR (volatile unsigned short *)UART_MCR
#define pUART_LSR (volatile unsigned short *)UART_LSR
#define pUART_MSR (volatile unsigned short *)UART_MSR
#define pUART_SCR (volatile unsigned short *)UART_SCR
#define pUART_GCTL (volatile unsigned short *)UART_GCTL
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define pSPI_CTL (volatile unsigned short *)SPI_CTL
#define pSPI_FLG (volatile unsigned short *)SPI_FLG
#define pSPI_STAT (volatile unsigned short *)SPI_STAT
#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR
#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR
#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD
#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW
/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG
#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER
#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD
#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH
#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG
#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER
#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD
#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH
#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG
#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER
#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD
#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH
#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG
#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER
#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD
#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH
#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG
#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER
#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD
#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH
#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG
#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER
#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD
#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH
#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG
#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER
#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD
#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH
#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG
#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER
#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD
#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH
/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE
#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE
#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS
#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG
#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER
#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD
#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH
#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG
#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER
#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD
#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH
#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG
#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER
#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD
#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH
#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG
#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER
#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD
#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH
#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE
#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE
#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS
/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D
#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C
#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S
#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T
#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D
#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C
#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S
#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T
#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D
#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C
#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S
#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T
#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR
#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR
#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE
#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH
#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN
/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D
#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C
#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S
#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T
#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D
#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C
#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S
#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T
#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D
#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C
#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S
#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T
#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR
#define pFIO1_POLAR (volatile unsigned short *)FIO1_POLAR
#define pFIO1_EDGE (volatile unsigned short *)FIO1_EDGE
#define pFIO1_BOTH (volatile unsigned short *)FIO1_BOTH
#define pFIO1_INEN (volatile unsigned short *)FIO1_INEN
/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
#define pFIO2_FLAG_D (volatile unsigned short *)FIO2_FLAG_D
#define pFIO2_FLAG_C (volatile unsigned short *)FIO2_FLAG_C
#define pFIO2_FLAG_S (volatile unsigned short *)FIO2_FLAG_S
#define pFIO2_FLAG_T (volatile unsigned short *)FIO2_FLAG_T
#define pFIO2_MASKA_D (volatile unsigned short *)FIO2_MASKA_D
#define pFIO2_MASKA_C (volatile unsigned short *)FIO2_MASKA_C
#define pFIO2_MASKA_S (volatile unsigned short *)FIO2_MASKA_S
#define pFIO2_MASKA_T (volatile unsigned short *)FIO2_MASKA_T
#define pFIO2_MASKB_D (volatile unsigned short *)FIO2_MASKB_D
#define pFIO2_MASKB_C (volatile unsigned short *)FIO2_MASKB_C
#define pFIO2_MASKB_S (volatile unsigned short *)FIO2_MASKB_S
#define pFIO2_MASKB_T (volatile unsigned short *)FIO2_MASKB_T
#define pFIO2_DIR (volatile unsigned short *)FIO2_DIR
#define pFIO2_POLAR (volatile unsigned short *)FIO2_POLAR
#define pFIO2_EDGE (volatile unsigned short *)FIO2_EDGE
#define pFIO2_BOTH (volatile unsigned short *)FIO2_BOTH
#define pFIO2_INEN (volatile unsigned short *)FIO2_INEN
/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
#define pSPORT0_TCR1 (volatile unsigned short *)SPORT0_TCR1
#define pSPORT0_TCR2 (volatile unsigned short *)SPORT0_TCR2
#define pSPORT0_TCLKDIV (volatile unsigned short *)SPORT0_TCLKDIV
#define pSPORT0_TFSDIV (volatile unsigned short *)SPORT0_TFSDIV
#define pSPORT0_TX (volatile unsigned long *)SPORT0_TX
#define pSPORT0_RX (volatile unsigned long *)SPORT0_RX
#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
#define pSPORT0_RCR1 (volatile unsigned short *)SPORT0_RCR1
#define pSPORT0_RCR2 (volatile unsigned short *)SPORT0_RCR2
#define pSPORT0_RCLKDIV (volatile unsigned short *)SPORT0_RCLKDIV
#define pSPORT0_RFSDIV (volatile unsigned short *)SPORT0_RFSDIV
#define pSPORT0_STAT (volatile unsigned short *)SPORT0_STAT
#define pSPORT0_CHNL (volatile unsigned short *)SPORT0_CHNL
#define pSPORT0_MCMC1 (volatile unsigned short *)SPORT0_MCMC1
#define pSPORT0_MCMC2 (volatile unsigned short *)SPORT0_MCMC2
#define pSPORT0_MTCS0 (volatile unsigned long *)SPORT0_MTCS0
#define pSPORT0_MTCS1 (volatile unsigned long *)SPORT0_MTCS1
#define pSPORT0_MTCS2 (volatile unsigned long *)SPORT0_MTCS2
#define pSPORT0_MTCS3 (volatile unsigned long *)SPORT0_MTCS3
#define pSPORT0_MRCS0 (volatile unsigned long *)SPORT0_MRCS0
#define pSPORT0_MRCS1 (volatile unsigned long *)SPORT0_MRCS1
#define pSPORT0_MRCS2 (volatile unsigned long *)SPORT0_MRCS2
#define pSPORT0_MRCS3 (volatile unsigned long *)SPORT0_MRCS3
/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
#define pSPORT1_TCR1 (volatile unsigned short *)SPORT1_TCR1
#define pSPORT1_TCR2 (volatile unsigned short *)SPORT1_TCR2
#define pSPORT1_TCLKDIV (volatile unsigned short *)SPORT1_TCLKDIV
#define pSPORT1_TFSDIV (volatile unsigned short *)SPORT1_TFSDIV
#define pSPORT1_TX (volatile unsigned long *)SPORT1_TX
#define pSPORT1_RX (volatile unsigned long *)SPORT1_RX
#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
#define pSPORT1_RCR1 (volatile unsigned short *)SPORT1_RCR1
#define pSPORT1_RCR2 (volatile unsigned short *)SPORT1_RCR2
#define pSPORT1_RCLKDIV (volatile unsigned short *)SPORT1_RCLKDIV
#define pSPORT1_RFSDIV (volatile unsigned short *)SPORT1_RFSDIV
#define pSPORT1_STAT (volatile unsigned short *)SPORT1_STAT
#define pSPORT1_CHNL (volatile unsigned short *)SPORT1_CHNL
#define pSPORT1_MCMC1 (volatile unsigned short *)SPORT1_MCMC1
#define pSPORT1_MCMC2 (volatile unsigned short *)SPORT1_MCMC2
#define pSPORT1_MTCS0 (volatile unsigned long *)SPORT1_MTCS0
#define pSPORT1_MTCS1 (volatile unsigned long *)SPORT1_MTCS1
#define pSPORT1_MTCS2 (volatile unsigned long *)SPORT1_MTCS2
#define pSPORT1_MTCS3 (volatile unsigned long *)SPORT1_MTCS3
#define pSPORT1_MRCS0 (volatile unsigned long *)SPORT1_MRCS0
#define pSPORT1_MRCS1 (volatile unsigned long *)SPORT1_MRCS1
#define pSPORT1_MRCS2 (volatile unsigned long *)SPORT1_MRCS2
#define pSPORT1_MRCS3 (volatile unsigned long *)SPORT1_MRCS3
/* Asynchronous Memory Controller - External Bus Interface Unit */
#define pEBIU_AMGCTL (volatile unsigned short *)EBIU_AMGCTL
#define pEBIU_AMBCTL0 (volatile unsigned long *)EBIU_AMBCTL0
#define pEBIU_AMBCTL1 (volatile unsigned long *)EBIU_AMBCTL1
/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
#define pEBIU_SDGCTL (volatile unsigned long *)EBIU_SDGCTL
#define pEBIU_SDBCTL (volatile unsigned long *)EBIU_SDBCTL
#define pEBIU_SDRRC (volatile unsigned short *)EBIU_SDRRC
#define pEBIU_SDSTAT (volatile unsigned short *)EBIU_SDSTAT
/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/
#define pPPI0_CONTROL (volatile unsigned short *)PPI0_CONTROL
#define pPPI0_STATUS (volatile unsigned short *)PPI0_STATUS
#define pPPI0_COUNT (volatile unsigned short *)PPI0_COUNT
#define pPPI0_DELAY (volatile unsigned short *)PPI0_DELAY
#define pPPI0_FRAME (volatile unsigned short *)PPI0_FRAME
/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF)*/
#define pPPI1_CONTROL (volatile unsigned short *)PPI1_CONTROL
#define pPPI1_STATUS (volatile unsigned short *)PPI1_STATUS
#define pPPI1_COUNT (volatile unsigned short *)PPI1_COUNT
#define pPPI1_DELAY (volatile unsigned short *)PPI1_DELAY
#define pPPI1_FRAME (volatile unsigned short *)PPI1_FRAME
/*DMA Traffic controls*/
#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER)
#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT)
/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
#define pDMA1_0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG
#define pDMA1_0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR
#define pDMA1_0_START_ADDR (volatile void **)DMA1_0_START_ADDR
#define pDMA1_0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT
#define pDMA1_0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT
#define pDMA1_0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY
#define pDMA1_0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY
#define pDMA1_0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR
#define pDMA1_0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR
#define pDMA1_0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT
#define pDMA1_0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT
#define pDMA1_0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS
#define pDMA1_0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
#define pDMA1_1_CONFIG (volatile unsigned short *)DMA1_1_CONFIG
#define pDMA1_1_NEXT_DESC_PTR (volatile void **)DMA1_1_NEXT_DESC_PTR
#define pDMA1_1_START_ADDR (volatile void **)DMA1_1_START_ADDR
#define pDMA1_1_X_COUNT (volatile unsigned short *)DMA1_1_X_COUNT
#define pDMA1_1_Y_COUNT (volatile unsigned short *)DMA1_1_Y_COUNT
#define pDMA1_1_X_MODIFY (volatile unsigned short *)DMA1_1_X_MODIFY
#define pDMA1_1_Y_MODIFY (volatile unsigned short *)DMA1_1_Y_MODIFY
#define pDMA1_1_CURR_DESC_PTR (volatile void **)DMA1_1_CURR_DESC_PTR
#define pDMA1_1_CURR_ADDR (volatile void **)DMA1_1_CURR_ADDR
#define pDMA1_1_CURR_X_COUNT (volatile unsigned short *)DMA1_1_CURR_X_COUNT
#define pDMA1_1_CURR_Y_COUNT (volatile unsigned short *)DMA1_1_CURR_Y_COUNT
#define pDMA1_1_IRQ_STATUS (volatile unsigned short *)DMA1_1_IRQ_STATUS
#define pDMA1_1_PERIPHERAL_MAP (volatile unsigned short *)DMA1_1_PERIPHERAL_MAP
#define pDMA1_2_CONFIG (volatile unsigned short *)DMA1_2_CONFIG
#define pDMA1_2_NEXT_DESC_PTR (volatile void **)DMA1_2_NEXT_DESC_PTR
#define pDMA1_2_START_ADDR (volatile void **)DMA1_2_START_ADDR
#define pDMA1_2_X_COUNT (volatile unsigned short *)DMA1_2_X_COUNT
#define pDMA1_2_Y_COUNT (volatile unsigned short *)DMA1_2_Y_COUNT
#define pDMA1_2_X_MODIFY (volatile unsigned short *)DMA1_2_X_MODIFY
#define pDMA1_2_Y_MODIFY (volatile unsigned short *)DMA1_2_Y_MODIFY
#define pDMA1_2_CURR_DESC_PTR (volatile void **)DMA1_2_CURR_DESC_PTR
#define pDMA1_2_CURR_ADDR (volatile void **)DMA1_2_CURR_ADDR
#define pDMA1_2_CURR_X_COUNT (volatile unsigned short *)DMA1_2_CURR_X_COUNT
#define pDMA1_2_CURR_Y_COUNT (volatile unsigned short *)DMA1_2_CURR_Y_COUNT
#define pDMA1_2_IRQ_STATUS (volatile unsigned short *)DMA1_2_IRQ_STATUS
#define pDMA1_2_PERIPHERAL_MAP (volatile unsigned short *)DMA1_2_PERIPHERAL_MAP
#define pDMA1_3_CONFIG (volatile unsigned short *)DMA1_3_CONFIG
#define pDMA1_3_NEXT_DESC_PTR (volatile void **)DMA1_3_NEXT_DESC_PTR
#define pDMA1_3_START_ADDR (volatile void **)DMA1_3_START_ADDR
#define pDMA1_3_X_COUNT (volatile unsigned short *)DMA1_3_X_COUNT
#define pDMA1_3_Y_COUNT (volatile unsigned short *)DMA1_3_Y_COUNT
#define pDMA1_3_X_MODIFY (volatile unsigned short *)DMA1_3_X_MODIFY
#define pDMA1_3_Y_MODIFY (volatile unsigned short *)DMA1_3_Y_MODIFY
#define pDMA1_3_CURR_DESC_PTR (volatile void **)DMA1_3_CURR_DESC_PTR
#define pDMA1_3_CURR_ADDR (volatile void **)DMA1_3_CURR_ADDR
#define pDMA1_3_CURR_X_COUNT (volatile unsigned short *)DMA1_3_CURR_X_COUNT
#define pDMA1_3_CURR_Y_COUNT (volatile unsigned short *)DMA1_3_CURR_Y_COUNT
#define pDMA1_3_IRQ_STATUS (volatile unsigned short *)DMA1_3_IRQ_STATUS
#define pDMA1_3_PERIPHERAL_MAP (volatile unsigned short *)DMA1_3_PERIPHERAL_MAP
#define pDMA1_4_CONFIG (volatile unsigned short *)DMA1_4_CONFIG
#define pDMA1_4_NEXT_DESC_PTR (volatile void **)DMA1_4_NEXT_DESC_PTR
#define pDMA1_4_START_ADDR (volatile void **)DMA1_4_START_ADDR
#define pDMA1_4_X_COUNT (volatile unsigned short *)DMA1_4_X_COUNT
#define pDMA1_4_Y_COUNT (volatile unsigned short *)DMA1_4_Y_COUNT
#define pDMA1_4_X_MODIFY (volatile unsigned short *)DMA1_4_X_MODIFY
#define pDMA1_4_Y_MODIFY (volatile unsigned short *)DMA1_4_Y_MODIFY
#define pDMA1_4_CURR_DESC_PTR (volatile void **)DMA1_4_CURR_DESC_PTR
#define pDMA1_4_CURR_ADDR (volatile void **)DMA1_4_CURR_ADDR
#define pDMA1_4_CURR_X_COUNT (volatile unsigned short *)DMA1_4_CURR_X_COUNT
#define pDMA1_4_CURR_Y_COUNT (volatile unsigned short *)DMA1_4_CURR_Y_COUNT
#define pDMA1_4_IRQ_STATUS (volatile unsigned short *)DMA1_4_IRQ_STATUS
#define pDMA1_4_PERIPHERAL_MAP (volatile unsigned short *)DMA1_4_PERIPHERAL_MAP
#define pDMA1_5_CONFIG (volatile unsigned short *)DMA1_5_CONFIG
#define pDMA1_5_NEXT_DESC_PTR (volatile void **)DMA1_5_NEXT_DESC_PTR
#define pDMA1_5_START_ADDR (volatile void **)DMA1_5_START_ADDR
#define pDMA1_5_X_COUNT (volatile unsigned short *)DMA1_5_X_COUNT
#define pDMA1_5_Y_COUNT (volatile unsigned short *)DMA1_5_Y_COUNT
#define pDMA1_5_X_MODIFY (volatile unsigned short *)DMA1_5_X_MODIFY
#define pDMA1_5_Y_MODIFY (volatile unsigned short *)DMA1_5_Y_MODIFY
#define pDMA1_5_CURR_DESC_PTR (volatile void **)DMA1_5_CURR_DESC_PTR
#define pDMA1_5_CURR_ADDR (volatile void **)DMA1_5_CURR_ADDR
#define pDMA1_5_CURR_X_COUNT (volatile unsigned short *)DMA1_5_CURR_X_COUNT
#define pDMA1_5_CURR_Y_COUNT (volatile unsigned short *)DMA1_5_CURR_Y_COUNT
#define pDMA1_5_IRQ_STATUS (volatile unsigned short *)DMA1_5_IRQ_STATUS
#define pDMA1_5_PERIPHERAL_MAP (volatile unsigned short *)DMA1_5_PERIPHERAL_MAP
#define pDMA1_6_CONFIG (volatile unsigned short *)DMA1_6_CONFIG
#define pDMA1_6_NEXT_DESC_PTR (volatile void **)DMA1_6_NEXT_DESC_PTR
#define pDMA1_6_START_ADDR (volatile void **)DMA1_6_START_ADDR
#define pDMA1_6_X_COUNT (volatile unsigned short *)DMA1_6_X_COUNT
#define pDMA1_6_Y_COUNT (volatile unsigned short *)DMA1_6_Y_COUNT
#define pDMA1_6_X_MODIFY (volatile unsigned short *)DMA1_6_X_MODIFY
#define pDMA1_6_Y_MODIFY (volatile unsigned short *)DMA1_6_Y_MODIFY
#define pDMA1_6_CURR_DESC_PTR (volatile void **)DMA1_6_CURR_DESC_PTR
#define pDMA1_6_CURR_ADDR (volatile void **)DMA1_6_CURR_ADDR
#define pDMA1_6_CURR_X_COUNT (volatile unsigned short *)DMA1_6_CURR_X_COUNT
#define pDMA1_6_CURR_Y_COUNT (volatile unsigned short *)DMA1_6_CURR_Y_COUNT
#define pDMA1_6_IRQ_STATUS (volatile unsigned short *)DMA1_6_IRQ_STATUS
#define pDMA1_6_PERIPHERAL_MAP (volatile unsigned short *)DMA1_6_PERIPHERAL_MAP
#define pDMA1_7_CONFIG (volatile unsigned short *)DMA1_7_CONFIG
#define pDMA1_7_NEXT_DESC_PTR (volatile void **)DMA1_7_NEXT_DESC_PTR
#define pDMA1_7_START_ADDR (volatile void **)DMA1_7_START_ADDR
#define pDMA1_7_X_COUNT (volatile unsigned short *)DMA1_7_X_COUNT
#define pDMA1_7_Y_COUNT (volatile unsigned short *)DMA1_7_Y_COUNT
#define pDMA1_7_X_MODIFY (volatile unsigned short *)DMA1_7_X_MODIFY
#define pDMA1_7_Y_MODIFY (volatile unsigned short *)DMA1_7_Y_MODIFY
#define pDMA1_7_CURR_DESC_PTR (volatile void **)DMA1_7_CURR_DESC_PTR
#define pDMA1_7_CURR_ADDR (volatile void **)DMA1_7_CURR_ADDR
#define pDMA1_7_CURR_X_COUNT (volatile unsigned short *)DMA1_7_CURR_X_COUNT
#define pDMA1_7_CURR_Y_COUNT (volatile unsigned short *)DMA1_7_CURR_Y_COUNT
#define pDMA1_7_IRQ_STATUS (volatile unsigned short *)DMA1_7_IRQ_STATUS
#define pDMA1_7_PERIPHERAL_MAP (volatile unsigned short *)DMA1_7_PERIPHERAL_MAP
#define pDMA1_8_CONFIG (volatile unsigned short *)DMA1_8_CONFIG
#define pDMA1_8_NEXT_DESC_PTR (volatile void **)DMA1_8_NEXT_DESC_PTR
#define pDMA1_8_START_ADDR (volatile void **)DMA1_8_START_ADDR
#define pDMA1_8_X_COUNT (volatile unsigned short *)DMA1_8_X_COUNT
#define pDMA1_8_Y_COUNT (volatile unsigned short *)DMA1_8_Y_COUNT
#define pDMA1_8_X_MODIFY (volatile unsigned short *)DMA1_8_X_MODIFY
#define pDMA1_8_Y_MODIFY (volatile unsigned short *)DMA1_8_Y_MODIFY
#define pDMA1_8_CURR_DESC_PTR (volatile void **)DMA1_8_CURR_DESC_PTR
#define pDMA1_8_CURR_ADDR (volatile void **)DMA1_8_CURR_ADDR
#define pDMA1_8_CURR_X_COUNT (volatile unsigned short *)DMA1_8_CURR_X_COUNT
#define pDMA1_8_CURR_Y_COUNT (volatile unsigned short *)DMA1_8_CURR_Y_COUNT
#define pDMA1_8_IRQ_STATUS (volatile unsigned short *)DMA1_8_IRQ_STATUS
#define pDMA1_8_PERIPHERAL_MAP (volatile unsigned short *)DMA1_8_PERIPHERAL_MAP
#define pDMA1_9_CONFIG (volatile unsigned short *)DMA1_9_CONFIG
#define pDMA1_9_NEXT_DESC_PTR (volatile void **)DMA1_9_NEXT_DESC_PTR
#define pDMA1_9_START_ADDR (volatile void **)DMA1_9_START_ADDR
#define pDMA1_9_X_COUNT (volatile unsigned short *)DMA1_9_X_COUNT
#define pDMA1_9_Y_COUNT (volatile unsigned short *)DMA1_9_Y_COUNT
#define pDMA1_9_X_MODIFY (volatile unsigned short *)DMA1_9_X_MODIFY
#define pDMA1_9_Y_MODIFY (volatile unsigned short *)DMA1_9_Y_MODIFY
#define pDMA1_9_CURR_DESC_PTR (volatile void **)DMA1_9_CURR_DESC_PTR
#define pDMA1_9_CURR_ADDR (volatile void **)DMA1_9_CURR_ADDR
#define pDMA1_9_CURR_X_COUNT (volatile unsigned short *)DMA1_9_CURR_X_COUNT
#define pDMA1_9_CURR_Y_COUNT (volatile unsigned short *)DMA1_9_CURR_Y_COUNT
#define pDMA1_9_IRQ_STATUS (volatile unsigned short *)DMA1_9_IRQ_STATUS
#define pDMA1_9_PERIPHERAL_MAP (volatile unsigned short *)DMA1_9_PERIPHERAL_MAP
#define pDMA1_10_CONFIG (volatile unsigned short *)DMA1_10_CONFIG
#define pDMA1_10_NEXT_DESC_PTR (volatile void **)DMA1_10_NEXT_DESC_PTR
#define pDMA1_10_START_ADDR (volatile void **)DMA1_10_START_ADDR
#define pDMA1_10_X_COUNT (volatile unsigned short *)DMA1_10_X_COUNT
#define pDMA1_10_Y_COUNT (volatile unsigned short *)DMA1_10_Y_COUNT
#define pDMA1_10_X_MODIFY (volatile unsigned short *)DMA1_10_X_MODIFY
#define pDMA1_10_Y_MODIFY (volatile unsigned short *)DMA1_10_Y_MODIFY
#define pDMA1_10_CURR_DESC_PTR (volatile void **)DMA1_10_CURR_DESC_PTR
#define pDMA1_10_CURR_ADDR (volatile void **)DMA1_10_CURR_ADDR
#define pDMA1_10_CURR_X_COUNT (volatile unsigned short *)DMA1_10_CURR_X_COUNT
#define pDMA1_10_CURR_Y_COUNT (volatile unsigned short *)DMA1_10_CURR_Y_COUNT
#define pDMA1_10_IRQ_STATUS (volatile unsigned short *)DMA1_10_IRQ_STATUS
#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP
#define pDMA1_11_CONFIG (volatile unsigned short *)DMA1_11_CONFIG
#define pDMA1_11_NEXT_DESC_PTR (volatile void **)DMA1_11_NEXT_DESC_PTR
#define pDMA1_11_START_ADDR (volatile void **)DMA1_11_START_ADDR
#define pDMA1_11_X_COUNT (volatile unsigned short *)DMA1_11_X_COUNT
#define pDMA1_11_Y_COUNT (volatile unsigned short *)DMA1_11_Y_COUNT
#define pDMA1_11_X_MODIFY (volatile signed short *)DMA1_11_X_MODIFY
#define pDMA1_11_Y_MODIFY (volatile signed short *)DMA1_11_Y_MODIFY
#define pDMA1_11_CURR_DESC_PTR (volatile void **)DMA1_11_CURR_DESC_PTR
#define pDMA1_11_CURR_ADDR (volatile void **)DMA1_11_CURR_ADDR
#define pDMA1_11_CURR_X_COUNT (volatile unsigned short *)DMA1_11_CURR_X_COUNT
#define pDMA1_11_CURR_Y_COUNT (volatile unsigned short *)DMA1_11_CURR_Y_COUNT
#define pDMA1_11_IRQ_STATUS (volatile unsigned short *)DMA1_11_IRQ_STATUS
#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP
/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF)*/
#define pMDMA1_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG
#define pMDMA1_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR
#define pMDMA1_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR
#define pMDMA1_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT
#define pMDMA1_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT
#define pMDMA1_D0_X_MODIFY (volatile signed short *)MDMA1_D0_X_MODIFY
#define pMDMA1_D0_Y_MODIFY (volatile signed short *)MDMA1_D0_Y_MODIFY
#define pMDMA1_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR
#define pMDMA1_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR
#define pMDMA1_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
#define pMDMA1_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
#define pMDMA1_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS
#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
#define pMDMA1_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG
#define pMDMA1_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR
#define pMDMA1_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR
#define pMDMA1_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT
#define pMDMA1_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT
#define pMDMA1_S0_X_MODIFY (volatile signed short *)MDMA1_S0_X_MODIFY
#define pMDMA1_S0_Y_MODIFY (volatile signed short *)MDMA1_S0_Y_MODIFY
#define pMDMA1_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR
#define pMDMA1_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR
#define pMDMA1_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
#define pMDMA1_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
#define pMDMA1_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS
#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
#define pMDMA1_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG
#define pMDMA1_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR
#define pMDMA1_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR
#define pMDMA1_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT
#define pMDMA1_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT
#define pMDMA1_D1_X_MODIFY (volatile signed short *)MDMA1_D1_X_MODIFY
#define pMDMA1_D1_Y_MODIFY (volatile signed short *)MDMA1_D1_Y_MODIFY
#define pMDMA1_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR
#define pMDMA1_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR
#define pMDMA1_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
#define pMDMA1_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
#define pMDMA1_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS
#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
#define pMDMA1_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG
#define pMDMA1_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR
#define pMDMA1_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR
#define pMDMA1_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT
#define pMDMA1_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT
#define pMDMA1_S1_X_MODIFY (volatile signed short *)MDMA1_S1_X_MODIFY
#define pMDMA1_S1_Y_MODIFY (volatile signed short *)MDMA1_S1_Y_MODIFY
#define pMDMA1_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR
#define pMDMA1_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR
#define pMDMA1_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
#define pMDMA1_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
#define pMDMA1_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS
#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
#define pDMA2_0_CONFIG (volatile unsigned short *)DMA2_0_CONFIG
#define pDMA2_0_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR
#define pDMA2_0_START_ADDR (volatile void **)DMA2_0_START_ADDR
#define pDMA2_0_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT
#define pDMA2_0_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT
#define pDMA2_0_X_MODIFY (volatile signed short *)DMA2_0_X_MODIFY
#define pDMA2_0_Y_MODIFY (volatile signed short *)DMA2_0_Y_MODIFY
#define pDMA2_0_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR
#define pDMA2_0_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR
#define pDMA2_0_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT
#define pDMA2_0_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT
#define pDMA2_0_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS
#define pDMA2_0_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
#define pDMA2_1_CONFIG (volatile unsigned short *)DMA2_1_CONFIG
#define pDMA2_1_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR
#define pDMA2_1_START_ADDR (volatile void **)DMA2_1_START_ADDR
#define pDMA2_1_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT
#define pDMA2_1_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT
#define pDMA2_1_X_MODIFY (volatile signed short *)DMA2_1_X_MODIFY
#define pDMA2_1_Y_MODIFY (volatile signed short *)DMA2_1_Y_MODIFY
#define pDMA2_1_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR
#define pDMA2_1_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR
#define pDMA2_1_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT
#define pDMA2_1_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT
#define pDMA2_1_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS
#define pDMA2_1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
#define pDMA2_2_CONFIG (volatile unsigned short *)DMA2_2_CONFIG
#define pDMA2_2_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR
#define pDMA2_2_START_ADDR (volatile void **)DMA2_2_START_ADDR
#define pDMA2_2_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT
#define pDMA2_2_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT
#define pDMA2_2_X_MODIFY (volatile signed short *)DMA2_2_X_MODIFY
#define pDMA2_2_Y_MODIFY (volatile signed short *)DMA2_2_Y_MODIFY
#define pDMA2_2_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR
#define pDMA2_2_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR
#define pDMA2_2_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT
#define pDMA2_2_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT
#define pDMA2_2_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS
#define pDMA2_2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
#define pDMA2_3_CONFIG (volatile unsigned short *)DMA2_3_CONFIG
#define pDMA2_3_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR
#define pDMA2_3_START_ADDR (volatile void **)DMA2_3_START_ADDR
#define pDMA2_3_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT
#define pDMA2_3_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT
#define pDMA2_3_X_MODIFY (volatile signed short *)DMA2_3_X_MODIFY
#define pDMA2_3_Y_MODIFY (volatile signed short *)DMA2_3_Y_MODIFY
#define pDMA2_3_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR
#define pDMA2_3_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR
#define pDMA2_3_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT
#define pDMA2_3_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT
#define pDMA2_3_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS
#define pDMA2_3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
#define pDMA2_4_CONFIG (volatile unsigned short *)DMA2_4_CONFIG
#define pDMA2_4_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR
#define pDMA2_4_START_ADDR (volatile void **)DMA2_4_START_ADDR
#define pDMA2_4_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT
#define pDMA2_4_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT
#define pDMA2_4_X_MODIFY (volatile signed short *)DMA2_4_X_MODIFY
#define pDMA2_4_Y_MODIFY (volatile signed short *)DMA2_4_Y_MODIFY
#define pDMA2_4_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR
#define pDMA2_4_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR
#define pDMA2_4_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT
#define pDMA2_4_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT
#define pDMA2_4_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS
#define pDMA2_4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
#define pDMA2_5_CONFIG (volatile unsigned short *)DMA2_5_CONFIG
#define pDMA2_5_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR
#define pDMA2_5_START_ADDR (volatile void **)DMA2_5_START_ADDR
#define pDMA2_5_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT
#define pDMA2_5_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT
#define pDMA2_5_X_MODIFY (volatile signed short *)DMA2_5_X_MODIFY
#define pDMA2_5_Y_MODIFY (volatile signed short *)DMA2_5_Y_MODIFY
#define pDMA2_5_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR
#define pDMA2_5_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR
#define pDMA2_5_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT
#define pDMA2_5_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT
#define pDMA2_5_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS
#define pDMA2_5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
#define pDMA2_6_CONFIG (volatile unsigned short *)DMA2_6_CONFIG
#define pDMA2_6_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR
#define pDMA2_6_START_ADDR (volatile void **)DMA2_6_START_ADDR
#define pDMA2_6_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT
#define pDMA2_6_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT
#define pDMA2_6_X_MODIFY (volatile signed short *)DMA2_6_X_MODIFY
#define pDMA2_6_Y_MODIFY (volatile signed short *)DMA2_6_Y_MODIFY
#define pDMA2_6_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR
#define pDMA2_6_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR
#define pDMA2_6_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT
#define pDMA2_6_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT
#define pDMA2_6_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS
#define pDMA2_6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
#define pDMA2_7_CONFIG (volatile unsigned short *)DMA2_7_CONFIG
#define pDMA2_7_NEXT_DESC_PTR (volatile void **)DMA2_7_NEXT_DESC_PTR
#define pDMA2_7_START_ADDR (volatile void **)DMA2_7_START_ADDR
#define pDMA2_7_X_COUNT (volatile unsigned short *)DMA2_7_X_COUNT
#define pDMA2_7_Y_COUNT (volatile unsigned short *)DMA2_7_Y_COUNT
#define pDMA2_7_X_MODIFY (volatile signed short *)DMA2_7_X_MODIFY
#define pDMA2_7_Y_MODIFY (volatile signed short *)DMA2_7_Y_MODIFY
#define pDMA2_7_CURR_DESC_PTR (volatile void **)DMA2_7_CURR_DESC_PTR
#define pDMA2_7_CURR_ADDR (volatile void **)DMA2_7_CURR_ADDR
#define pDMA2_7_CURR_X_COUNT (volatile unsigned short *)DMA2_7_CURR_X_COUNT
#define pDMA2_7_CURR_Y_COUNT (volatile unsigned short *)DMA2_7_CURR_Y_COUNT
#define pDMA2_7_IRQ_STATUS (volatile unsigned short *)DMA2_7_IRQ_STATUS
#define pDMA2_7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_7_PERIPHERAL_MAP
#define pDMA2_8_CONFIG (volatile unsigned short *)DMA2_8_CONFIG
#define pDMA2_8_NEXT_DESC_PTR (volatile void **)DMA2_8_NEXT_DESC_PTR
#define pDMA2_8_START_ADDR (volatile void **)DMA2_8_START_ADDR
#define pDMA2_8_X_COUNT (volatile unsigned short *)DMA2_8_X_COUNT
#define pDMA2_8_Y_COUNT (volatile unsigned short *)DMA2_8_Y_COUNT
#define pDMA2_8_X_MODIFY (volatile signed short *)DMA2_8_X_MODIFY
#define pDMA2_8_Y_MODIFY (volatile signed short *)DMA2_8_Y_MODIFY
#define pDMA2_8_CURR_DESC_PTR (volatile void **)DMA2_8_CURR_DESC_PTR
#define pDMA2_8_CURR_ADDR (volatile void **)DMA2_8_CURR_ADDR
#define pDMA2_8_CURR_X_COUNT (volatile unsigned short *)DMA2_8_CURR_X_COUNT
#define pDMA2_8_CURR_Y_COUNT (volatile unsigned short *)DMA2_8_CURR_Y_COUNT
#define pDMA2_8_IRQ_STATUS (volatile unsigned short *)DMA2_8_IRQ_STATUS
#define pDMA2_8_PERIPHERAL_MAP (volatile unsigned short *)DMA2_8_PERIPHERAL_MAP
#define pDMA2_9_CONFIG (volatile unsigned short *)DMA2_9_CONFIG
#define pDMA2_9_NEXT_DESC_PTR (volatile void **)DMA2_9_NEXT_DESC_PTR
#define pDMA2_9_START_ADDR (volatile void **)DMA2_9_START_ADDR
#define pDMA2_9_X_COUNT (volatile unsigned short *)DMA2_9_X_COUNT
#define pDMA2_9_Y_COUNT (volatile unsigned short *)DMA2_9_Y_COUNT
#define pDMA2_9_X_MODIFY (volatile signed short *)DMA2_9_X_MODIFY
#define pDMA2_9_Y_MODIFY (volatile signed short *)DMA2_9_Y_MODIFY
#define pDMA2_9_CURR_DESC_PTR (volatile void **)DMA2_9_CURR_DESC_PTR
#define pDMA2_9_CURR_ADDR (volatile void **)DMA2_9_CURR_ADDR
#define pDMA2_9_CURR_X_COUNT (volatile unsigned short *)DMA2_9_CURR_X_COUNT
#define pDMA2_9_CURR_Y_COUNT (volatile unsigned short *)DMA2_9_CURR_Y_COUNT
#define pDMA2_9_IRQ_STATUS (volatile unsigned short *)DMA2_9_IRQ_STATUS
#define pDMA2_9_PERIPHERAL_MAP (volatile unsigned short *)DMA2_9_PERIPHERAL_MAP
#define pDMA2_10_CONFIG (volatile unsigned short *)DMA2_10_CONFIG
#define pDMA2_10_NEXT_DESC_PTR (volatile void **)DMA2_10_NEXT_DESC_PTR
#define pDMA2_10_START_ADDR (volatile void **)DMA2_10_START_ADDR
#define pDMA2_10_X_COUNT (volatile unsigned short *)DMA2_10_X_COUNT
#define pDMA2_10_Y_COUNT (volatile unsigned short *)DMA2_10_Y_COUNT
#define pDMA2_10_X_MODIFY (volatile signed short *)DMA2_10_X_MODIFY
#define pDMA2_10_Y_MODIFY (volatile signed short *)DMA2_10_Y_MODIFY
#define pDMA2_10_CURR_DESC_PTR (volatile void **)DMA2_10_CURR_DESC_PTR
#define pDMA2_10_CURR_ADDR (volatile void **)DMA2_10_CURR_ADDR
#define pDMA2_10_CURR_X_COUNT (volatile unsigned short *)DMA2_10_CURR_X_COUNT
#define pDMA2_10_CURR_Y_COUNT (volatile unsigned short *)DMA2_10_CURR_Y_COUNT
#define pDMA2_10_IRQ_STATUS (volatile unsigned short *)DMA2_10_IRQ_STATUS
#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP
#define pDMA2_11_CONFIG (volatile unsigned short *)DMA2_11_CONFIG
#define pDMA2_11_NEXT_DESC_PTR (volatile void **)DMA2_11_NEXT_DESC_PTR
#define pDMA2_11_START_ADDR (volatile void **)DMA2_11_START_ADDR
#define pDMA2_11_X_COUNT (volatile unsigned short *)DMA2_11_X_COUNT
#define pDMA2_11_Y_COUNT (volatile unsigned short *)DMA2_11_Y_COUNT
#define pDMA2_11_X_MODIFY (volatile signed short *)DMA2_11_X_MODIFY
#define pDMA2_11_Y_MODIFY (volatile signed short *)DMA2_11_Y_MODIFY
#define pDMA2_11_CURR_DESC_PTR (volatile void **)DMA2_11_CURR_DESC_PTR
#define pDMA2_11_CURR_ADDR (volatile void **)DMA2_11_CURR_ADDR
#define pDMA2_11_CURR_X_COUNT (volatile unsigned short *)DMA2_11_CURR_X_COUNT
#define pDMA2_11_CURR_Y_COUNT (volatile unsigned short *)DMA2_11_CURR_Y_COUNT
#define pDMA2_11_IRQ_STATUS (volatile unsigned short *)DMA2_11_IRQ_STATUS
#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP
/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
#define pMDMA2_D0_CONFIG (volatile unsigned short *)MDMA2_D0_CONFIG
#define pMDMA2_D0_NEXT_DESC_PTR (volatile void **)MDMA2_D0_NEXT_DESC_PTR
#define pMDMA2_D0_START_ADDR (volatile void **)MDMA2_D0_START_ADDR
#define pMDMA2_D0_X_COUNT (volatile unsigned short *)MDMA2_D0_X_COUNT
#define pMDMA2_D0_Y_COUNT (volatile unsigned short *)MDMA2_D0_Y_COUNT
#define pMDMA2_D0_X_MODIFY (volatile signed short *)MDMA2_D0_X_MODIFY
#define pMDMA2_D0_Y_MODIFY (volatile signed short *)MDMA2_D0_Y_MODIFY
#define pMDMA2_D0_CURR_DESC_PTR (volatile void **)MDMA2_D0_CURR_DESC_PTR
#define pMDMA2_D0_CURR_ADDR (volatile void **)MDMA2_D0_CURR_ADDR
#define pMDMA2_D0_CURR_X_COUNT (volatile unsigned short *)MDMA2_D0_CURR_X_COUNT
#define pMDMA2_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT
#define pMDMA2_D0_IRQ_STATUS (volatile unsigned short *)MDMA2_D0_IRQ_STATUS
#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP
#define pMDMA2_S0_CONFIG (volatile unsigned short *)MDMA2_S0_CONFIG
#define pMDMA2_S0_NEXT_DESC_PTR (volatile void **)MDMA2_S0_NEXT_DESC_PTR
#define pMDMA2_S0_START_ADDR (volatile void **)MDMA2_S0_START_ADDR
#define pMDMA2_S0_X_COUNT (volatile unsigned short *)MDMA2_S0_X_COUNT
#define pMDMA2_S0_Y_COUNT (volatile unsigned short *)MDMA2_S0_Y_COUNT
#define pMDMA2_S0_X_MODIFY (volatile signed short *)MDMA2_S0_X_MODIFY
#define pMDMA2_S0_Y_MODIFY (volatile signed short *)MDMA2_S0_Y_MODIFY
#define pMDMA2_S0_CURR_DESC_PTR (volatile void **)MDMA2_S0_CURR_DESC_PTR
#define pMDMA2_S0_CURR_ADDR (volatile void **)MDMA2_S0_CURR_ADDR
#define pMDMA2_S0_CURR_X_COUNT (volatile unsigned short *)MDMA2_S0_CURR_X_COUNT
#define pMDMA2_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT
#define pMDMA2_S0_IRQ_STATUS (volatile unsigned short *)MDMA2_S0_IRQ_STATUS
#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP
#define pMDMA2_D1_CONFIG (volatile unsigned short *)MDMA2_D1_CONFIG
#define pMDMA2_D1_NEXT_DESC_PTR (volatile void **)MDMA2_D1_NEXT_DESC_PTR
#define pMDMA2_D1_START_ADDR (volatile void **)MDMA2_D1_START_ADDR
#define pMDMA2_D1_X_COUNT (volatile unsigned short *)MDMA2_D1_X_COUNT
#define pMDMA2_D1_Y_COUNT (volatile unsigned short *)MDMA2_D1_Y_COUNT
#define pMDMA2_D1_X_MODIFY (volatile signed short *)MDMA2_D1_X_MODIFY
#define pMDMA2_D1_Y_MODIFY (volatile signed short *)MDMA2_D1_Y_MODIFY
#define pMDMA2_D1_CURR_DESC_PTR (volatile void **)MDMA2_D1_CURR_DESC_PTR
#define pMDMA2_D1_CURR_ADDR (volatile void **)MDMA2_D1_CURR_ADDR
#define pMDMA2_D1_CURR_X_COUNT (volatile unsigned short *)MDMA2_D1_CURR_X_COUNT
#define pMDMA2_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT
#define pMDMA2_D1_IRQ_STATUS (volatile unsigned short *)MDMA2_D1_IRQ_STATUS
#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP
#define pMDMA2_S1_CONFIG (volatile unsigned short *)MDMA2_S1_CONFIG
#define pMDMA2_S1_NEXT_DESC_PTR (volatile void **)MDMA2_S1_NEXT_DESC_PTR
#define pMDMA2_S1_START_ADDR (volatile void **)MDMA2_S1_START_ADDR
#define pMDMA2_S1_X_COUNT (volatile unsigned short *)MDMA2_S1_X_COUNT
#define pMDMA2_S1_Y_COUNT (volatile unsigned short *)MDMA2_S1_Y_COUNT
#define pMDMA2_S1_X_MODIFY (volatile signed short *)MDMA2_S1_X_MODIFY
#define pMDMA2_S1_Y_MODIFY (volatile signed short *)MDMA2_S1_Y_MODIFY
#define pMDMA2_S1_CURR_DESC_PTR (volatile void **)MDMA2_S1_CURR_DESC_PTR
#define pMDMA2_S1_CURR_ADDR (volatile void **)MDMA2_S1_CURR_ADDR
#define pMDMA2_S1_CURR_X_COUNT (volatile unsigned short *)MDMA2_S1_CURR_X_COUNT
#define pMDMA2_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT
#define pMDMA2_S1_IRQ_STATUS (volatile unsigned short *)MDMA2_S1_IRQ_STATUS
#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP
/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
#define pIMDMA_D0_CONFIG (volatile unsigned short *)IMDMA_D0_CONFIG
#define pIMDMA_D0_NEXT_DESC_PTR (volatile void **)IMDMA_D0_NEXT_DESC_PTR
#define pIMDMA_D0_START_ADDR (volatile void **)IMDMA_D0_START_ADDR
#define pIMDMA_D0_X_COUNT (volatile unsigned short *)IMDMA_D0_X_COUNT
#define pIMDMA_D0_Y_COUNT (volatile unsigned short *)IMDMA_D0_Y_COUNT
#define pIMDMA_D0_X_MODIFY (volatile signed short *)IMDMA_D0_X_MODIFY
#define pIMDMA_D0_Y_MODIFY (volatile signed short *)IMDMA_D0_Y_MODIFY
#define pIMDMA_D0_CURR_DESC_PTR (volatile void **)IMDMA_D0_CURR_DESC_PTR
#define pIMDMA_D0_CURR_ADDR (volatile void **)IMDMA_D0_CURR_ADDR
#define pIMDMA_D0_CURR_X_COUNT (volatile unsigned short *)IMDMA_D0_CURR_X_COUNT
#define pIMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT
#define pIMDMA_D0_IRQ_STATUS (volatile unsigned short *)IMDMA_D0_IRQ_STATUS
#define pIMDMA_S0_CONFIG (volatile unsigned short *)IMDMA_S0_CONFIG
#define pIMDMA_S0_NEXT_DESC_PTR (volatile void **)IMDMA_S0_NEXT_DESC_PTR
#define pIMDMA_S0_START_ADDR (volatile void **)IMDMA_S0_START_ADDR
#define pIMDMA_S0_X_COUNT (volatile unsigned short *)IMDMA_S0_X_COUNT
#define pIMDMA_S0_Y_COUNT (volatile unsigned short *)IMDMA_S0_Y_COUNT
#define pIMDMA_S0_X_MODIFY (volatile signed short *)IMDMA_S0_X_MODIFY
#define pIMDMA_S0_Y_MODIFY (volatile signed short *)IMDMA_S0_Y_MODIFY
#define pIMDMA_S0_CURR_DESC_PTR (volatile void **)IMDMA_S0_CURR_DESC_PTR
#define pIMDMA_S0_CURR_ADDR (volatile void **)IMDMA_S0_CURR_ADDR
#define pIMDMA_S0_CURR_X_COUNT (volatile unsigned short *)IMDMA_S0_CURR_X_COUNT
#define pIMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT
#define pIMDMA_S0_IRQ_STATUS (volatile unsigned short *)IMDMA_S0_IRQ_STATUS
#define pIMDMA_D1_CONFIG (volatile unsigned short *)IMDMA_D1_CONFIG
#define pIMDMA_D1_NEXT_DESC_PTR (volatile void **)IMDMA_D1_NEXT_DESC_PTR
#define pIMDMA_D1_START_ADDR (volatile void **)IMDMA_D1_START_ADDR
#define pIMDMA_D1_X_COUNT (volatile unsigned short *)IMDMA_D1_X_COUNT
#define pIMDMA_D1_Y_COUNT (volatile unsigned short *)IMDMA_D1_Y_COUNT
#define pIMDMA_D1_X_MODIFY (volatile signed short *)IMDMA_D1_X_MODIFY
#define pIMDMA_D1_Y_MODIFY (volatile signed short *)IMDMA_D1_Y_MODIFY
#define pIMDMA_D1_CURR_DESC_PTR (volatile void **)IMDMA_D1_CURR_DESC_PTR
#define pIMDMA_D1_CURR_ADDR (volatile void **)IMDMA_D1_CURR_ADDR
#define pIMDMA_D1_CURR_X_COUNT (volatile unsigned short *)IMDMA_D1_CURR_X_COUNT
#define pIMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT
#define pIMDMA_D1_IRQ_STATUS (volatile unsigned short *)IMDMA_D1_IRQ_STATUS
#define pIMDMA_S1_CONFIG (volatile unsigned short *)IMDMA_S1_CONFIG
#define pIMDMA_S1_NEXT_DESC_PTR (volatile void **)IMDMA_S1_NEXT_DESC_PTR
#define pIMDMA_S1_START_ADDR (volatile void **)IMDMA_S1_START_ADDR
#define pIMDMA_S1_X_COUNT (volatile unsigned short *)IMDMA_S1_X_COUNT
#define pIMDMA_S1_Y_COUNT (volatile unsigned short *)IMDMA_S1_Y_COUNT
#define pIMDMA_S1_X_MODIFY (volatile signed short *)IMDMA_S1_X_MODIFY
#define pIMDMA_S1_Y_MODIFY (volatile signed short *)IMDMA_S1_Y_MODIFY
#define pIMDMA_S1_CURR_DESC_PTR (volatile void **)IMDMA_S1_CURR_DESC_PTR
#define pIMDMA_S1_CURR_ADDR (volatile void **)IMDMA_S1_CURR_ADDR
#define pIMDMA_S1_CURR_X_COUNT (volatile unsigned short *)IMDMA_S1_CURR_X_COUNT
#define pIMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT
#define pIMDMA_S1_IRQ_STATUS (volatile unsigned short *)IMDMA_S1_IRQ_STATUS
/*
* System Reset and Interrupt Controller registers for
* core A (0xFFC0 0100-0xFFC0 01FF)
*/
#define pSWRST (volatile unsigned short *)SICA_SWRST
#define pSYSCR (volatile unsigned short *)SICA_SYSCR
#define pRVECT (volatile unsigned short *)SICA_RVECT
#define pSIC_SWRST (volatile unsigned short *)SICA_SWRST
#define pSIC_SYSCR (volatile unsigned short *)SICA_SYSCR
#define pSIC_RVECT (volatile unsigned short *)SICA_RVECT
#define pSIC_IMASK (volatile unsigned long *)SICA_IMASK
#define pSIC_IAR0 ((volatile unsigned long *)SICA_IAR0)
#define pSIC_IAR1 (volatile unsigned long *)SICA_IAR1
#define pSIC_IAR2 (volatile unsigned long *)SICA_IAR2
#define pSIC_ISR (volatile unsigned long *)SICA_ISR0
#define pSIC_IWR (volatile unsigned long *)SICA_IWR0
/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
#define pWDOG_CTL (volatile unsigned short *)WDOGA_CTL
#define pWDOG_CNT (volatile unsigned long *)WDOGA_CNT
#define pWDOG_STAT (volatile unsigned long *)WDOGA_STAT
/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
#define pFIO_FLAG_D (volatile unsigned short *)FIO0_FLAG_D
#define pFIO_FLAG_C (volatile unsigned short *)FIO0_FLAG_C
#define pFIO_FLAG_S (volatile unsigned short *)FIO0_FLAG_S
#define pFIO_FLAG_T (volatile unsigned short *)FIO0_FLAG_T
#define pFIO_MASKA_D (volatile unsigned short *)FIO0_MASKA_D
#define pFIO_MASKA_C (volatile unsigned short *)FIO0_MASKA_C
#define pFIO_MASKA_S (volatile unsigned short *)FIO0_MASKA_S
#define pFIO_MASKA_T (volatile unsigned short *)FIO0_MASKA_T
#define pFIO_MASKB_D (volatile unsigned short *)FIO0_MASKB_D
#define pFIO_MASKB_C (volatile unsigned short *)FIO0_MASKB_C
#define pFIO_MASKB_S (volatile unsigned short *)FIO0_MASKB_S
#define pFIO_MASKB_T (volatile unsigned short *)FIO0_MASKB_T
#define pFIO_DIR (volatile unsigned short *)FIO0_DIR
#define pFIO_POLAR (volatile unsigned short *)FIO0_POLAR
#define pFIO_EDGE (volatile unsigned short *)FIO0_EDGE
#define pFIO_BOTH (volatile unsigned short *)FIO0_BOTH
#define pFIO_INEN (volatile unsigned short *)FIO0_INEN
/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF)*/
#define pPPI_CONTROL (volatile unsigned short *)PPI0_CONTROL
#define pPPI_STATUS (volatile unsigned short *)PPI0_STATUS
#define pPPI_COUNT (volatile unsigned short *)PPI0_COUNT
#define pPPI_DELAY (volatile unsigned short *)PPI0_DELAY
#define pPPI_FRAME (volatile unsigned short *)PPI0_FRAME
/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
#define pDMA0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG
#define pDMA0_NEXT_DESC_PTR (volatile void **)DMA1_0_NEXT_DESC_PTR
#define pDMA0_START_ADDR (volatile void **)DMA1_0_START_ADDR
#define pDMA0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT
#define pDMA0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT
#define pDMA0_X_MODIFY (volatile unsigned short *)DMA1_0_X_MODIFY
#define pDMA0_Y_MODIFY (volatile unsigned short *)DMA1_0_Y_MODIFY
#define pDMA0_CURR_DESC_PTR (volatile void **)DMA1_0_CURR_DESC_PTR
#define pDMA0_CURR_ADDR (volatile void **)DMA1_0_CURR_ADDR
#define pDMA0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT
#define pDMA0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT
#define pDMA0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS
#define pDMA0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
#define pMDMA_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG
#define pMDMA_D0_NEXT_DESC_PTR (volatile void **)MDMA1_D0_NEXT_DESC_PTR
#define pMDMA_D0_START_ADDR (volatile void **)MDMA1_D0_START_ADDR
#define pMDMA_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT
#define pMDMA_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT
#define pMDMA_D0_X_MODIFY (volatile unsigned short *)MDMA1_D0_X_MODIFY
#define pMDMA_D0_Y_MODIFY (volatile unsigned short *)MDMA1_D0_Y_MODIFY
#define pMDMA_D0_CURR_DESC_PTR (volatile void **)MDMA1_D0_CURR_DESC_PTR
#define pMDMA_D0_CURR_ADDR (volatile void **)MDMA1_D0_CURR_ADDR
#define pMDMA_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
#define pMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
#define pMDMA_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS
#define pMDMA_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
#define pMDMA_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG
#define pMDMA_S0_NEXT_DESC_PTR (volatile void **)MDMA1_S0_NEXT_DESC_PTR
#define pMDMA_S0_START_ADDR (volatile void **)MDMA1_S0_START_ADDR
#define pMDMA_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT
#define pMDMA_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT
#define pMDMA_S0_X_MODIFY (volatile unsigned short *)MDMA1_S0_X_MODIFY
#define pMDMA_S0_Y_MODIFY (volatile unsigned short *)MDMA1_S0_Y_MODIFY
#define pMDMA_S0_CURR_DESC_PTR (volatile void **)MDMA1_S0_CURR_DESC_PTR
#define pMDMA_S0_CURR_ADDR (volatile void **)MDMA1_S0_CURR_ADDR
#define pMDMA_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
#define pMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
#define pMDMA_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS
#define pMDMA_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
#define pMDMA_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG
#define pMDMA_D1_NEXT_DESC_PTR (volatile void **)MDMA1_D1_NEXT_DESC_PTR
#define pMDMA_D1_START_ADDR (volatile void **)MDMA1_D1_START_ADDR
#define pMDMA_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT
#define pMDMA_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT
#define pMDMA_D1_X_MODIFY (volatile unsigned short *)MDMA1_D1_X_MODIFY
#define pMDMA_D1_Y_MODIFY (volatile unsigned short *)MDMA1_D1_Y_MODIFY
#define pMDMA_D1_CURR_DESC_PTR (volatile void **)MDMA1_D1_CURR_DESC_PTR
#define pMDMA_D1_CURR_ADDR (volatile void **)MDMA1_D1_CURR_ADDR
#define pMDMA_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
#define pMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
#define pMDMA_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS
#define pMDMA_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
#define pMDMA_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG
#define pMDMA_S1_NEXT_DESC_PTR (volatile void **)MDMA1_S1_NEXT_DESC_PTR
#define pMDMA_S1_START_ADDR (volatile void **)MDMA1_S1_START_ADDR
#define pMDMA_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT
#define pMDMA_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT
#define pMDMA_S1_X_MODIFY (volatile unsigned short *)MDMA1_S1_X_MODIFY
#define pMDMA_S1_Y_MODIFY (volatile unsigned short *)MDMA1_S1_Y_MODIFY
#define pMDMA_S1_CURR_DESC_PTR (volatile void **)MDMA1_S1_CURR_DESC_PTR
#define pMDMA_S1_CURR_ADDR (volatile void **)MDMA1_S1_CURR_ADDR
#define pMDMA_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
#define pMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
#define pMDMA_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS
#define pMDMA_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
#define pDMA1_CONFIG (volatile unsigned short *)DMA2_0_CONFIG
#define pDMA1_NEXT_DESC_PTR (volatile void **)DMA2_0_NEXT_DESC_PTR
#define pDMA1_START_ADDR (volatile void **)DMA2_0_START_ADDR
#define pDMA1_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT
#define pDMA1_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT
#define pDMA1_X_MODIFY (volatile unsigned short *)DMA2_0_X_MODIFY
#define pDMA1_Y_MODIFY (volatile unsigned short *)DMA2_0_Y_MODIFY
#define pDMA1_CURR_DESC_PTR (volatile void **)DMA2_0_CURR_DESC_PTR
#define pDMA1_CURR_ADDR (volatile void **)DMA2_0_CURR_ADDR
#define pDMA1_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT
#define pDMA1_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT
#define pDMA1_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS
#define pDMA1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
#define pDMA2_CONFIG (volatile unsigned short *)DMA2_1_CONFIG
#define pDMA2_NEXT_DESC_PTR (volatile void **)DMA2_1_NEXT_DESC_PTR
#define pDMA2_START_ADDR (volatile void **)DMA2_1_START_ADDR
#define pDMA2_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT
#define pDMA2_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT
#define pDMA2_X_MODIFY (volatile unsigned short *)DMA2_1_X_MODIFY
#define pDMA2_Y_MODIFY (volatile unsigned short *)DMA2_1_Y_MODIFY
#define pDMA2_CURR_DESC_PTR (volatile void **)DMA2_1_CURR_DESC_PTR
#define pDMA2_CURR_ADDR (volatile void **)DMA2_1_CURR_ADDR
#define pDMA2_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT
#define pDMA2_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT
#define pDMA2_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS
#define pDMA2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
#define pDMA3_CONFIG (volatile unsigned short *)DMA2_2_CONFIG
#define pDMA3_NEXT_DESC_PTR (volatile void **)DMA2_2_NEXT_DESC_PTR
#define pDMA3_START_ADDR (volatile void **)DMA2_2_START_ADDR
#define pDMA3_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT
#define pDMA3_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT
#define pDMA3_X_MODIFY (volatile unsigned short *)DMA2_2_X_MODIFY
#define pDMA3_Y_MODIFY (volatile unsigned short *)DMA2_2_Y_MODIFY
#define pDMA3_CURR_DESC_PTR (volatile void **)DMA2_2_CURR_DESC_PTR
#define pDMA3_CURR_ADDR (volatile void **)DMA2_2_CURR_ADDR
#define pDMA3_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT
#define pDMA3_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT
#define pDMA3_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS
#define pDMA3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
#define pDMA4_CONFIG (volatile unsigned short *)DMA2_3_CONFIG
#define pDMA4_NEXT_DESC_PTR (volatile void **)DMA2_3_NEXT_DESC_PTR
#define pDMA4_START_ADDR (volatile void **)DMA2_3_START_ADDR
#define pDMA4_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT
#define pDMA4_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT
#define pDMA4_X_MODIFY (volatile unsigned short *)DMA2_3_X_MODIFY
#define pDMA4_Y_MODIFY (volatile unsigned short *)DMA2_3_Y_MODIFY
#define pDMA4_CURR_DESC_PTR (volatile void **)DMA2_3_CURR_DESC_PTR
#define pDMA4_CURR_ADDR (volatile void **)DMA2_3_CURR_ADDR
#define pDMA4_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT
#define pDMA4_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT
#define pDMA4_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS
#define pDMA4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
#define pDMA5_CONFIG (volatile unsigned short *)DMA2_4_CONFIG
#define pDMA5_NEXT_DESC_PTR (volatile void **)DMA2_4_NEXT_DESC_PTR
#define pDMA5_START_ADDR (volatile void **)DMA2_4_START_ADDR
#define pDMA5_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT
#define pDMA5_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT
#define pDMA5_X_MODIFY (volatile unsigned short *)DMA2_4_X_MODIFY
#define pDMA5_Y_MODIFY (volatile unsigned short *)DMA2_4_Y_MODIFY
#define pDMA5_CURR_DESC_PTR (volatile void **)DMA2_4_CURR_DESC_PTR
#define pDMA5_CURR_ADDR (volatile void **)DMA2_4_CURR_ADDR
#define pDMA5_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT
#define pDMA5_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT
#define pDMA5_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS
#define pDMA5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
#define pDMA6_CONFIG (volatile unsigned short *)DMA2_5_CONFIG
#define pDMA6_NEXT_DESC_PTR (volatile void **)DMA2_5_NEXT_DESC_PTR
#define pDMA6_START_ADDR (volatile void **)DMA2_5_START_ADDR
#define pDMA6_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT
#define pDMA6_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT
#define pDMA6_X_MODIFY (volatile unsigned short *)DMA2_5_X_MODIFY
#define pDMA6_Y_MODIFY (volatile unsigned short *)DMA2_5_Y_MODIFY
#define pDMA6_CURR_DESC_PTR (volatile void **)DMA2_5_CURR_DESC_PTR
#define pDMA6_CURR_ADDR (volatile void **)DMA2_5_CURR_ADDR
#define pDMA6_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT
#define pDMA6_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT
#define pDMA6_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS
#define pDMA6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
#define pDMA7_CONFIG (volatile unsigned short *)DMA2_6_CONFIG
#define pDMA7_NEXT_DESC_PTR (volatile void **)DMA2_6_NEXT_DESC_PTR
#define pDMA7_START_ADDR (volatile void **)DMA2_6_START_ADDR
#define pDMA7_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT
#define pDMA7_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT
#define pDMA7_X_MODIFY (volatile unsigned short *)DMA2_6_X_MODIFY
#define pDMA7_Y_MODIFY (volatile unsigned short *)DMA2_6_Y_MODIFY
#define pDMA7_CURR_DESC_PTR (volatile void **)DMA2_6_CURR_DESC_PTR
#define pDMA7_CURR_ADDR (volatile void **)DMA2_6_CURR_ADDR
#define pDMA7_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT
#define pDMA7_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT
#define pDMA7_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS
#define pDMA7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
#endif /* _CDEF_BF561_H */

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include/asm-blackfin/arch-bf561/defBF561.h Normal file
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include/asm-blackfin/arch-bf561/defBF561_extn.h Normal file
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/*
* defBF561_extn.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
#ifndef _DEF_BF561_EXTN_H
#define _DEF_BF561_EXTN_H
#define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
/* Delay inserted for PLL transition */
#define PLL_DELAY 0x1000
#define L1_ISRAM 0xFFA00000
#define L1_ISRAM_END 0xFFA10000
#define DATA_BANKA_SRAM 0xFF800000
#define DATA_BANKA_SRAM_END 0xFF808000
#define DATA_BANKB_SRAM 0xFF900000
#define DATA_BANKB_SRAM_END 0xFF908000
#define SYSMMR_BASE 0xFFC00000
#define WDSIZE16 0x00000004
/* Event Vector Table Address */
#define EVT_EMULATION_ADDR 0xffe02000
#define EVT_RESET_ADDR 0xffe02004
#define EVT_NMI_ADDR 0xffe02008
#define EVT_EXCEPTION_ADDR 0xffe0200c
#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
#define EVT_TIMER_ADDR 0xffe02018
#define EVT_IVG7_ADDR 0xffe0201c
#define EVT_IVG8_ADDR 0xffe02020
#define EVT_IVG9_ADDR 0xffe02024
#define EVT_IVG10_ADDR 0xffe02028
#define EVT_IVG11_ADDR 0xffe0202c
#define EVT_IVG12_ADDR 0xffe02030
#define EVT_IVG13_ADDR 0xffe02034
#define EVT_IVG14_ADDR 0xffe02038
#define EVT_IVG15_ADDR 0xffe0203c
#define EVT_OVERRIDE_ADDR 0xffe02100
/* IMASK Bit values */
#define IVG15_POS 0x00008000
#define IVG14_POS 0x00004000
#define IVG13_POS 0x00002000
#define IVG12_POS 0x00001000
#define IVG11_POS 0x00000800
#define IVG10_POS 0x00000400
#define IVG9_POS 0x00000200
#define IVG8_POS 0x00000100
#define IVG7_POS 0x00000080
#define IVGTMR_POS 0x00000040
#define IVGHW_POS 0x00000020
#define WDOG_TMR_DISABLE (0xAD << 4)
#define ICTL_RST 0x00000000
#define ICTL_NMI 0x00000002
#define ICTL_GP 0x00000004
#define ICTL_DISABLE 0x00000003
/* Watch Dog timer values setup */
#define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE
#endif /* _DEF_BF561_EXTN_H */

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/*
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* Changed by HuTao Apr18, 2003
*
* Copyright was missing when I got the code so took from MIPS arch ...MaTed---
* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
* Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
*
* Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
* Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
* Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
*
* Adapted for BlackFin BF533 by Bas Vermeulen <bas@buyways.nl>
* Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
* Copyright (c) 2004 LG Soft India.
* Copyright (c) 2004 HHTech.
*
* Adapted for BlackFin BF561 by Bas Vermeulen <bas@buyways.nl>
* Copyright (c) 2005 BuyWays B.V. (www.buyways.nl)
*/
#ifndef _BF561_IRQ_H_
#define _BF561_IRQ_H_
/*
* Interrupt source definitions:
* Event Source Core Event Name IRQ No
* Emulation Events EMU 0
* Reset RST 1
* NMI NMI 2
* Exception EVX 3
* Reserved -- 4
* Hardware Error IVHW 5
* Core Timer IVTMR 6
*
* PLL Wakeup Interrupt IVG7 7
* DMA1 Error (generic) IVG7 8
* DMA2 Error (generic) IVG7 9
* IMDMA Error (generic) IVG7 10
* PPI1 Error Interrupt IVG7 11
* PPI2 Error Interrupt IVG7 12
* SPORT0 Error Interrupt IVG7 13
* SPORT1 Error Interrupt IVG7 14
* SPI Error Interrupt IVG7 15
* UART Error Interrupt IVG7 16
* Reserved Interrupt IVG7 17
*
* DMA1 0 Interrupt(PPI1) IVG8 18
* DMA1 1 Interrupt(PPI2) IVG8 19
* DMA1 2 Interrupt IVG8 20
* DMA1 3 Interrupt IVG8 21
* DMA1 4 Interrupt IVG8 22
* DMA1 5 Interrupt IVG8 23
* DMA1 6 Interrupt IVG8 24
* DMA1 7 Interrupt IVG8 25
* DMA1 8 Interrupt IVG8 26
* DMA1 9 Interrupt IVG8 27
* DMA1 10 Interrupt IVG8 28
* DMA1 11 Interrupt IVG8 29
*
* DMA2 0 (SPORT0 RX) IVG9 30
* DMA2 1 (SPORT0 TX) IVG9 31
* DMA2 2 (SPORT1 RX) IVG9 32
* DMA2 3 (SPORT2 TX) IVG9 33
* DMA2 4 (SPI) IVG9 34
* DMA2 5 (UART RX) IVG9 35
* DMA2 6 (UART TX) IVG9 36
* DMA2 7 Interrupt IVG9 37
* DMA2 8 Interrupt IVG9 38
* DMA2 9 Interrupt IVG9 39
* DMA2 10 Interrupt IVG9 40
* DMA2 11 Interrupt IVG9 41
*
* TIMER 0 Interrupt IVG10 42
* TIMER 1 Interrupt IVG10 43
* TIMER 2 Interrupt IVG10 44
* TIMER 3 Interrupt IVG10 45
* TIMER 4 Interrupt IVG10 46
* TIMER 5 Interrupt IVG10 47
* TIMER 6 Interrupt IVG10 48
* TIMER 7 Interrupt IVG10 49
* TIMER 8 Interrupt IVG10 50
* TIMER 9 Interrupt IVG10 51
* TIMER 10 Interrupt IVG10 52
* TIMER 11 Interrupt IVG10 53
*
* Programmable Flags0 A (8) IVG11 54
* Programmable Flags0 B (8) IVG11 55
* Programmable Flags1 A (8) IVG11 56
* Programmable Flags1 B (8) IVG11 57
* Programmable Flags2 A (8) IVG11 58
* Programmable Flags2 B (8) IVG11 59
*
* MDMA1 0 write/read INT IVG8 60
* MDMA1 1 write/read INT IVG8 61
*
* MDMA2 0 write/read INT IVG9 62
* MDMA2 1 write/read INT IVG9 63
*
* IMDMA 0 write/read INT IVG12 64
* IMDMA 1 write/read INT IVG12 65
*
* Watch Dog Timer IVG13 66
*
* Reserved interrupt IVG7 67
* Reserved interrupt IVG7 68
* Supplemental interrupt 0 IVG7 69
* supplemental interrupt 1 IVG7 70
*
* Software Interrupt 1 IVG14 71
* Software Interrupt 2 IVG15 72
*/
/*
* The ABSTRACT IRQ definitions
* the first seven of the following are fixed,
* the rest you change if you need to.
*/
/* IVG 0-6 */
#define IRQ_EMU 0 /* Emulation */
#define IRQ_RST 1 /* Reset */
#define IRQ_NMI 2 /* Non Maskable Interrupt */
#define IRQ_EVX 3 /* Exception */
#define IRQ_UNUSED 4 /* Reserved interrupt */
#define IRQ_HWERR 5 /* Hardware Error */
#define IRQ_CORETMR 6 /* Core timer */
#define IRQ_UART_RX_BIT 0x10000000
#define IRQ_UART_TX_BIT 0x20000000
#define IRQ_UART_ERROR_BIT 0x200
#endif /* _BF561_IRQ_H_ */

46
include/asm-blackfin/arch-common/bf53x_rtc.h Normal file
View File

@@ -0,0 +1,46 @@
/*
* U-boot - bf533_rtc.h
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BF533_RTC_H_
#define _BF533_RTC_H_
void rtc_init(void);
void wait_for_complete(void);
void rtc_reset(void);
#define MIN_TO_SECS(_x_) (60 * _x_)
#define HRS_TO_SECS(_x_) (60 * 60 * _x_)
#define DAYS_TO_SECS(_x_) (24 * 60 * 60 * _x_)
#define NUM_SECS_IN_DAY (24 * 3600)
#define NUM_SECS_IN_HOUR (3600)
#define NUM_SECS_IN_MIN (60)
/* Shift values for RTC_STAT register */
#define DAY_BITS_OFF 17
#define HOUR_BITS_OFF 12
#define MIN_BITS_OFF 6
#define SEC_BITS_OFF 0
#endif

40
include/asm-blackfin/arch-common/cdefBF5xx.h Normal file
View File

@@ -0,0 +1,40 @@
/************************************************************************
*
* cdefBF53x.h
*
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
*
************************************************************************/
#ifndef _CDEFBF53x_H
#define _CDEFBF53x_H
#if defined(__ADSPBF531__)
#include <asm/arch-bf533/cdefBF531.h>
#elif defined(__ADSPBF532__)
#include <asm/arch-bf533/cdefBF532.h>
#elif defined(__ADSPBF533__)
#include <asm/arch-bf533/cdefBF533.h>
#include <asm/arch-bf533/defBF533_extn.h>
#include <asm/arch-bf533/bf533_serial.h>
#elif defined(__ADSPBF537__)
#include <asm/arch-bf537/cdefBF537.h>
#include <asm/arch-bf537/defBF537_extn.h>
#include <asm/arch-bf537/bf537_serial.h>
#elif defined(__ADSPBF561__)
#include <asm/arch-bf561/cdefBF561.h>
#include <asm/arch-bf561/defBF561_extn.h>
#include <asm/arch-bf561/bf561_serial.h>
#elif defined(__ADSPBF535__)
#include <asm/cpu/cdefBF5d35.h>
#elif defined(__AD6532__)
#include <asm/cpu/cdefAD6532.h>
#else
#if defined(__ADSPLPBLACKFIN__)
#include <asm/arch-bf533/cdefBF532.h>
#else
#include <asm/arch-bf533/cdefBF535.h>
#endif
#endif
#endif /* _CDEFBF53x_H */

45
include/asm-blackfin/cpu/cdef_LPBlackfin.h → include/asm-blackfin/arch-common/cdef_LPBlackfin.h
View File

@@ -1,38 +1,24 @@
/*
/************************************************************************
*
* cdef_LPBlackfin.h
*
* This file is subject to the terms and conditions of the GNU Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
*
* Non-GPL License also available as part of VisualDSP++
*
* http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
*
* (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
*
* This file under source code control, please send bugs or changes to:
* dsptools.support@analog.com
*
*/
************************************************************************/
#ifndef _CDEF_LPBLACKFIN_H
#define _CDEF_LPBLACKFIN_H
/*
* #if !defined(__ADSPLPBLACKFIN__)
* #warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
* #endif
*/
#include <asm/cpu/def_LPBlackfin.h>
#if !defined(__ADSPLPBLACKFIN__)
#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
#endif
#include <asm/arch-common/def_LPBlackfin.h>
/* Cache & SRAM Memory */
/* Cache & SRAM Memory */
#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
/* #define MMR_TIMEOUT 0xFFE00010 */ /* Memory-Mapped Register Timeout Register */
#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
@@ -66,15 +52,8 @@
#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
/* #define DTEST_INDEX 0xFFE00304 */ /* Data Test Index Register */
#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
/*
* # define DTEST_DATA2 0xFFE00408 Data Test Data Register
* #define DTEST_DATA3 0xFFE0040C Data Test Data Register
*/
#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
@@ -111,8 +90,6 @@
#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
/* #define ITEST_INDEX 0xFFE01304 */ /* Instruction Test Index Register */
#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
@@ -180,6 +157,4 @@
#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
/* #define IPRIO 0xFFE02110 */ /* Core Interrupt Priority Register */
#endif /* _CDEF_LPBLACKFIN_H */
#endif /* _CDEF_LPBLACKFIN_H */

4
include/asm-blackfin/cpu/def_LPBlackfin.h → include/asm-blackfin/arch-common/def_LPBlackfin.h
View File

@@ -92,13 +92,13 @@
/* ** Masks */
/* Exception cause */
#define SEQSTAT_EXCAUSE MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
#define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
0
0 )
/* Indicates whether the last reset was a software reset (=1) */
#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P )

48
include/asm-blackfin/bitops.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - bitops.h Routines for bit operations
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_BITOPS_H
@@ -59,7 +59,7 @@ static __inline__ unsigned long ffz(unsigned long word)
static __inline__ void set_bit(int nr, volatile void *addr)
{
int *a = (int *) addr;
int *a = (int *)addr;
int mask;
unsigned long flags;
@@ -72,7 +72,7 @@ static __inline__ void set_bit(int nr, volatile void *addr)
static __inline__ void __set_bit(int nr, volatile void *addr)
{
int *a = (int *) addr;
int *a = (int *)addr;
int mask;
a += nr >> 5;
@@ -88,7 +88,7 @@ static __inline__ void __set_bit(int nr, volatile void *addr)
static __inline__ void clear_bit(int nr, volatile void *addr)
{
int *a = (int *) addr;
int *a = (int *)addr;
int mask;
unsigned long flags;
@@ -102,7 +102,7 @@ static __inline__ void clear_bit(int nr, volatile void *addr)
static __inline__ void change_bit(int nr, volatile void *addr)
{
int mask, flags;
unsigned long *ADDR = (unsigned long *) addr;
unsigned long *ADDR = (unsigned long *)addr;
ADDR += nr >> 5;
mask = 1 << (nr & 31);
@@ -114,7 +114,7 @@ static __inline__ void change_bit(int nr, volatile void *addr)
static __inline__ void __change_bit(int nr, volatile void *addr)
{
int mask;
unsigned long *ADDR = (unsigned long *) addr;
unsigned long *ADDR = (unsigned long *)addr;
ADDR += nr >> 5;
mask = 1 << (nr & 31);
@@ -124,7 +124,7 @@ static __inline__ void __change_bit(int nr, volatile void *addr)
static __inline__ int test_and_set_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
volatile unsigned int *a = (volatile unsigned int *)addr;
unsigned long flags;
a += nr >> 5;
@@ -140,7 +140,7 @@ static __inline__ int test_and_set_bit(int nr, volatile void *addr)
static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
volatile unsigned int *a = (volatile unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
@@ -152,7 +152,7 @@ static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
volatile unsigned int *a = (volatile unsigned int *)addr;
unsigned long flags;
a += nr >> 5;
@@ -168,7 +168,7 @@ static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
volatile unsigned int *a = (volatile unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
@@ -180,7 +180,7 @@ static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
static __inline__ int test_and_change_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
volatile unsigned int *a = (volatile unsigned int *)addr;
unsigned long flags;
a += nr >> 5;
@@ -196,7 +196,7 @@ static __inline__ int test_and_change_bit(int nr, volatile void *addr)
static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = (volatile unsigned int *) addr;
volatile unsigned int *a = (volatile unsigned int *)addr;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
@@ -208,16 +208,15 @@ static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
/*
* This routine doesn't need to be atomic.
*/
static __inline__ int __constant_test_bit(int nr,
const volatile void *addr)
static __inline__ int __constant_test_bit(int nr, const volatile void *addr)
{
return ((1UL << (nr & 31)) &
(((const volatile unsigned int *) addr)[nr >> 5])) != 0;
(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
}
static __inline__ int __test_bit(int nr, volatile void *addr)
{
int *a = (int *) addr;
int *a = (int *)addr;
int mask;
a += nr >> 5;
@@ -235,7 +234,7 @@ static __inline__ int __test_bit(int nr, volatile void *addr)
static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;
@@ -290,7 +289,7 @@ static __inline__ int ext2_set_bit(int nr, volatile void *addr)
{
int mask, retval;
unsigned long flags;
volatile unsigned char *ADDR = (unsigned char *) addr;
volatile unsigned char *ADDR = (unsigned char *)addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
@@ -305,7 +304,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
unsigned long flags;
volatile unsigned char *ADDR = (unsigned char *) addr;
volatile unsigned char *ADDR = (unsigned char *)addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
@@ -319,7 +318,7 @@ static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
{
int mask;
const volatile unsigned char *ADDR = (const unsigned char *) addr;
const volatile unsigned char *ADDR = (const unsigned char *)addr;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
@@ -331,10 +330,9 @@ static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
unsigned long size,
unsigned long
offset)
unsigned long offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
unsigned long result = offset & ~31UL;
unsigned long tmp;

26
include/asm-blackfin/blackfin.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - blackfin.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,29 +18,23 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_H_
#define _BLACKFIN_H_
#include <asm/cpu/defBF533.h>
#include <asm/cpu/bf533_serial.h>
#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
# ifdef SHARED_RESOURCES
# include <asm/shared_resources.h>
# endif
#ifndef __ASSEMBLY__
#ifndef ASSEMBLY
# include <linux/types.h>
#ifdef SHARED_RESOURCES
#include <asm/shared_resources.h>
#endif
#include <asm/cpu/cdefBF53x.h>
#endif
extern u_long get_sclk(void);
#endif
#include <asm/cpu/defBF533.h>
#include <asm/cpu/defBF533_extn.h>
#include <asm/cpu/bf533_serial.h>
#include <asm/arch-common/cdefBF5xx.h>
#endif

6
include/asm-blackfin/blackfin_defs.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - blackfin_defs.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __BLACKFIN_DEFS_H__

6
include/asm-blackfin/byteorder.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - byteorder.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_BYTEORDER_H

38
include/asm-blackfin/cplb.h
View File

@@ -7,14 +7,15 @@
************************************************************************/
/* Defines necessary for cplb initialisation routines. */
#ifndef _CPLB_H
#define _CPLB_H
#define CONFIG_BLKFIN_WT
#define CPLB_ENABLE_ICACHE_P 0
#define CPLB_ENABLE_DCACHE_P 1
#define CPLB_ENABLE_DCACHE2_P 2
#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/
#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
#define CPLB_ENABLE_ICPLBS_P 4
#define CPLB_ENABLE_DCPLBS_P 5
@@ -45,4 +46,35 @@
#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
#endif /* _CPLB_H */
/* Data Attibutes*/
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
#define ANOMALY_05000158 0x200
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
#else /*Write Through */
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
#endif
#if defined(CONFIG_BF561)
#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */
#else
#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */
#endif
#endif /* _CPLB_H */

572
include/asm-blackfin/cplbtab.h
View File

@@ -1,572 +0,0 @@
/*This file is subject to the terms and conditions of the GNU General Public
* License.
*
* Blackfin BF533/2.6 support : LG Soft India
* Updated : Ashutosh Singh / Jahid Khan : Rrap Software Pvt Ltd
* Updated : 1. SDRAM_KERNEL, SDRAM_DKENEL are added as initial cplb's
* shouldn't be victimized. cplbmgr.S search logic is corrected
* to findout the appropriate victim.
* 2. SDRAM_IGENERIC in dpdt_table is replaced with SDRAM_DGENERIC
* : LG Soft India
*/
#include <config.h>
#ifndef __ARCH_BFINNOMMU_CPLBTAB_H
#define __ARCH_BFINNOMMU_CPLBTAB_H
/*************************************************************************
* ICPLB TABLE
*************************************************************************/
.data
/* This table is configurable */
.align 4;
/* Data Attibutes*/
#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID)
#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
#define ANOMALY_05000158 0x200
#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
#else /*Write Through*/
#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158)
#define L1_DMEMORY (PAGE_SIZE_4KB | CPLB_L1_CHBL | CPLB_L1_AOW | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158)
#define SDRAM_EBIU (PAGE_SIZE_1MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158)
#endif
.global icplb_table
icplb_table:
.byte4 0xFFA00000;
.byte4 (L1_IMEMORY);
.byte4 0x00000000;
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
.byte4 0x00400000;
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
.byte4 0x07C00000;
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page14*/
.byte4 0x00800000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
.byte4 0x00C00000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
.byte4 0x01000000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
.byte4 0x01400000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
.byte4 0x01800000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
.byte4 0x01C00000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
#ifndef CONFIG_EZKIT /*STAMP Memory regions*/
.byte4 0x02000000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
.byte4 0x02400000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
.byte4 0x02800000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
.byte4 0x02C00000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
.byte4 0x03000000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
.byte4 0x03400000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
#endif
.byte4 0xffffffff; /* end of section - termination*/
.align 4;
.global ipdt_table
ipdt_table:
#ifdef CONFIG_CPLB_INFO
.byte4 0x00000000;
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page0*/
.byte4 0x00400000;
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page1*/
#endif
.byte4 0x00800000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page2*/
.byte4 0x00C00000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page3*/
.byte4 0x01000000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page4*/
.byte4 0x01400000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page5*/
.byte4 0x01800000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page6*/
.byte4 0x01C00000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page7*/
#ifndef CONFIG_EZKIT /*STAMP Memory regions*/
.byte4 0x02000000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page8*/
.byte4 0x02400000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page9*/
.byte4 0x02800000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page10*/
.byte4 0x02C00000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page11*/
.byte4 0x03000000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page12*/
.byte4 0x03400000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page13*/
.byte4 0x03800000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page14*/
.byte4 0x03C00000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page15*/
#endif
.byte4 0x20200000;
.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
.byte4 0x20100000;
.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
.byte4 0x20000000;
.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
.byte4 0x20300000; /*Fix for Network*/
.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
#ifdef CONFIG_STAMP
.byte4 0x04000000;
.byte4 (SDRAM_IGENERIC);
.byte4 0x04400000;
.byte4 (SDRAM_IGENERIC);
.byte4 0x04800000;
.byte4 (SDRAM_IGENERIC);
.byte4 0x04C00000;
.byte4 (SDRAM_IGENERIC);
.byte4 0x05000000;
.byte4 (SDRAM_IGENERIC);
.byte4 0x05400000;
.byte4 (SDRAM_IGENERIC);
.byte4 0x05800000;
.byte4 (SDRAM_IGENERIC);
.byte4 0x05C00000;
.byte4 (SDRAM_IGENERIC);
.byte4 0x06000000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page25*/
.byte4 0x06400000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page26*/
.byte4 0x06800000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page27*/
.byte4 0x06C00000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page28*/
.byte4 0x07000000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page29*/
.byte4 0x07400000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page30*/
.byte4 0x07800000;
.byte4 (SDRAM_IGENERIC); /*SDRAM_Page31*/
#ifdef CONFIG_CPLB_INFO
.byte4 0x07C00000;
.byte4 (SDRAM_IKERNEL); /*SDRAM_Page32*/
#endif
#endif
.byte4 0xffffffff; /* end of section - termination*/
/*********************************************************************
* DCPLB TABLE
********************************************************************/
.global dcplb_table
dcplb_table:
.byte4 0x00000000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
.byte4 0x00400000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
.byte4 0x07C00000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page15*/
.byte4 0x00800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
.byte4 0x00C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
.byte4 0x01000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
.byte4 0x01400000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
.byte4 0x01800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
.byte4 0x01C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
#ifndef CONFIG_EZKIT
.byte4 0x02000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
.byte4 0x02400000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
.byte4 0x02800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
.byte4 0x02C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
.byte4 0x03000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
.byte4 0x03400000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
.byte4 0x03800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
#endif
.byte4 0xffffffff; /*end of section - termination*/
/**********************************************************************
* PAGE DESCRIPTOR TABLE
*
**********************************************************************/
/* Till here we are discussing about the static memory management model.
* However, the operating envoronments commonly define more CPLB
* descriptors to cover the entire addressable memory than will fit into
* the available on-chip 16 CPLB MMRs. When this happens, the below table
* will be used which will hold all the potentially required CPLB descriptors
*
* This is how Page descriptor Table is implemented in uClinux/Blackfin.
*/
.global dpdt_table
dpdt_table:
#ifdef CONFIG_CPLB_INFO
.byte4 0x00000000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page0*/
.byte4 0x00400000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page1*/
#endif
.byte4 0x00800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page2*/
.byte4 0x00C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page3*/
.byte4 0x01000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page4*/
.byte4 0x01400000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page5*/
.byte4 0x01800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page6*/
.byte4 0x01C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page7*/
#ifndef CONFIG_EZKIT
.byte4 0x02000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page8*/
.byte4 0x02400000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page9*/
.byte4 0x02800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page10*/
.byte4 0x02C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page11*/
.byte4 0x03000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page12*/
.byte4 0x03400000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page13*/
.byte4 0x03800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page14*/
.byte4 0x03C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page15*/
#endif
.byte4 0x20200000;
.byte4 (SDRAM_EBIU); /* Async Memory Bank 2 (Secnd)*/
.byte4 0x20100000;
.byte4 (SDRAM_EBIU); /* Async Memory Bank 1 (Prim B)*/
.byte4 0x20000000;
.byte4 (SDRAM_EBIU); /* Async Memory Bank 0 (Prim A)*/
.byte4 0x20300000; /*Fix for Network*/
.byte4 (SDRAM_EBIU); /*Async Memory bank 3*/
#ifdef CONFIG_STAMP
.byte4 0x04000000;
.byte4 (SDRAM_DGENERIC);
.byte4 0x04400000;
.byte4 (SDRAM_DGENERIC);
.byte4 0x04800000;
.byte4 (SDRAM_DGENERIC);
.byte4 0x04C00000;
.byte4 (SDRAM_DGENERIC);
.byte4 0x05000000;
.byte4 (SDRAM_DGENERIC);
.byte4 0x05400000;
.byte4 (SDRAM_DGENERIC);
.byte4 0x05800000;
.byte4 (SDRAM_DGENERIC);
.byte4 0x05C00000;
.byte4 (SDRAM_DGENERIC);
.byte4 0x06000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page25*/
.byte4 0x06400000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page26*/
.byte4 0x06800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page27*/
.byte4 0x06C00000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page28*/
.byte4 0x07000000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page29*/
.byte4 0x07400000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page30*/
.byte4 0x07800000;
.byte4 (SDRAM_DGENERIC); /*SDRAM_Page31*/
#ifdef CONFIG_CPLB_INFO
.byte4 0x07C00000;
.byte4 (SDRAM_DKERNEL); /*SDRAM_Page32*/
#endif
#endif
.byte4 0xFF900000;
.byte4 (L1_DMEMORY);
.byte4 0xFF901000;
.byte4 (L1_DMEMORY);
.byte4 0xFF902000;
.byte4 (L1_DMEMORY);
.byte4 0xFF903000;
.byte4 (L1_DMEMORY);
.byte4 0xFF904000;
.byte4 (L1_DMEMORY);
.byte4 0xFF905000;
.byte4 (L1_DMEMORY);
.byte4 0xFF906000;
.byte4 (L1_DMEMORY);
.byte4 0xFF907000;
.byte4 (L1_DMEMORY);
.byte4 0xFF800000;
.byte4 (L1_DMEMORY);
.byte4 0xFF801000;
.byte4 (L1_DMEMORY);
.byte4 0xFF802000;
.byte4 (L1_DMEMORY);
.byte4 0xFF803000;
.byte4 (L1_DMEMORY);
.byte4 0xffffffff; /*end of section - termination*/
#ifdef CONFIG_CPLB_INFO
.global ipdt_swapcount_table; /* swapin count first, then swapout count*/
ipdt_swapcount_table:
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 10 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 20 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 30 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 40 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 50 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 60 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 70 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 80 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 90 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 100 */
.global dpdt_swapcount_table; /* swapin count first, then swapout count*/
dpdt_swapcount_table:
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 10 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 20 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 30 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 40 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 50 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 60 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 70 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 80 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 80 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 100 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 110 */
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000;
.byte4 0x00000000; /* 120 */
#endif
#endif /*__ARCH_BFINNOMMU_CPLBTAB_H*/

32
include/asm-blackfin/cpu/cdefBF53x.h
View File

@@ -1,32 +0,0 @@
/************************************************************************
*
* cdefBF53x.h
*
* (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
*
************************************************************************/
#ifndef _CDEFBF53x_H
#define _CDEFBF53x_H
#if defined(__ADSPBF531__)
#include <asm/cpu/cdefBF531.h>
#elif defined(__ADSPBF532__)
#include <asm/cpu/cdefBF532.h>
#elif defined(__ADSPBF533__)
#include <asm/cpu/cdefBF533.h>
#elif defined(__ADSPBF561__)
#include <asm/cpu/cdefBF561.h>
#elif defined(__ADSPBF535__)
#include <asm/cpu/cdefBF535.h>
#elif defined(__AD6532__)
#include <sam/cpu/cdefAD6532.h>
#else
#if defined(__ADSPLPBLACKFIN__)
#include <asm/cpu/cdefBF532.h>
#else
#include <asm/cpu/cdefBF535.h>
#endif
#endif
#endif /* _CDEFBF53x_H */

6
include/asm-blackfin/current.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - current.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_CURRENT_H

12
include/asm-blackfin/delay.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - delay.h Routines for introducing delays
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_DELAY_H
@@ -35,9 +35,9 @@
extern __inline__ void __delay(unsigned long loops)
{
__asm__ __volatile__("1:\t%0 += -1;\n\t"
"cc = %0 == 0;\n\t"
"if ! cc jump 1b;\n":"=d"(loops)
:"0"(loops));
"cc = %0 == 0;\n\t"
"if ! cc jump 1b;\n":"=d"(loops)
:"0"(loops));
}
/*

13
include/asm-blackfin/entry.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - entry.h Routines for context saving and restoring
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __BLACKFIN_ENTRY_H
@@ -27,7 +27,6 @@
#include <linux/config.h>
#include <asm/setup.h>
#include <asm/page.h>
/*
* Stack layout in 'ret_from_exception':
@@ -370,16 +369,12 @@
#define STR1(X) #X
#if defined(NEW_PT_REGS)
#define PT_OFF_ORIG_R0 208
#define PT_OFF_SR 8
#else
#define PT_OFF_ORIG_R0 0x54
#define PT_OFF_SR 0x38 /* seqstat in pt_regs */
#endif
#endif
#endif
#endif

6
include/asm-blackfin/errno.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - errno.h Error number defines
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_ERRNO_H

19
include/asm-blackfin/global_data.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - global_data.h Declarations for global data of u-boot
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __ASM_GBL_DATA_H
@@ -45,11 +45,16 @@ typedef struct global_data {
unsigned long board_type;
unsigned long baudrate;
unsigned long have_console; /* serial_init() was called */
unsigned long ram_size; /* RAM size */
unsigned long ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
void **jt; /* jump table */
#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
unsigned long post_log_word; /* Record POST activities */
unsigned long post_init_f_time; /* When post_init_f started */
#endif
void **jt; /* jump table */
} gd_t;
/*
@@ -59,6 +64,6 @@ typedef struct global_data {
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("P5")
#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5")
#endif

16
include/asm-blackfin/hw_irq.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - hw_irq.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/hw_irq.h
@@ -24,14 +24,20 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <linux/config.h>
#ifdef CONFIG_EZKIT533
#include <asm/board/bf533_irq.h>
#include <asm/arch-bf533/irq.h>
#endif
#ifdef CONFIG_EZKIT561
#include <asm/arch-bf561/irq.h>
#endif
#ifdef CONFIG_STAMP
#include <asm/board/bf533_irq.h>
#include <asm/arch-bf533/irq.h>
#endif
#ifdef CONFIG_BF537
#include <asm/arch-bf537/irq.h>
#endif

15
include/asm-blackfin/io-kernel.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - io-kernel.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_IO_H
@@ -87,7 +87,8 @@
#define IOMAP_WRITETHROUGH 3
#ifndef __ASSEMBLY__
extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
extern void *__ioremap(unsigned long physaddr, unsigned long size,
int cacheflag);
extern void __iounmap(void *addr, unsigned long size);
extern inline void *ioremap(unsigned long physaddr, unsigned long size)
{
@@ -97,11 +98,13 @@ extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
extern inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
extern inline void *ioremap_writethrough(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
}
extern inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
extern inline void *ioremap_fullcache(unsigned long physaddr,
unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}

22
include/asm-blackfin/io.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - io.h IO routines
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,18 +18,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_IO_H
#define _BLACKFIN_IO_H
static inline void sync(void)
{
__asm__ __volatile__ asm("ssync" : : : "memory");
}
#ifdef __KERNEL__
#include <linux/config.h>
@@ -38,7 +33,12 @@ static inline void sync(void)
extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
extern unsigned char cf_inb(volatile unsigned char *addr);
extern void cf_outb(unsigned char val, volatile unsigned char* addr);
extern void cf_outb(unsigned char val, volatile unsigned char *addr);
static inline void sync(void)
{
__builtin_bfin_ssync();
}
/*
* These are for ISA/PCI shared memory _only_ and should never be used
@@ -51,7 +51,6 @@ extern void cf_outb(unsigned char val, volatile unsigned char* addr);
* memory location directly.
*/
#define readb(addr) ({ unsigned char __v = (*(volatile unsigned char *) (addr));asm("ssync;"); __v; })
#define readw(addr) ({ unsigned short __v = (*(volatile unsigned short *) (addr)); asm("ssync;");__v; })
#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr));asm("ssync;"); __v; })
@@ -100,8 +99,7 @@ extern inline void *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}
extern inline void *ioremap_nocache(unsigned long physaddr,
unsigned long size)
extern inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
}

12
include/asm-blackfin/irq.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - irq.h Interrupt related header file
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file was based on
* linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
@@ -31,15 +31,15 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_IRQ_H_
#define _BLACKFIN_IRQ_H_
#include <linux/config.h>
#include <asm/cpu/bf533_irq.h>
#include <asm/hw_irq.h>
/*
* On the Blackfin, the interrupt structure allows remmapping of the hardware
@@ -85,8 +85,8 @@ static __inline__ int irq_cannonicalize(int irq)
extern void (*mach_enable_irq) (unsigned int);
extern void (*mach_disable_irq) (unsigned int);
extern int sys_request_irq(unsigned int,
void (*)(int, void *, struct pt_regs *),
unsigned long, const char *, void *);
void (*)(int, void *, struct pt_regs *),
unsigned long, const char *, void *);
extern void sys_free_irq(unsigned int, void *);
/*

6
include/asm-blackfin/linkage.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - linkage.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _LINUX_LINKAGE_H

9
include/asm-blackfin/machdep.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - machdep.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_MACHDEP_H
@@ -39,7 +39,8 @@ struct hwclk_time;
struct gendisk;
struct buffer_head;
extern void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *));
extern
void (*mach_sched_init) (void (*handler) (int, void *, struct pt_regs *));
/* machine dependent keyboard functions */
extern int (*mach_keyb_init) (void);

52
include/asm-blackfin/mem_init.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - mem_init.h Header file for memory initialization
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,11 +18,17 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E )
#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
CONFIG_MEM_MT48LC64M4A2FB_7E || \
CONFIG_MEM_MT48LC16M8A2TG_75 || \
CONFIG_MEM_MT48LC8M16A2TG_7E || \
CONFIG_MEM_MT48LC8M32B2B5_7 || \
CONFIG_MEM_MT48LC32M8A2_75)
#if ( CONFIG_SCLK_HZ > 119402985 )
#define SDRAM_tRP TRP_2
#define SDRAM_tRP_num 2
@@ -66,7 +72,7 @@
#if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
#define SDRAM_tRP TRP_1
#define SDRAM_tRP_num 1
#define SDRAM_tRAS TRAS_4
#define SDRAM_tRAS TRAS_3
#define SDRAM_tRAS_num 3
#define SDRAM_tRCD TRCD_1
#define SDRAM_tWR TWR_2
@@ -99,18 +105,46 @@
#if (CONFIG_MEM_MT48LC16M16A2TG_75)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_2
#endif
#if (CONFIG_MEM_MT48LC16M8A2TG_75)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC32M8A2_75)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_2
#endif
#if (CONFIG_MEM_MT48LC8M32B2B5_7)
/*SDRAM INFORMATION: */
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
#define SDRAM_CL CL_3
#endif
#if ( CONFIG_MEM_SIZE == 128 )
#define SDRAM_SIZE EBSZ_128
#endif

128
include/asm-blackfin/page.h
View File

@@ -1,128 +0,0 @@
/*
* U-boot - page.h
*
* Copyright (c) 2005 blackfin.uclinux.org
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _BLACKFIN_PAGE_H
#define _BLACKFIN_PAGE_H
#include <linux/config.h>
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT (12)
#define PAGE_SIZE (4096)
#define PAGE_MASK (~(PAGE_SIZE-1))
#ifdef __KERNEL__
#include <asm/setup.h>
#if PAGE_SHIFT < 13
#define KTHREAD_SIZE (8192)
#else
#define KTHREAD_SIZE PAGE_SIZE
#endif
#ifndef __ASSEMBLY__
#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
#define free_user_page(page, addr) free_page(addr)
#define clear_page(page) memset((page), 0, PAGE_SIZE)
#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE)
#define clear_user_page(page, vaddr) clear_page(page)
#define copy_user_page(to, from, vaddr) copy_page(to, from)
/*
* These are used to make use of C type-checking..
*/
typedef struct {
unsigned long pte;
} pte_t;
typedef struct {
unsigned long pmd[16];
} pmd_t;
typedef struct {
unsigned long pgd;
} pgd_t;
typedef struct {
unsigned long pgprot;
} pgprot_t;
#define pte_val(x) ((x).pte)
#define pmd_val(x) ((&x)->pmd[0])
#define pgd_val(x) ((x).pgd)
#define pgprot_val(x) ((x).pgprot)
#define __pte(x) ((pte_t) { (x) } )
#define __pmd(x) ((pmd_t) { (x) } )
#define __pgd(x) ((pgd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
/* Pure 2^n version of get_order */
extern __inline__ int get_order(unsigned long size)
{
int order;
size = (size - 1) >> (PAGE_SHIFT - 1);
order = -1;
do {
size >>= 1;
order++;
} while (size);
return order;
}
#endif /* !__ASSEMBLY__ */
#include <asm/page_offset.h>
#define PAGE_OFFSET (PAGE_OFFSET_RAW)
#ifndef __ASSEMBLY__
#define __pa(vaddr) virt_to_phys((void *)vaddr)
#define __va(paddr) phys_to_virt((unsigned long)paddr)
#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
#define BUG() do { \
\
while (1); /* dead-loop */ \
} while (0)
#define PAGE_BUG(page) do { \
BUG(); \
} while (0)
#endif
#endif
#endif

6
include/asm-blackfin/page_offset.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - page_offset.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/*

6
include/asm-blackfin/posix_types.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - posix_types.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __ARCH_BLACKFIN_POSIX_TYPES_H

9
include/asm-blackfin/processor.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - processor.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* include/asm-m68k/processor.h
@@ -23,8 +23,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __ASM_BLACKFIN_PROCESSOR_H
@@ -126,8 +126,7 @@ static inline void release_thread(struct task_struct *dead_task)
{
}
extern int kernel_thread(int (*fn) (void *), void *arg,
unsigned long flags);
extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
#define copy_segments(tsk, mm) do { } while (0)
#define release_segments(mm) do { } while (0)

6
include/asm-blackfin/ptrace.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - ptrace.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_PTRACE_H

6
include/asm-blackfin/segment.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - segment.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_SEGMENT_H

9
include/asm-blackfin/setup.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - setup.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* asm/setup.h -- Definition of the Linux/Blackfin setup information
@@ -22,8 +22,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_SETUP_H
@@ -75,12 +75,13 @@ extern unsigned long vme_brdtype;
extern int blackfin_num_memory; /* # of memory blocks found (and used) */
extern int blackfin_realnum_memory; /* real # of memory blocks found */
extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */
struct mem_info {
unsigned long addr; /* physical address of memory chunk */
unsigned long size; /* length of memory chunk (in bytes) */
};
extern struct mem_info blackfin_memory[NUM_MEMINFO]; /* memory description */
#endif
#endif

6
include/asm-blackfin/shared_resources.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - setup.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _SHARED_RESOURCES_H_

16
include/asm-blackfin/string.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - string.h String functions
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* Changed by Lineo Inc. May 2001 */
@@ -30,22 +30,26 @@
#ifdef __KERNEL__ /* only set these up for kernel code */
#include <asm/setup.h>
#include <asm/page.h>
#include <asm/cpu/defBF533.h>
#include <config.h>
#include <asm/blackfin.h>
#define __HAVE_ARCH_STRCPY
#define __HAVE_ARCH_STRNCPY
#define __HAVE_ARCH_STRCMP
#define __HAVE_ARCH_STRNCMP
#define __HAVE_ARCH_MEMCPY
#define __HAVE_ARCH_MEMCMP
#define __HAVE_ARCH_MEMSET
#define __HAVE_ARCH_MEMMOVE
extern char *strcpy(char *dest, const char *src);
extern char *strncpy(char *dest, const char *src, size_t n);
extern int strcmp(const char *cs, const char *ct);
extern int strncmp(const char *cs, const char *ct, size_t count);
extern void * memcpy(void * dest,const void *src,size_t count);
extern void *memcpy(void *dest, const void *src, size_t count);
extern void *memset(void *s, int c, size_t count);
extern int memcmp(const void *, const void *, __kernel_size_t);
extern void *memmove(void *dest, const void *src, size_t count);
#else /* KERNEL */

6
include/asm-blackfin/system.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - system.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_SYSTEM_H

6
include/asm-blackfin/traps.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - traps.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* linux/include/asm/traps.h
@@ -23,8 +23,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/*

6
include/asm-blackfin/types.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - types.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_TYPES_H

6
include/asm-blackfin/u-boot.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - u-boot.h Structure declarations for board specific data
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -21,8 +21,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _U_BOOT_H_

16
include/asm-blackfin/uaccess.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - uaccess.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* This file is based on
* Based on: include/asm-m68knommu/uaccess.h
@@ -22,8 +22,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __BLACKFIN_UACCESS_H
@@ -41,11 +41,10 @@
/* We let the MMU do all checking */
static inline int access_ok(int type, const void *addr, unsigned long size)
{
return ((unsigned long) addr < 0x10f00000); /* need final decision - Tony */
return ((unsigned long)addr < 0x10f00000); /* need final decision - Tony */
}
static inline int verify_area(int type, const void *addr,
unsigned long size)
static inline int verify_area(int type, const void *addr, unsigned long size)
{
return access_ok(type, addr, size) ? 0 : -EFAULT;
}
@@ -173,12 +172,11 @@ static inline int bad_user_access_length(void)
* Copy a null terminated string from userspace.
*/
static inline long strncpy_from_user(char *dst, const char *src,
long count)
static inline long strncpy_from_user(char *dst, const char *src, long count)
{
char *tmp;
strncpy(dst, src, count);
for (tmp = dst; *tmp && count > 0; tmp++, count--);
for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
return (tmp - dst); /* DAVIDM should we count a NUL ? check getname */
}

7
include/asm-blackfin/virtconvert.h
View File

@@ -1,7 +1,7 @@
/*
* U-boot - virtconvert.h
*
* Copyright (c) 2005 blackfin.uclinux.org
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -18,8 +18,8 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __BLACKFIN_VIRT_CONVERT__
@@ -33,7 +33,6 @@
#include <linux/config.h>
#include <asm/setup.h>
#include <asm/page.h>
#define mm_vtop(vaddr) ((unsigned long) vaddr)
#define mm_ptov(vaddr) ((unsigned long) vaddr)

1
include/asm-microblaze/microblaze_timer.h
View File

@@ -39,4 +39,3 @@ typedef volatile struct microblaze_timer_t {
int loadreg; /* load register TLR */
int counter; /* timer/counter register */
} microblaze_timer_t;

5
include/asm-ppc/e300.h
View File

@@ -15,6 +15,11 @@
#define PVR_8360_REV10 (PVR_83xx | 0x0020)
#define PVR_8360_REV11 (PVR_83xx | 0x0020)
#if defined(CONFIG_MPC832X)
#undef PVR_83xx
#define PVR_83xx 0x80840000
#endif
/*
* Hardware Implementation-Dependent Register 0 (HID0)
*/

7
include/asm-ppc/global_data.h
View File

@@ -49,15 +49,18 @@ typedef struct global_data {
unsigned long scc_clk;
unsigned long brg_clk;
#endif
#if defined(CONFIG_MPC7448HPC2)
unsigned long mem_clk;
#endif
#if defined(CONFIG_MPC83XX)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
#if defined (CONFIG_MPC8349)
#if defined (CONFIG_MPC834X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbmph_clk;
u32 usbdr_clk;
#endif /* CONFIG_MPC8349 */
#endif /* CONFIG_MPC834X */
u32 core_clk;
u32 i2c1_clk;
u32 i2c2_clk;

56
include/asm-ppc/gpio.h Normal file
View File

@@ -0,0 +1,56 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define GPIO_GROUP_MAX 2
#else
#define GPIO_GROUP_MAX 1
#endif
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000
#define GPIO_ALT2_SEL 0x80000000
#define GPIO_ALT3_SEL 0xc0000000
#define GPIO_IN_SEL 0x40000000
#define GPIO_MASK 0xc0000000
#define GPIO_VAL(gpio) (0x80000000 >> (gpio))
#ifndef __ASSEMBLY__
typedef enum gpio_select { GPIO_SEL, GPIO_ALT1, GPIO_ALT2, GPIO_ALT3 } gpio_select_t;
typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
typedef struct {
unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
} gpio_param_s;
#endif
void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val);
void gpio_set_chip_configuration(void);

1962
include/asm-ppc/immap_83xx.h
View File

File diff suppressed because it is too large Load Diff

2
include/asm-ppc/immap_86xx.h
View File

@@ -721,6 +721,8 @@ typedef struct ccsr_pic {
uint frr; /* 0x41000 - Feature Reporting Register */
char res10[28];
uint gcr; /* 0x41020 - Global Configuration Register */
#define MPC86xx_PICGCR_RST 0x80000000
#define MPC86xx_PICGCR_MODE 0x20000000
char res11[92];
uint vir; /* 0x41080 - Vendor Identification Register */
char res12[12];

6
include/asm-ppc/immap_qe.h
View File

@@ -547,4 +547,10 @@ typedef struct qe_immap {
extern qe_map_t *qe_immr;
#if defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832X)
#define QE_MURAM_SIZE 0x4000UL
#endif
#endif /* __IMMAP_QE_H__ */

5
include/asm-ppc/mmu.h
View File

@@ -396,8 +396,8 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define BOOKE_PAGESZ_16M 7
#define BOOKE_PAGESZ_64M 8
#define BOOKE_PAGESZ_256M 9
#define BOOKE_PAGESZ_1GB 10
#define BOOKE_PAGESZ_4GB 11
#define BOOKE_PAGESZ_1G 10
#define BOOKE_PAGESZ_4G 11
#if defined(CONFIG_MPC86xx)
#define LAWBAR_BASE_ADDR 0x00FFFFFF
@@ -413,6 +413,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
#define LAWAR_TRGT_IF_PEX 0x00200000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000

29
include/asm-ppc/processor.h
View File

@@ -232,6 +232,9 @@
#define HID0_BHTE (1<<2) /* Branch History Table Enable */
#define HID0_BTCD (1<<1) /* Branch target cache disable */
#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
#define HID1_ASTME (1<<13) /* Address bus streaming mode */
#define HID1_ABE (1<<12) /* Address broadcast enable */
#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
#ifndef CONFIG_BOOKE
#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
@@ -298,6 +301,10 @@
#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
@@ -411,10 +418,12 @@
#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
/* e500 definitions */
#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
@@ -529,6 +538,10 @@
#define SPRG1 SPRN_SPRG1
#define SPRG2 SPRN_SPRG2
#define SPRG3 SPRN_SPRG3
#define SPRG4 SPRN_SPRG4
#define SPRG5 SPRN_SPRG5
#define SPRG6 SPRN_SPRG6
#define SPRG7 SPRN_SPRG7
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
#define SVR SPRN_SVR /* System Version Register */
@@ -693,8 +706,6 @@
#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
/* System-On-Chip Version Numbers (version field only) */
#define SVR_MPC5200 0x8011
/* Processor Version Register */
@@ -731,6 +742,7 @@
#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */
#define PVR_405EP_RA 0x51210950
#define PVR_405GPR_RB 0x50910951
#define PVR_405EZ_RA 0x41511460
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850
@@ -804,6 +816,12 @@
#define PVR_8260_HIP7R1 0x80822013
#define PVR_8260_HIP7RA 0x80822014
/*
* MPC 52xx
*/
#define PVR_5200 0x80822011
#define PVR_5200B 0x80822014
/*
* System Version Register
@@ -831,9 +849,12 @@
#define SVR_8560 0x8070
#define SVR_8555 0x8079
#define SVR_8541 0x807A
#define SVR_8544 0x8034
#define SVR_8544_E 0x803C
#define SVR_8548 0x8031
#define SVR_8548_E 0x8039
#define SVR_8641 0x8090
#define SVR_8568_E 0x807D
/* I am just adding a single entry for 8260 boards. I think we may be

4
include/asm-ppc/u-boot.h
View File

@@ -83,6 +83,7 @@ typedef struct bd_info {
defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_440)
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
@@ -107,7 +108,8 @@ typedef struct bd_info {
unsigned char bi_enet3addr[6];
#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
unsigned int bi_opbfreq; /* OPB clock in Hz */

2
include/configs/IceCube.h
View File

@@ -182,7 +182,7 @@
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
/*

631
include/configs/MPC832XEMDS.h Normal file
View File

@@ -0,0 +1,631 @@
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_QE 1 /* Has QE */
#define CONFIG_MPC83XX 1 /* MPC83xx family */
#define CONFIG_MPC832X 1 /* MPC832x CPU specific */
#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
/*
* System Clock Setup
*/
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
#else
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ 66000000
#endif
/*
* Hardware Reset Configuration Word
*/
#define CFG_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_2X1 |\
HRCWL_VCO_1X2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_2X1 |\
HRCWL_CE_PLL_VCO_DIV_2 |\
HRCWL_CE_PLL_DIV_1X1 |\
HRCWL_CE_TO_PLL_1X3)
#ifdef CONFIG_PCISLAVE
#define CFG_HRCW_HIGH (\
HRCWH_PCI_AGENT |\
HRCWH_PCI1_ARBITER_DISABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#else
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#endif
/*
* System IO Config
*/
#define CFG_SICRL 0x00000000
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
/*
* IMMR new address
*/
#define CFG_IMMR 0xE0000000
/*
* DDR Setup
*/
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
/* Determine DDR configuration from I2C interface
*/
#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
#else
/* Manually set up DDR parameters
*/
#define CFG_DDR_SIZE 128 /* MB */
#define CFG_DDR_CS0_CONFIG 0x80840102
#define CFG_DDR_TIMING_0 0x00220802
#define CFG_DDR_TIMING_1 0x3935d322
#define CFG_DDR_TIMING_2 0x0f9048ca
#define CFG_DDR_TIMING_3 0x00000000
#define CFG_DDR_CLK_CNTL 0x02000000
#define CFG_DDR_MODE 0x44400232
#define CFG_DDR_MODE2 0x8000c000
#define CFG_DDR_INTERVAL 0x03200064
#define CFG_DDR_CS0_BNDS 0x00000007
#define CFG_DDR_SDRAM_CFG 0x43080000
#define CFG_DDR_SDRAM_CFG2 0x00401000
#endif
/*
* Memory test
*/
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x00100000
/*
* The reserved memory
*/
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup
*/
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
#define CFG_LBC_LBCR 0x00000000
/*
* FLASH on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
/*
* BCSR on the Local Bus
*/
#define CFG_BCSR 0xF8000000
#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
/*
* SDRAM on the Local Bus
*/
#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */
#ifdef CFG_LB_SDRAM
#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */
/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
/*
* Base Register 2 and Option Register 2 configure SDRAM.
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR2, need:
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
* port size = 32-bits = BR2[19:20] = 11
* no parity checking = BR2[21:22] = 00
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* CFG_LBC_SDRAM_BASE should be masked and OR'ed into
* the top 17 bits of BR2.
*/
#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */
/*
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
*
* For OR2, need:
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
* 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CFG_OR2_PRELIM 0xfc006901
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
/*
* LSDMR masks
*/
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CFG_LBC_LSDMR_COMMON 0x0063b723
/*
* SDRAM Controller configuration sequence.
*/
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_NORMAL)
#endif
/*
* Windows to access PIB via local bus
*/
#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
/*
* CS2 on Local Bus, to PIB
*/
#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */
#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* CS3 on Local Bus, to PIB
*/
#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */
#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8323@0"
#define OF_SOC "soc8323@e0000000"
#define OF_QE "qe@e0100000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500"
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/*
* Config on-board RTC
*/
#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CFG_PCI_MEM_BASE 0x80000000
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI_MMIO_BASE 0x90000000
#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
#define CFG_PCI_IO_BASE 0xE0300000
#define CFG_PCI_IO_PHYS 0xE0300000
#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
#define CFG_PCI_SLV_MEM_BUS 0x00000000
#define CFG_PCI_SLV_MEM_SIZE 0x80000000
#ifdef CONFIG_PCI
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "Freescale GETH"
#define CONFIG_UEC_ETH1 /* ETH3 */
#ifdef CONFIG_UEC_ETH1
#define CFG_UEC1_UCC_NUM 2 /* UCC3 */
#define CFG_UEC1_RX_CLK QE_CLK9
#define CFG_UEC1_TX_CLK QE_CLK10
#define CFG_UEC1_ETH_TYPE FAST_ETH
#define CFG_UEC1_PHY_ADDR 3
#define CFG_UEC1_INTERFACE_MODE ENET_100_MII
#endif
#define CONFIG_UEC_ETH2 /* ETH4 */
#ifdef CONFIG_UEC_ETH2
#define CFG_UEC2_UCC_NUM 3 /* UCC4 */
#define CFG_UEC2_RX_CLK QE_CLK7
#define CFG_UEC2_TX_CLK QE_CLK8
#define CFG_UEC2_ETH_TYPE FAST_ETH
#define CFG_UEC2_PHY_ADDR 4
#define CFG_UEC2_INTERFACE_MODE ENET_100_MII
#endif
/*
* Environment
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_PCI \
| CFG_CMD_I2C) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_LOADS))
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_LOADS))
#endif
#else
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PCI \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C)
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C )
#endif
#endif
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
#define CFG_HID2 HID2_HBE
/*
* Cache Config
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
#endif
/*
* MMU Setup
*/
/* DDR: cache cacheable */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U
/* BCSR: cache-inhibit and guarded */
#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U CFG_IBAT3U
#define CFG_IBAT4L (0)
#define CFG_IBAT4U (0)
#define CFG_DBAT4L CFG_IBAT4L
#define CFG_DBAT4U CFG_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */
#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT5L CFG_IBAT5L
#define CFG_DBAT5U CFG_IBAT5U
#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT6L CFG_IBAT6L
#define CFG_DBAT6U CFG_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT7L CFG_IBAT7L
#define CFG_DBAT7U CFG_IBAT7U
#else
#define CFG_IBAT6L (0)
#define CFG_IBAT6U (0)
#define CFG_IBAT7L (0)
#define CFG_IBAT7U (0)
#define CFG_DBAT6L CFG_IBAT6L
#define CFG_DBAT6U CFG_IBAT6U
#define CFG_DBAT7L CFG_IBAT7L
#define CFG_DBAT7U CFG_IBAT7U
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_UEC_ETH)
#define CONFIG_ETHADDR 00:04:9f:ef:03:01
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=400000\0" \
"fdtfile=mpc832xemds.dtb\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */

56
include/configs/MPC8349EMDS.h
View File

@@ -60,17 +60,6 @@
#endif
#endif
#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK))
#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */
#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */
#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */
#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */
#define CFG_SCCR_VAL ( CFG_SCCR_INIT \
| CFG_SCCR_TSEC1CM \
| CFG_SCCR_TSEC2CM \
| CFG_SCCR_ENCCM \
| CFG_SCCR_USBCM )
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CFG_IMMR 0xE0000000
@@ -82,7 +71,7 @@
/*
* DDR Setup
*/
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_ECC /* support DDR ECC function */
#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
@@ -101,8 +90,15 @@
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#undef CONFIG_DDR_2T_TIMING
/*
* DDRCDR - DDR Control Driver Register
*/
#define CFG_DDRCDR_VALUE 0x80080001
#if defined(CONFIG_SPD_EEPROM)
/*
* Determine DDR configuration from I2C interface.
@@ -113,6 +109,21 @@
* Manually set up DDR parameters
*/
#define CFG_DDR_SIZE 256 /* MB */
#if defined(CONFIG_DDR_II)
#define CFG_DDRCDR 0x80080001
#define CFG_DDR_CS2_BNDS 0x0000000f
#define CFG_DDR_CS2_CONFIG 0x80330102
#define CFG_DDR_TIMING_0 0x00220802
#define CFG_DDR_TIMING_1 0x38357322
#define CFG_DDR_TIMING_2 0x2f9048c8
#define CFG_DDR_TIMING_3 0x00000000
#define CFG_DDR_CLK_CNTL 0x02000000
#define CFG_DDR_MODE 0x47d00432
#define CFG_DDR_MODE2 0x8000c000
#define CFG_DDR_INTERVAL 0x03cf0080
#define CFG_DDR_SDRAM_CFG 0x43000000
#define CFG_DDR_SDRAM_CFG2 0x00401000
#else
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
#define CFG_DDR_TIMING_1 0x36332321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
@@ -127,6 +138,7 @@
#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */
#endif
#endif
#endif
/*
* SDRAM on the Local Bus
@@ -140,19 +152,20 @@
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_SIZE 8 /* flash size in MB */
#define CFG_FLASH_SIZE 32 /* max flash size in MB */
/* #define CFG_FLASH_USE_BUFFER_WRITE */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
(2 << BR_PS_SHIFT) | /* 32 bit port size */ \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
@@ -197,7 +210,11 @@
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
#define CFG_LBC_LBCR 0x00000000
#define CFG_LB_SDRAM /* if board has SRDAM on local bus */
/*
* The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
* if board has SRDAM on local bus, you can define CFG_LB_SDRAM
*/
#undef CFG_LB_SDRAM
#ifdef CFG_LB_SDRAM
/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
@@ -314,6 +331,7 @@
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER

517
include/configs/MPC8349ITX.h
View File

@@ -21,7 +21,7 @@
*/
/*
MPC8349E-mITX board configuration file
MPC8349E-mITX and MPC8349E-mITX-GP board configuration file
Memory map:
@@ -31,11 +31,11 @@
0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
0xF000_0000-0xF000_FFFF Compact Flash
0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
0xF001_0000-0xF001_FFFF Local bus expansion slot
0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385
0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB)
0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB)
0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
I2C address list:
Align. Board
@@ -56,7 +56,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
#if (TEXT_BASE == 0xFE000000)
#define CFG_LOWBOOT
#endif
/*
* High Level Configuration Options
@@ -64,14 +66,26 @@
#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */
#define CONFIG_MPC8349 /* MPC8349 specific */
#define CONFIG_PCI
#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */
/* On-board devices */
#ifdef CONFIG_MPC8349ITX
#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */
#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */
#endif
#define CONFIG_PCI
#define CONFIG_RTC_DS1337
#define CONFIG_HARD_I2C
#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
/*
* Device configurations
*/
/* I2C */
#define CONFIG_HARD_I2C
#ifdef CONFIG_HARD_I2C
#define CONFIG_MISC_INIT_F
@@ -111,120 +125,9 @@
#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define PCI_66M
#ifdef PCI_66M
#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
#else
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
#endif
#ifndef CONFIG_SYS_CLK_FREQ
#ifdef PCI_66M
#define CONFIG_SYS_CLK_FREQ 66666666
#else
#define CONFIG_SYS_CLK_FREQ 33333333
#endif
#endif
#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00003000 /* memtest region */
#define CFG_MEMTEST_END 0x07100000 /* only has 128M */
/*
* DDR Setup
*/
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
* 32-bit data path mode.
*
* Please note that using this mode for devices with the real density of 64-bit
* effectively reduces the amount of available memory due to the effect of
* wrapping around while translating address to row/columns, for example in the
* 256MB module the upper 128MB get aliased with contents of the lower
* 128MB); normally this define should be used for devices with real 32-bit
* data path.
*/
#undef CONFIG_DDR_32BIT
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#undef CONFIG_DDR_2T_TIMING
#define CFG_83XX_DDR_USES_CS0
#ifndef CONFIG_SPD_EEPROM
/*
* Manually set up DDR parameters
*/
#define CFG_DDR_SIZE 256 /* Mb */
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
#define CFG_DDR_TIMING_1 0x26242321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
#endif
/* FLASH on the Local Bus */
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
#define CFG_FLASH_EMPTY_INFO
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */
/* VSC7385 on the Local Bus */
#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */
#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \
OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */
#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 135 /* sectors per device */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */
#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V)
#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \
OR_GPCM_SCY_9 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH
#define CFG_CF_BASE 0xF0000000
#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */
#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */
#undef CONFIG_IDE_RESET
#undef CONFIG_IDE_PREINIT
#define CFG_IDE_MAXBUS 1
#define CFG_IDE_MAXDEVICE 1
@@ -237,13 +140,108 @@
#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */
#endif
#define CONFIG_DOS_PARTITION
#define CFG_MID_FLASH_JUMP 0x7F000000
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#endif
/*
* DDR Setup
*/
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#define CFG_83XX_DDR_USES_CS0
#define CFG_MEMTEST_START 0x1000 /* memtest region */
#define CFG_MEMTEST_END 0x2000
#ifdef CONFIG_HARD_I2C
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
#endif
#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */
#define CFG_DDR_SIZE 256 /* Mb */
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
#define CFG_DDR_TIMING_1 0x26242321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
#endif
/*
*Flash on the Local Bus
*/
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CFG_FLASH_EMPTY_INFO
#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* The ITX has two flash chips, but the ITX-GP has only one. To support both
boards, we say we have two, but don't display a message if we find only one. */
#define CFG_FLASH_QUIET_TEST
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000}
#define CFG_FLASH_SIZE 16 /* FLASH size in MB */
#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */
/*
* BRx, ORx, LBLAWBARx, and LBLAWARx
*/
/* Flash */
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385
#define CFG_VSC7385_BASE 0xF8000000
#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V)
#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE
#define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
#endif
/* LED */
#define CFG_LED_BASE 0xF9000000
#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V)
#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
OR_GPCM_EHTR | OR_GPCM_EAD)
/* Compact Flash */
#ifdef CONFIG_COMPACT_FLASH
#define CFG_CF_BASE 0xF0000000
#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
#define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE
#define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
#endif
/*
* U-Boot memory configuration
*/
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
@@ -253,10 +251,10 @@
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK
#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -272,97 +270,9 @@
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
#define CFG_LBC_LBCR 0x00000000
#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */
#ifdef CFG_LB_SDRAM
/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/
/*
* Base Register 2 and Option Register 2 configure SDRAM.
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
*
* For BR2, need:
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
* port-size = 32-bits = BR2[19:20] = 11
* no parity checking = BR2[21:22] = 00
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
*/
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CFG_LBLAWBAR2_PRELIM 0xF0000000
#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */
#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V)
#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \
OR_SDRAM_XAM | \
((9 - 7) << OR_SDRAM_COLS_SHIFT) | \
((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \
OR_SDRAM_EAD)
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/
/*
* LSDMR masks
*/
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27))
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
| CFG_LBC_LSDMR_BSMA1516 \
| CFG_LBC_LSDMR_RFCR8 \
| CFG_LBC_LSDMR_PRETOACT6 \
| CFG_LBC_LSDMR_ACTTORW3 \
| CFG_LBC_LSDMR_BL8 \
| CFG_LBC_LSDMR_WRC3 \
| CFG_LBC_LSDMR_CL3 \
)
/*
* SDRAM Controller configuration sequence.
*/
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_NORMAL)
#endif
/*
* Serial Port
*/
@@ -374,20 +284,16 @@
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_BAUDRATE 115200
#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_FLAT_TREE
#define CONFIG_OF_BOARD_SETUP
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
@@ -397,6 +303,9 @@
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500"
/*
* PCI
*/
#ifdef CONFIG_PCI
#define CONFIG_MPC83XX_PCI2
@@ -447,14 +356,18 @@
#endif
#define PCI_66M
#ifdef PCI_66M
#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
#else
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
#endif
/* TSEC */
#ifdef CONFIG_TSEC_ENET
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI
#endif
#define CONFIG_MII
#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
@@ -468,6 +381,7 @@
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CFG_TSEC2_OFFSET 0x25000
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
@@ -479,14 +393,15 @@
#endif
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE))
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH /* Flash is not usable now */
@@ -533,16 +448,23 @@
/* Watchdog */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_WATCHDOG
#define CFG_WATCHDOG_VALUE 0xFFFFFFC3
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_HUSH_PARSER /* Use the HUSH parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#ifdef CONFIG_MPC8349ITX
#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
#else
#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
@@ -562,15 +484,15 @@
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
/*
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */
#endif
#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CFG_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
HRCWL_DDR_TO_SCB_CLK_1X1 |\
@@ -578,12 +500,12 @@
HRCWL_VCO_1X2 |\
HRCWL_CORE_TO_CSB_2X1)
#ifdef PCI_64BIT
#ifdef CFG_LOWBOOT
#define CFG_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_64_BIT_PCI |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_PCI2_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
@@ -596,7 +518,7 @@
HRCWH_PCI_HOST |\
HRCWH_32_BIT_PCI |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_PCI2_ARBITER_DISABLE |\
HRCWH_PCI2_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_BOOTSEQ_DISABLE |\
@@ -606,30 +528,32 @@
HRCWH_TSEC2M_IN_GMII )
#endif
/* System performance */
/*
* System performance
*/
#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */
/* System IO Config */
/*
* System IO Config
*/
#define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */
#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
/* DDR @ 0x00000000 */
/* DDR */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
/* PCI @ 0x80000000 */
/* PCI */
#ifdef CONFIG_PCI
#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
@@ -706,97 +630,72 @@
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
#endif
#if 1
#define CONFIG_IPADDR 10.82.19.159
#define CONFIG_SERVERIP 10.82.48.106
#define CONFIG_GATEWAYIP 10.82.19.254
#define CONFIG_NETMASK 255.255.252.0
#define CONFIG_NETDEV eth0
#define CONFIG_HOSTNAME mpc8349emitx
#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs
#define CONFIG_BOOTFILE timur/uImage
#define CONFIG_UBOOTPATH timur/u-boot.bin
#else
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.252.0
#define CONFIG_NETDEV eth0
#ifdef CONFIG_MPC8349ITX
#define CONFIG_HOSTNAME mpc8349emitx
#else
#define CONFIG_HOSTNAME mpc8349emitxgp
#endif
/* Default path and filenames */
#define CONFIG_ROOTPATH /nfsroot/rootfs
#define CONFIG_BOOTFILE uImage
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH u-boot.bin
#endif
#define CONFIG_UBOOTSTART fe700000
#define CONFIG_UBOOTEND fe77ffff
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BAUDRATE 115200
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTDELAY 6
#ifdef CONFIG_MPC8349ITX
#define CONFIG_FDTFILE mpc8349emitx.dtb
#else
#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
#define CONFIG_FDTFILE mpc8349emitxgp.dtb
#endif
#define CONFIG_BOOTDELAY 0
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
#define CONFIG_BOOTARGS \
"root=/dev/nfs rw" \
" nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \
" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
" ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
" console=ttyS0," MK_STR(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
"erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
"cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \
"cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \
"tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
"protect off FEF00000 FEF7FFFF; " \
"erase FEF00000 FEF7FFFF; " \
"cp.b $loadaddr FEF00000 $filesize; " \
"protect on FEF00000 FEF7FFFF; " \
"cmp.b $loadaddr FEF00000 $filesize\0" \
"tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \
"copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
"cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"fdtaddr=400000\0" \
"fdtfile=mpc8349emitx.dtb\0" \
""
"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \
" ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
" console=$console,$baudrate $othbootargs; " \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
"setenv bootargs root=/dev/ram rw" \
" console=$console,$baudrate $othbootargs; " \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#undef MK_STR
#undef XMK_STR

49
include/configs/MPC8360EMDS.h
View File

@@ -100,12 +100,19 @@
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_83XX_DDR_USES_CS0
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_DDR_ECC /* support DDR ECC function */
#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
/*
* DDRCDR - DDR Control Driver Register
*/
#define CFG_DDRCDR_VALUE 0x80080001
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#if defined(CONFIG_SPD_EEPROM)
/*
@@ -117,6 +124,21 @@
* Manually set up DDR parameters
*/
#define CFG_DDR_SIZE 256 /* MB */
#if defined(CONFIG_DDR_II)
#define CFG_DDRCDR 0x80080001
#define CFG_DDR_CS0_BNDS 0x0000000f
#define CFG_DDR_CS0_CONFIG 0x80330102
#define CFG_DDR_TIMING_0 0x00220802
#define CFG_DDR_TIMING_1 0x38357322
#define CFG_DDR_TIMING_2 0x2f9048c8
#define CFG_DDR_TIMING_3 0x00000000
#define CFG_DDR_CLK_CNTL 0x02000000
#define CFG_DDR_MODE 0x47d00432
#define CFG_DDR_MODE2 0x8000c000
#define CFG_DDR_INTERVAL 0x03cf0080
#define CFG_DDR_SDRAM_CFG 0x43000000
#define CFG_DDR_SDRAM_CFG2 0x00401000
#else
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */
@@ -124,6 +146,7 @@
#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */
#endif
#endif
/*
* Memory test
@@ -168,7 +191,7 @@
#define CFG_FLASH_CFI /* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */
#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
@@ -176,10 +199,12 @@
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V) /* valid */
#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */
#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
#undef CFG_FLASH_CHECKSUM
@@ -188,7 +213,7 @@
*/
#define CFG_BCSR 0xF8000000
#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
#define CFG_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
@@ -278,8 +303,8 @@
/*
* Windows to access PIB via local bus
*/
#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */
#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */
#define CFG_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
#define CFG_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
/*
* CS4 on Local Bus, to PIB
@@ -309,6 +334,7 @@
#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
@@ -316,14 +342,19 @@
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_LIBFDT 1
#undef CONFIG_OF_FLAT_TREE
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_HAS_BD_T 1
#define CONFIG_OF_HAS_UBOOT_ENV 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8360@0"
#define OF_SOC "soc8360@e0000000"
#define OF_QE "qe@e0100000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500"
@@ -609,7 +640,7 @@
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=400000\0" \
"fdtfile=mpc8349emds.dtb\0" \
"fdtfile=mpc8360emds.dtb\0" \
""
#define CONFIG_NFSBOOTCOMMAND \

5
include/configs/MPC8540ADS.h
View File

@@ -330,13 +330,12 @@
/*
* General PCI
* Addresses are mapped 1-1.
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x0
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */

2
include/configs/MPC8541CDS.h
View File

@@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void);
/*
* General PCI
* Addresses are mapped 1-1.
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE

591
include/configs/MPC8544DS.h Normal file
View File

@@ -0,0 +1,591 @@
/*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mpc8544ds board configuration file
*
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_MPC8544 1
#define CONFIG_MPC8544DS 1
#undef CONFIG_PCI /* Enable PCI/PCIE */
#undef CONFIG_PCI1 /* PCI controller 1 */
#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_DLL
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_DDR_ECC_CMD
/*
* When initializing flash, if we cannot find the manufacturer ID,
* assume this is the AMD flash associated with the CDS board.
* This allows booting from a promjet.
*/
#define CONFIG_ASSUME_AMD_FLASH
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
#define CFG_ALT_MEMTEST
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000)
#define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000)
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
/*
* Make sure required options are set
*/
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif
#undef CONFIG_CLOCKS_IN_MHZ
/*
* Memory map
*
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
*
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
*
* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
*
* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
*
* Localbus cacheable
*
* 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
* 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
*
* Localbus non-cacheable
*
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
*
*/
/*
* Local Bus Definitions
*/
#define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */
#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
#define CFG_BR0_PRELIM 0xff801001
#define CFG_BR1_PRELIM 0xfe801001
#define CFG_OR0_PRELIM 0xff806e65
#define CFG_OR1_PRELIM 0xff806e65
#define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_LBC_NONCACHE_BASE 0xf8000000
#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */
#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
* register */
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
#define PIXIS_VCTL 0x10 /* VELA Control Register */
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM 1
#define CFG_INIT_L1_LOCK 1
#define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */
#define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */
/* define to use L2SRAM as initial stack */
#undef CONFIG_L2_INIT_RAM
#define CFG_INIT_L2_ADDR 0xf8fc0000
#define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */
#ifdef CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR
#define CFG_INIT_RAM_END CFG_INIT_L1_END
#else
#define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR
#define CFG_INIT_RAM_END CFG_INIT_L2_END
#endif
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
*/
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8544@0"
#define OF_SOC "soc8544@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500"
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3100
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
#define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
#define CFG_PCI1_MEM_BASE 0xc0000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe1000000
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x80000000
/* controller 2, Slot 1, tgtid 1, Base address 9000 */
#define CFG_PCIE2_MEM_BASE 0x80000000
#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCIE2_IO_BASE 0x00000000
#define CFG_PCIE2_IO_PHYS 0xe2000000
#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */
/* controller 1, Slot 2,tgtid 2, Base address a000 */
#define CFG_PCIE1_MEM_BASE 0xa0000000
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */
#define CFG_PCIE1_MEM_BASE2 0xa8000000
#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2
#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */
#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */
#define CFG_PCIE1_IO_PHYS 0xaf000000
#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
/* controller 3, direct to uli, tgtid 3, Base address b000 */
#define CFG_PCIE3_MEM_BASE 0xb0000000
#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCIE3_IO_BASE 0x00000000
#define CFG_PCIE3_IO_PHYS 0xe3000000
#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_RTL8139
#ifdef CONFIG_RTL8139
/* This macro is used by RTL8139 but not defined in PPC architecture */
#define KSEG1ADDR(x) (x)
#define _IO_BASE 0x00000000
#endif
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
#define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI
#ifdef CONFIG_SCSI_AHCI
#define CONFIG_SATA_ULI5288
#define CFG_SCSI_MAX_SCSI_ID 4
#define CFG_SCSI_MAX_LUN 1
#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif /* SCSCI */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/
#define CFG_ENV_IS_IN_FLASH 1
#if CFG_MONITOR_BASE > 0xfff80000
#define CFG_ENV_ADDR 0xfff80000
#else
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#endif
#define CFG_ENV_SIZE 0x2000
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PCI \
| CFG_CMD_PING \
| CFG_CMD_I2C \
| CFG_CMD_MII \
| CFG_CMD_BEDBUG \
| CFG_CMD_NET)
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_I2C \
| CFG_CMD_MII)
#endif
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.251
#define CONFIG_HOSTNAME 8544ds_unknown
#define CONFIG_ROOTPATH /nfs/mpc85xx
#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
#define PCIE_ENV \
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
"pcie1regs=setenv a e000a; run pciereg\0" \
"pcie2regs=setenv a e0009; run pciereg\0" \
"pcie3regs=setenv a e000b; run pciereg\0" \
"pcieerr=md ${a}020 1; md ${a}e00;" \
"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1;" \
"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
"pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \
"pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \
"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
"pci w $b.0 130 ffffffff\0" \
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
"pcie1err=setenv a e000a; run pcieerr\0" \
"pcie2err=setenv a e0009; run pcieerr\0" \
"pcie3err=setenv a e000b; run pcieerr\0" \
"pcie1errc=setenv a e000a; run pcieerrc\0" \
"pcie2errc=setenv a e0009; run pcieerrc\0" \
"pcie3errc=setenv a e000b; run pcieerrc\0"
#else
#define PCIE_ENV ""
#endif
#if defined(CONFIG_PCI1)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
"echo e;md ${a}e00 9\0" \
"pci1regs=setenv a e0008; run pcireg\0" \
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1\0" \
"pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
"pci w.w $b.0 56 ffff\0" \
"pci1err=setenv a e0008; run pcierr\0" \
"pci1errc=setenv a e0008; run pcierrc\0"
#else
#define PCI_ENV ""
#endif
#if defined(CONFIG_TSEC_ENET)
#define ENET_ENV \
"enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
"md ${a}098 2\0" \
"enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
"enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
"enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
"echo mib;md ${a}680 31\0" \
"enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
"enet1regs=setenv a e0024; run enetreg\0" \
"enet3regs=setenv a e0026; run enetreg\0"
#else
#define ENET_ENV ""
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \
"fdtaddr=400000\0" \
"fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \
"eoi=mw e00400b0 0\0" \
"iack=md e00400a0 1\0" \
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
"ddrregs=setenv a e0002; run ddrreg\0" \
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
"guregs=setenv a e00e0; run gureg\0" \
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
"ecmregs=setenv a e0001; run ecmreg\0" \
PCIE_ENV \
PCI_ENV \
ENET_ENV
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/sda3 rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#endif /* __CONFIG_H */

30
include/configs/MPC8548CDS.h
View File

@@ -36,12 +36,12 @@
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
#undef CONFIG_PCI
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
@@ -340,22 +340,34 @@ extern unsigned long get_clock_freq(void);
/*
* General PCI
* Addresses are mapped 1-1.
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_BASE 0x90000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI2_IO_PHYS 0xe2800000
#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */
#define CFG_PEX_MEM_BASE 0xa0000000
#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PEX_IO_BASE 0x00000000
#define CFG_PEX_IO_PHYS 0xe3000000
#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */
/*
* RapidIO MMU
*/
#define CFG_RIO_MEM_BASE 0xC0000000
#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
#if defined(CONFIG_PCI)

8
include/configs/MPC8560ADS.h
View File

@@ -320,14 +320,14 @@
/*
* General PCI
* Addresses are mapped 1-1.
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0xe2000000
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)

505
include/configs/MPC8568MDS.h Normal file
View File

@@ -0,0 +1,505 @@
/*
* Copyright 2004-2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mpc8568mds board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
#undef CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
/*
* When initializing flash, if we cannot find the manufacturer ID,
* assume this is the AMD flash associated with the MDS board.
* This allows booting from a promjet.
*/
#define CONFIG_ASSUME_AMD_FLASH
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif /*Replace a call to get_clock_freq (after it is implemented)*/
#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
/*#define CONFIG_L2_CACHE*/ /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
/*
* DDR Setup
*/
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
/*
* Make sure required options are set
*/
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif
#undef CONFIG_CLOCKS_IN_MHZ
/*
* Local Bus Definitions
*/
/*
* FLASH on the Local Bus
* Two banks, 8M each, using the CFI driver.
* Boot from BR0/OR0 bank at 0xff00_0000
* Alternate BR1/OR1 bank at 0xff80_0000
*
* BR0, BR1:
* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
* Port Size = 16 bits = BRx[19:20] = 10
* Use GPCM = BRx[24:26] = 000
* Valid = BRx[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
*
* OR0, OR1:
* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
* Reserved ORx[17:18] = 11, confusion here?
* CSNT = ORx[20] = 1
* ACS = half cycle delay = ORx[21:22] = 11
* SCY = 6 = ORx[24:27] = 0110
* TRLX = use relaxed timing = ORx[29] = 1
* EAD = use external address latch delay = OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
#define CFG_BCSR_BASE 0xf8000000
#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
/*Chip select 0 - Flash*/
#define CFG_BR0_PRELIM 0xfe001001
#define CFG_OR0_PRELIM 0xfe006ff7
/*Chip slelect 1 - BCSR*/
#define CFG_BR1_PRELIM 0xf8000801
#define CFG_OR1_PRELIM 0xffffe9f7
/*#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
/*
* SDRAM on the LocalBus
*/
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*Chip select 2 - SDRAM*/
#define CFG_BR2_PRELIM 0xf0001861
#define CFG_OR2_PRELIM 0xfc006901
#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
*/
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
/*
* Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1)
* or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
| CFG_LBC_LSDMR_PRETOACT7 \
| CFG_LBC_LSDMR_ACTTORW7 \
| CFG_LBC_LSDMR_BL8 \
| CFG_LBC_LSDMR_WRC4 \
| CFG_LBC_LSDMR_CL3 \
| CFG_LBC_LSDMR_RFEN \
)
/*
* The bcsr registers are connected to CS3 on MDS.
* The new memory map places bcsr at 0xf8000000.
*
* For BR3, need:
* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
* port-size = 8-bits = BR[19:20] = 01
* no parity checking = BR[21:22] = 00
* GPMC for MSEL = BR[24:26] = 000
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
*
* For OR3, need:
* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
* disable buffer ctrl OR[19] = 0
* CSNT OR[20] = 1
* ACS OR[21:22] = 11
* XACS OR[23] = 1
* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
* SETA OR[28] = 0
* TRLX OR[29] = 1
* EHTR OR[30] = 1
* EAD extra time OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
#define CFG_BCSR (0xf8000000)
/*Chip slelect 4 - PIB*/
#define CFG_BR4_PRELIM 0xf8008801
#define CFG_OR4_PRELIM 0xffffe9f7
/*Chip select 5 - PIB*/
#define CFG_BR5_PRELIM 0xf8010801
#define CFG_OR5_PRELIM 0xffff69f7
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser*/
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
#define OF_CPU "PowerPC,8568@0"
#define OF_SOC "soc8568@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
/*
* I2C
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
* Memory Addresses are mapped 1-1. I/O is mapped from 0
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
#define CFG_PEX_MEM_BASE 0xa0000000
#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PEX_IO_BASE 0x00000000
#define CFG_PEX_IO_PHYS 0xe2800000
#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */
#define CFG_SRIO_MEM_BASE 0xc0000000
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
#undef CONFIG_MPC85XX_TSEC3
#undef CONFIG_MPC85XX_TSEC4
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PCI \
| CFG_CMD_PING \
| CFG_CMD_I2C \
| CFG_CMD_MII)
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_I2C \
| CFG_CMD_MII)
#endif
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /nfsroot
#define CONFIG_BOOTFILE your.uImage
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=600000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
"fdtaddr=400000\0" \
"fdtfile=your.fdt.dtb\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs\0" \
"ramargs=setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs\0" \
#define CONFIG_NFSBOOTCOMMAND \
"run nfsargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"run ramargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"bootm $loadaddr $ramdiskaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */

16
include/configs/MPC8641HPCN.h
View File

@@ -212,7 +212,6 @@
#endif
#if defined(CFG_RAMBOOT)
#undef CFG_FLASH_CFI_DRIVER
#undef CONFIG_SPD_EEPROM
#define CFG_SDRAM_SIZE 256
#endif
@@ -468,7 +467,6 @@
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000
@@ -486,21 +484,13 @@
| CFG_CMD_SCSI \
| CFG_CMD_EXT2) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_IMLS \
| CFG_CMD_FLASH \
| CFG_CMD_LOADS))
~(CFG_CMD_ENV))
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_I2C \
| CFG_CMD_SCSI \
| CGF_CMD_EXT2) \
| CFG_CMD_I2C) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_IMLS \
| CFG_CMD_FLASH \
| CFG_CMD_LOADS))
~(CFG_CMD_ENV))
#endif
#else
#if defined(CONFIG_PCI)

12
include/configs/NC650.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2006 Detlev Zundel, dzu@denx.de
* (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
@@ -237,18 +237,8 @@
/*
* NAND flash support
*/
#define CFG_NAND_LEGACY
#define CFG_MAX_NAND_DEVICE 1
#define NAND_ChipID_UNKNOWN 0x00
#define SECTORSIZE 512
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define ADDR_COLUMN 1
#define NAND_NO_RB
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9

11
include/configs/PCI405.h
View File

@@ -1,6 +1,9 @@
/*
* (C) Copyright 2007
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
*
* (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -32,8 +35,6 @@
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $"
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PCI405 1 /* ...on a PCI405 board */
@@ -53,9 +54,9 @@
"mem_linux=14336k\0" \
"optargs=panic=0\0" \
"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
"addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
"addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
""
#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci"
#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci"
#define CONFIG_PREBOOT /* enable preboot variable */

8
include/configs/PLU405.h
View File

@@ -51,17 +51,13 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if 0 /* test-only */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_PHY1_ADDR 1 /* PHY address */
#else
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#endif
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/

11
include/configs/TQM834x.h
View File

@@ -57,17 +57,6 @@
*/
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
#define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK))
#define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */
#define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */
#define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */
#define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */
#define CFG_SCCR_VAL ( CFG_SCCR_INIT \
| CFG_SCCR_TSEC1CM \
| CFG_SCCR_TSEC2CM \
| CFG_SCCR_ENCCM \
| CFG_SCCR_USBCM )
/* board pre init: do not call, nothing to do */
#undef CONFIG_BOARD_EARLY_INIT_F

420
include/configs/acadia.h Normal file
View File

@@ -0,0 +1,420 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* acadia.h - configuration for AMCC Acadia (405EZ)
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_ACADIA 1 /* Board is Acadia */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
#define CONFIG_NO_SERIAL_EEPROM
/*#undef CONFIG_NO_SERIAL_EEPROM*/
#ifdef CONFIG_NO_SERIAL_EEPROM
/*----------------------------------------------------------------------------
* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
* assuming a 66MHz input clock to the 405EZ.
*---------------------------------------------------------------------------*/
/* #define PLLMR0_100_100_12 */
#define PLLMR0_200_133_66
/* #define PLLMR0_266_160_80 */
/* #define PLLMR0_333_166_83 */
#endif
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */
#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xfe000000
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_CPLD_BASE 0x80000000
#define CFG_NAND_ADDR 0xd0000000
#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
#define CFG_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* RAM (CRAM)
*----------------------------------------------------------------------*/
#define CFG_MBYTES_RAM 64 /* 64MB */
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_AD7414 1 /* use AD7414 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CFG_DTT_MAX_TEMP 70
#define CFG_DTT_LOW_TEMP -30
#define CFG_DTT_HYSTERESIS 3
#if 0 /* test-only... */
/*-----------------------------------------------------------------------
* SPI stuff - Define to include SPI control
*-----------------------------------------------------------------------
*/
#define CONFIG_SPI
#endif
/*-----------------------------------------------------------------------
* Ethernet
*----------------------------------------------------------------------*/
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_NET_MULTI 1
#define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=acadia\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=acadia/uImage\0" \
"kernel_addr=fff10000\0" \
"ramdisk_addr=fff20000\0" \
"initrd_high=30000000\0" \
"load=tftp 200000 acadia/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b ${fileaddr} fffc0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
"kozio=bootm ffc60000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
#if 0 /* test-only */
#define TEST_ONLY_NAND
#endif
#ifdef TEST_ONLY_NAND
#define CMD_NAND CFG_CMD_NAND
#else
#define CMD_NAND 0
#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DTT | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_FAT | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CMD_NAND | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_USB)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#ifdef TEST_ONLY_NAND
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 0 (Flash) initialization */
#define CFG_EBC_PB0AP 0x03337200
#define CFG_EBC_PB0CR 0xfe0bc000
/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
/* Memory Bank 1 (CRAM) initialization */
#define CFG_EBC_PB1AP 0x030400c0
#define CFG_EBC_PB1CR 0x000bc000
/* Memory Bank 2 (CRAM) initialization */
#define CFG_EBC_PB2AP 0x030400c0
#define CFG_EBC_PB2CR 0x020bc000
/* Memory Bank 3 (NAND-FLASH) initialization */
#define CFG_EBC_PB3AP 0x018003c0
#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
/* Memory Bank 4 (CPLD) initialization */
#define CFG_EBC_PB4AP 0x04006000
#define CFG_EBC_PB4CR (CFG_CPLD_BASE | 0x18000)
#define CFG_EBC_CFG 0xf8400000
/*-----------------------------------------------------------------------
* GPIO Setup
*----------------------------------------------------------------------*/
#define CFG_GPIO_CRAM_CLK 8
#define CFG_GPIO_CRAM_WAIT 9
#define CFG_GPIO_CRAM_ADV 10
#define CFG_GPIO_CRAM_CRE (32 + 21)
/*-----------------------------------------------------------------------
* Definitions for GPIO_0 setup (PPC405EZ specific)
*
* GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs
* GPIO0[4] - External Bus Controller Hold Input
* GPIO0[5] - External Bus Controller Priority Input
* GPIO0[6] - External Bus Controller HLDA Output
* GPIO0[7] - External Bus Controller Bus Request Output
* GPIO0[8] - CRAM Clk Output
* GPIO0[9] - External Bus Controller Ready Input
* GPIO0[10] - CRAM Adv Output
* GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
* GPIO0[25] - External DMA Request Input
* GPIO0[26] - External DMA EOT I/O
* GPIO0[25] - External DMA Ack_n Output
* GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
* GPIO0[28-30] - Trace Outputs / PWM Inputs
* GPIO0[31] - PWM_8 I/O
*/
#define CFG_GPIO0_TCR 0xC0000000
#define CFG_GPIO0_OSRL 0x50000000
#define CFG_GPIO0_OSRH 0x00000055
#define CFG_GPIO0_ISR1L 0x00000000
#define CFG_GPIO0_ISR1H 0x00000055
#define CFG_GPIO0_TSRL 0x00000000
#define CFG_GPIO0_TSRH 0x00000055
/*-----------------------------------------------------------------------
* Definitions for GPIO_1 setup (PPC405EZ specific)
*
* GPIO1[0-6] - PWM_9 to PWM_15 I/O
* GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
* GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
* GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
* GPIO1[10-12] - UART0 Control Inputs
* GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
* GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
* GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
* GPIO1[16] - SPI_SS_1_N Output
* GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
*/
#define CFG_GPIO1_OSRH 0x55455555
#define CFG_GPIO1_OSRL 0x40000110
#define CFG_GPIO1_ISR1H 0x00000000
#define CFG_GPIO1_ISR1L 0x15555445
#define CFG_GPIO1_TSRH 0x00000000
#define CFG_GPIO1_TSRL 0x00000000
#define CFG_GPIO1_TCR 0xFFFF8014
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

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