From 158d93adb482ef6dc1e50fcf9a7c3b21128d4cd9 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 2 Mar 2020 09:44:03 +0100 Subject: [PATCH 01/23] imx6, aristainetos2c: add da9063 pmic setup On the aristainetos2c boards the PMIC needs to be initialized, because the Ethernet PHY uses a different regulator that is not setup per hardware default. This does not influence the other versions as this regulator isn't used there at all. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 56 +++++++++++++++++++++++++++++++ configs/aristainetos2c_defconfig | 3 ++ 2 files changed, 59 insertions(+) diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 3541717873..70671039c2 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -30,6 +30,9 @@ #include #include #include +#include +#include +#include #include #include @@ -438,6 +441,56 @@ static void aristainetos_bootmode_settings(void) } } +#if defined(CONFIG_DM_PMIC_DA9063) +/* + * On the aristainetos2c boards the PMIC needs to be initialized, + * because the Ethernet PHY uses a different regulator that is not + * setup per hardware default. This does not influence the other versions + * as this regulator isn't used there at all. + * + * Unfortunately we have not yet a interface to setup all + * values we need. + */ +static int setup_pmic_voltages(void) +{ + struct udevice *dev; + int off; + int ret; + + off = fdt_path_offset(gd->fdt_blob, "pmic0"); + if (off < 0) { + printf("%s: No pmic path offset\n", __func__); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev); + if (ret) { + printf("%s: Could not find PMIC\n", __func__); + return ret; + } + + pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01); + pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1); + ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B); + if (ret < 0) { + printf("%s: error %d get register\n", __func__, ret); + return ret; + } + ret &= 0xf0; + ret |= 0x09; + pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret); + pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43); + pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3); + + return 0; +} +#else +static int setup_pmic_voltages(void) +{ + return 0; +} +#endif + int board_late_init(void) { int x, y; @@ -457,6 +510,9 @@ int board_late_init(void) else env_set("board_type", ARI_BT_7); + if (setup_pmic_voltages()) + printf("Error setup PMIC\n"); + return 0; } diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index c6d92251ce..8611915877 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -87,7 +87,10 @@ CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_PMIC_DA9063=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_DA9063=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_PWM=y CONFIG_PWM_IMX=y From c82b70bcc3b73934a1aeaeceb52561a3950a1fc5 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 19 Feb 2020 14:36:25 +0100 Subject: [PATCH 02/23] imx: remove woodburn board Board is not longer used, remove it. Signed-off-by: Stefano Babic --- arch/arm/Kconfig | 10 -- board/woodburn/Kconfig | 25 --- board/woodburn/MAINTAINERS | 12 -- board/woodburn/Makefile | 8 - board/woodburn/imximage.cfg | 4 - board/woodburn/lowlevel_init.S | 24 --- board/woodburn/woodburn.c | 251 ------------------------------ configs/woodburn_defconfig | 51 ------ configs/woodburn_sd_defconfig | 63 -------- include/configs/woodburn.h | 18 --- include/configs/woodburn_common.h | 195 ----------------------- include/configs/woodburn_sd.h | 30 ---- 12 files changed, 691 deletions(-) delete mode 100644 board/woodburn/Kconfig delete mode 100644 board/woodburn/MAINTAINERS delete mode 100644 board/woodburn/Makefile delete mode 100644 board/woodburn/imximage.cfg delete mode 100644 board/woodburn/lowlevel_init.S delete mode 100644 board/woodburn/woodburn.c delete mode 100644 configs/woodburn_defconfig delete mode 100644 configs/woodburn_sd_defconfig delete mode 100644 include/configs/woodburn.h delete mode 100644 include/configs/woodburn_common.h delete mode 100644 include/configs/woodburn_sd.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8d9f7fcce7..3d3d070223 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -598,15 +598,6 @@ config TARGET_X600 select PL011_SERIAL select SUPPORT_SPL -config TARGET_WOODBURN - bool "Support woodburn" - select CPU_ARM1136 - -config TARGET_WOODBURN_SD - bool "Support woodburn_sd" - select CPU_ARM1136 - select SUPPORT_SPL - config TARGET_FLEA3 bool "Support flea3" select CPU_ARM1136 @@ -1880,7 +1871,6 @@ source "board/birdland/bav335x/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" -source "board/woodburn/Kconfig" source "board/xilinx/Kconfig" source "board/xilinx/zynq/Kconfig" source "board/xilinx/zynqmp/Kconfig" diff --git a/board/woodburn/Kconfig b/board/woodburn/Kconfig deleted file mode 100644 index 4699526cfd..0000000000 --- a/board/woodburn/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -if TARGET_WOODBURN - -config SYS_BOARD - default "woodburn" - -config SYS_SOC - default "mx35" - -config SYS_CONFIG_NAME - default "woodburn" - -endif - -if TARGET_WOODBURN_SD - -config SYS_BOARD - default "woodburn" - -config SYS_SOC - default "mx35" - -config SYS_CONFIG_NAME - default "woodburn_sd" - -endif diff --git a/board/woodburn/MAINTAINERS b/board/woodburn/MAINTAINERS deleted file mode 100644 index 4fbf6bb88b..0000000000 --- a/board/woodburn/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -WOODBURN BOARD -M: Stefano Babic -S: Maintained -F: board/woodburn/ -F: include/configs/woodburn.h -F: configs/woodburn_defconfig - -WOODBURN_SD BOARD -#M: - -S: Maintained -F: include/configs/woodburn_sd.h -F: configs/woodburn_sd_defconfig diff --git a/board/woodburn/Makefile b/board/woodburn/Makefile deleted file mode 100644 index 9c3cd6934a..0000000000 --- a/board/woodburn/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2007, Guennadi Liakhovetski -# -# (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - -obj-y := woodburn.o -obj-y += lowlevel_init.o diff --git a/board/woodburn/imximage.cfg b/board/woodburn/imximage.cfg deleted file mode 100644 index ba42a5e7d5..0000000000 --- a/board/woodburn/imximage.cfg +++ /dev/null @@ -1,4 +0,0 @@ -BOOT_FROM sd - -/* DDR2 init */ -DATA 4 0xB8001010 0x00000304 diff --git a/board/woodburn/lowlevel_init.S b/board/woodburn/lowlevel_init.S deleted file mode 100644 index 8186b3922b..0000000000 --- a/board/woodburn/lowlevel_init.S +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007, Guennadi Liakhovetski - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2011, Stefano Babic - */ - -#include -#include - -.globl lowlevel_init -lowlevel_init: - - core_init - - init_aips - - init_max - - init_m3if - - mov pc, lr diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c deleted file mode 100644 index c69df6c7bf..0000000000 --- a/board/woodburn/woodburn.c +++ /dev/null @@ -1,251 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012, Stefano Babic - * - * Based on flea3.c and mx35pdk.c - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CCM_CCMR_CONFIG 0x003F4208 - -#define ESDCTL_DDR2_CONFIG 0x007FFC3F - -/* For MMC */ -#define GPIO_MMC_CD 7 -#define GPIO_MMC_WP 8 - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - - return 0; -} - -static void board_setup_sdram(void) -{ - struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; - - /* Initialize with default values both CSD0/1 */ - writel(0x2000, &esdc->esdctl0); - writel(0x2000, &esdc->esdctl1); - - mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, - 13, 10, 2, 0x8080); -} - -static void setup_iomux_fec(void) -{ - static const iomux_v3_cfg_t fec_pads[] = { - MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, - MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, - MX35_PAD_FEC_RX_DV__FEC_RX_DV, - MX35_PAD_FEC_COL__FEC_COL, - MX35_PAD_FEC_RDATA0__FEC_RDATA_0, - MX35_PAD_FEC_TDATA0__FEC_TDATA_0, - MX35_PAD_FEC_TX_EN__FEC_TX_EN, - MX35_PAD_FEC_MDC__FEC_MDC, - MX35_PAD_FEC_MDIO__FEC_MDIO, - MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, - MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, - MX35_PAD_FEC_CRS__FEC_CRS, - MX35_PAD_FEC_RDATA1__FEC_RDATA_1, - MX35_PAD_FEC_TDATA1__FEC_TDATA_1, - MX35_PAD_FEC_RDATA2__FEC_RDATA_2, - MX35_PAD_FEC_TDATA2__FEC_TDATA_2, - MX35_PAD_FEC_RDATA3__FEC_RDATA_3, - MX35_PAD_FEC_TDATA3__FEC_TDATA_3, - }; - - /* setup pins for FEC */ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); -} - -int woodburn_init(void) -{ - struct ccm_regs *ccm = - (struct ccm_regs *)IMX_CCM_BASE; - - /* initialize PLL and clock configuration */ - writel(CCM_CCMR_CONFIG, &ccm->ccmr); - - /* Set-up RAM */ - board_setup_sdram(); - - /* enable clocks */ - writel(readl(&ccm->cgr0) | - MXC_CCM_CGR0_EMI_MASK | - MXC_CCM_CGR0_EDIO_MASK | - MXC_CCM_CGR0_EPIT1_MASK, - &ccm->cgr0); - - writel(readl(&ccm->cgr1) | - MXC_CCM_CGR1_FEC_MASK | - MXC_CCM_CGR1_GPIO1_MASK | - MXC_CCM_CGR1_GPIO2_MASK | - MXC_CCM_CGR1_GPIO3_MASK | - MXC_CCM_CGR1_I2C1_MASK | - MXC_CCM_CGR1_I2C2_MASK | - MXC_CCM_CGR1_I2C3_MASK, - &ccm->cgr1); - - /* Set-up NAND */ - __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); - - /* Set pinmux for the required peripherals */ - setup_iomux_fec(); - - /* setup GPIO1_4 FEC_ENABLE signal */ - imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4); - gpio_direction_output(4, 1); - imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9); - gpio_direction_output(9, 1); - - return 0; -} - -#if defined(CONFIG_SPL_BUILD) -void board_init_f(ulong dummy) -{ - /* Set the stack pointer. */ - asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); - - /* Initialize MUX and SDRAM */ - woodburn_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - preloader_console_init(); - timer_init(); - - board_init_r(NULL, 0); -} - -void spl_board_init(void) -{ -} - -#endif - - -/* Booting from NOR in external mode */ -int board_early_init_f(void) -{ - return woodburn_init(); -} - - -int board_init(void) -{ - struct pmic *p; - u32 val; - int ret; - - /* address of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - ret = pmic_init(I2C_PMIC); - if (ret) - return ret; - - p = pmic_get("FSL_PMIC"); - - /* - * Set switchers in Auto in NORMAL mode & STANDBY mode - * Setup the switcher mode for SW1 & SW2 - */ - pmic_reg_read(p, REG_SW_4, &val); - val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | - (SWMODE_MASK << SWMODE2_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); - /* Set SWILIMB */ - val |= (1 << 22); - pmic_reg_write(p, REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - pmic_reg_read(p, REG_SW_5, &val); - val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | - (SWMODE_MASK << SWMODE3_SHIFT)); - val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); - pmic_reg_write(p, REG_SW_5, val); - - /* Set VGEN1 to 3.15V */ - pmic_reg_read(p, REG_SETTING_0, &val); - val &= ~(VGEN1_MASK); - val |= VGEN1_3_15; - pmic_reg_write(p, REG_SETTING_0, val); - - pmic_reg_read(p, REG_MODE_0, &val); - val |= VGEN1EN; - pmic_reg_write(p, REG_MODE_0, val); - udelay(2000); - - return 0; -} - -#if defined(CONFIG_FSL_ESDHC_IMX) -struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; - -int board_mmc_init(bd_t *bis) -{ - static const iomux_v3_cfg_t sdhc1_pads[] = { - MX35_PAD_SD1_CMD__ESDHC1_CMD, - MX35_PAD_SD1_CLK__ESDHC1_CLK, - MX35_PAD_SD1_DATA0__ESDHC1_DAT0, - MX35_PAD_SD1_DATA1__ESDHC1_DAT1, - MX35_PAD_SD1_DATA2__ESDHC1_DAT2, - MX35_PAD_SD1_DATA3__ESDHC1_DAT3, - }; - - /* configure pins for SDHC1 only */ - imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); - - /* MMC Card Detect on GPIO1_7 */ - imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7); - gpio_direction_input(GPIO_MMC_CD); - - /* MMC Write Protection on GPIO1_8 */ - imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8); - gpio_direction_input(GPIO_MMC_WP); - - esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); - - return fsl_esdhc_initialize(bis, &esdhc_cfg); -} - -int board_mmc_getcd(struct mmc *mmc) -{ - return !gpio_get_value(GPIO_MMC_CD); -} -#endif - -u32 get_board_rev(void) -{ - int rev = 0; - - return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; -} diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig deleted file mode 100644 index 2898564e95..0000000000 --- a/configs/woodburn_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_TARGET_WOODBURN=y -CONFIG_SYS_TEXT_BASE=0xA0000000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="woodburn U-Boot > " -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)" -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xA0080000 -CONFIG_ENV_ADDR_REDUND=0xA00A0000 -CONFIG_MXC_GPIO=y -CONFIG_FSL_ESDHC_IMX=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ8XXX=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig deleted file mode 100644 index 99675054f0..0000000000 --- a/configs/woodburn_sd_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_TARGET_WOODBURN_SD=y -CONFIG_SYS_TEXT_BASE=0x82000000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_NR_DRAM_BANKS=1 -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_TEXT_BASE=0x10002300 -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg" -CONFIG_BOOTDELAY=3 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_BOARD_INIT=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 -CONFIG_HUSH_PARSER=y -CONFIG_SYS_PROMPT="woodburn U-Boot > " -CONFIG_CMD_IMLS=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)" -CONFIG_EFI_PARTITION=y -# CONFIG_PARTITION_UUIDS is not set -# CONFIG_SPL_PARTITION_UUIDS is not set -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_ADDR=0xA0080000 -CONFIG_ENV_ADDR_REDUND=0xA00A0000 -CONFIG_MXC_GPIO=y -CONFIG_FSL_ESDHC_IMX=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXC=y -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ8XXX=y -CONFIG_MII=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y diff --git a/include/configs/woodburn.h b/include/configs/woodburn.h deleted file mode 100644 index 7f9ddb5b8e..0000000000 --- a/include/configs/woodburn.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011, Stefano Babic - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Configuration for the woodburn board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "woodburn_common.h" - -/* Set TEXT at the beginning of the NOR flash */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h deleted file mode 100644 index 194e43ecc6..0000000000 --- a/include/configs/woodburn_common.h +++ /dev/null @@ -1,195 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011, Stefano Babic - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Configuration for the woodburn board. - */ - -#ifndef __WOODBURN_COMMON_CONFIG_H -#define __WOODBURN_COMMON_CONFIG_H - -#include - - /* High Level Configuration Options */ -#define CONFIG_MX35 -#define CONFIG_MX35_HCLK_FREQ 24000000 -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3 - -/* This is required to setup the ESDC controller */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 -#define CONFIG_RTC_MC13XXX - -/* mmc driver */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/* - * UART (console) - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * Command definition - */ - -#define CONFIG_NET_RETRY_COUNT 100 - - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -/* - * Ethernet on SOC (FEC) - */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 - -#define CONFIG_DISCOVER_PHY - -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR - -#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \ - IRAM_BASE_ADDR - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * MTD Command for mtdparts - */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -/* Address and size of Redundant Environment Sector */ - -/* - * CFI FLASH driver setup - */ - -/* A non-standard buffered write algorithm */ - -/* - * NAND FLASH driver setup - */ -#define CONFIG_NAND_MXC_V1_1 -#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define CONFIG_HOSTNAME "woodburn" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "loadaddr=80800000\0" \ - "kernel_addr_r=80800000\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "net_self=if run net_self_load;then " \ - "run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ - "else echo Images not loades;fi\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +80000;" \ - "erase ${uboot_addr} +80000;" \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "bootcmd=run net_nfs\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h deleted file mode 100644 index 60d8a4b8c3..0000000000 --- a/include/configs/woodburn_sd.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011, Stefano Babic - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Configuration for the woodburn board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "woodburn_common.h" - -/* Set TEXT in RAM */ - -/* - * SPL - */ - -#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#endif /* __CONFIG_H */ From 10a8cc01b32114c6412691206f6402ed3fc50c9f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 17 Feb 2020 15:17:01 -0300 Subject: [PATCH 03/23] imx8qxp_mek: Fix the console command line string Currently the expansion of the console variable leads to the following kernel command line: console=ttyLP0,${baudrate} earlycon root=/dev/mmcblk1p2 rootwait rw , which causes the console to not show characters after the LPUART driver is probed as the 'baudrate' variable is not properly translated. Fix it by splitting the console variable in two parts: one for the ttyLP0 part and the other one for the baudrate, which matches the way it is done on other i.MX targets. Tested by successfully booting a mainline kernel on a i.MX8QXP MEK board. Signed-off-by: Fabio Estevam --- include/configs/imx8qxp_mek.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 81ac4b52f3..0aaca3325b 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -65,7 +65,7 @@ "script=boot.scr\0" \ "image=Image\0" \ "panel=NULL\0" \ - "console=ttyLP0,${baudrate} earlycon\0" \ + "console=ttyLP0\0" \ "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ @@ -76,7 +76,7 @@ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ @@ -104,7 +104,7 @@ "echo wait for boot; " \ "fi;" \ "fi;\0" \ - "netargs=setenv bootargs console=${console} " \ + "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ From 028b195b3912b523a2a325f1cc9eaf7f5e658afc Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 27 Feb 2020 14:58:54 -0300 Subject: [PATCH 04/23] mx7dsabresd: Add myself as maintainer I would like to help co-maintaining this board. Signed-off-by: Fabio Estevam --- board/freescale/mx7dsabresd/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/mx7dsabresd/MAINTAINERS b/board/freescale/mx7dsabresd/MAINTAINERS index 5f805afc58..721321c9cc 100644 --- a/board/freescale/mx7dsabresd/MAINTAINERS +++ b/board/freescale/mx7dsabresd/MAINTAINERS @@ -1,5 +1,6 @@ MX7DSABRESD BOARD M: Adrian Alonso +M: Fabio Estevam S: Maintained F: board/freescale/mx7dsabresd F: include/configs/mx7dsabresd.h From 322bc3e4124d48a502eca76838f1edf0be5fd690 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 27 Feb 2020 14:58:55 -0300 Subject: [PATCH 05/23] imx8qxp_mek: Add myself as maintainer I would like to help co-maintaining this board. Signed-off-by: Fabio Estevam --- board/freescale/imx8qxp_mek/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/freescale/imx8qxp_mek/MAINTAINERS b/board/freescale/imx8qxp_mek/MAINTAINERS index e9bf0b35a3..3a21f5521d 100644 --- a/board/freescale/imx8qxp_mek/MAINTAINERS +++ b/board/freescale/imx8qxp_mek/MAINTAINERS @@ -1,5 +1,6 @@ i.MX8QXP MEK BOARD M: Peng Fan +M: Fabio Estevam S: Maintained F: board/freescale/imx8qxp_mek/ F: include/configs/imx8qxp_mek.h From 47c2eae1b8a1c55940b042ec1738b3267c2b4dc9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 19 Feb 2020 09:56:26 -0300 Subject: [PATCH 06/23] ARM: dts: imx6sx: Sync with kernel 5.4.16 Sync the imx6sx dts files with kernel 5.4.16. Signed-off-by: Fabio Estevam --- arch/arm/dts/imx6sx-pinfunc.h | 6 +- arch/arm/dts/imx6sx.dtsi | 507 ++++++++++++++--------- include/dt-bindings/clock/imx6sx-clock.h | 13 +- 3 files changed, 309 insertions(+), 217 deletions(-) diff --git a/arch/arm/dts/imx6sx-pinfunc.h b/arch/arm/dts/imx6sx-pinfunc.h index 42c4c800fe..aa194a2fdd 100644 --- a/arch/arm/dts/imx6sx-pinfunc.h +++ b/arch/arm/dts/imx6sx-pinfunc.h @@ -1,10 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ #ifndef __DTS_IMX6SX_PINFUNC_H diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi index 8ccf2647e9..531a52c1e9 100644 --- a/arch/arm/dts/imx6sx.dtsi +++ b/arch/arm/dts/imx6sx.dtsi @@ -1,19 +1,23 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2014 Freescale Semiconductor, Inc. #include #include #include #include #include "imx6sx-pinfunc.h" -#include "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + /* + * The decompressor and also some bootloaders rely on a + * pre-existing /chosen node to be available to insert the + * command line and merge other ATAGS info. + */ + chosen {}; + aliases { can0 = &flexcan1; can1 = &flexcan2; @@ -40,13 +44,11 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; - spi0 = &qspi1; - spi1 = &qspi2; - spi2 = &ecspi1; - spi3 = &ecspi2; - spi4 = &ecspi3; - spi5 = &ecspi4; - spi6 = &ecspi5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + spi4 = &ecspi5; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; @@ -75,6 +77,7 @@ 198000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SX_CLK_ARM>, <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, @@ -87,50 +90,67 @@ }; }; - intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; + ckil: clock-ckil { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; }; - clocks { - #address-cells = <1>; - #size-cells = <0>; + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; - ckil: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "ckil"; - }; + ipp_di0: clock-ipp-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; - osc: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc"; - }; + ipp_di1: clock-ipp-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; - ipp_di0: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di0"; - }; + anaclk1: clock-anaclk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "anaclk1"; + }; - ipp_di1: clock@3 { - compatible = "fixed-clock"; - reg = <3>; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "ipp_di1"; - }; + anaclk2: clock-anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "anaclk2"; + }; + + tempmon: tempmon { + compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&gpc>; + interrupts = ; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; }; soc { @@ -140,18 +160,28 @@ interrupt-parent = <&gpc>; ranges; - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = ; + ocram_s: sram@8f8000 { + compatible = "mmio-sram"; + reg = <0x008f8000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCRAM_S>; }; - ocram: sram@00900000 { + ocram: sram@900000 { compatible = "mmio-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; - L2: l2-cache@00a02000 { + intc: interrupt-controller@a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + + L2: l2-cache@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = ; @@ -161,7 +191,7 @@ arm,data-latency = <4 2 3>; }; - gpu: gpu@01800000 { + gpu: gpu@1800000 { compatible = "vivante,gc"; reg = <0x01800000 0x4000>; interrupts = ; @@ -169,9 +199,10 @@ <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_GPU>; clock-names = "bus", "core", "shader"; + power-domains = <&pd_pu>; }; - dma_apbh: dma-apbh@01804000 { + dma_apbh: dma-apbh@1804000 { compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; interrupts = , @@ -184,7 +215,7 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@01806000{ + gpmi: gpmi-nand@1806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -204,21 +235,21 @@ status = "disabled"; }; - aips1: aips-bus@02000000 { + aips1: aips-bus@2000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x100000>; ranges; - spba-bus@02000000 { + spba-bus@2000000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02000000 0x40000>; ranges; - spdif: spdif@02004000 { + spdif: spdif@2004000 { compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = ; @@ -240,7 +271,7 @@ status = "disabled"; }; - ecspi1: ecspi@02008000 { + ecspi1: spi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -252,7 +283,7 @@ status = "disabled"; }; - ecspi2: ecspi@0200c000 { + ecspi2: spi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -264,7 +295,7 @@ status = "disabled"; }; - ecspi3: ecspi@02010000 { + ecspi3: spi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -276,7 +307,7 @@ status = "disabled"; }; - ecspi4: ecspi@02014000 { + ecspi4: spi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -288,8 +319,9 @@ status = "disabled"; }; - uart1: serial@02020000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + uart1: serial@2020000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x02020000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -300,7 +332,7 @@ status = "disabled"; }; - esai: esai@02024000 { + esai: esai@2024000 { reg = <0x02024000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_ESAI_IPG>, @@ -313,7 +345,7 @@ status = "disabled"; }; - ssi1: ssi@02028000 { + ssi1: ssi@2028000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; @@ -327,7 +359,7 @@ status = "disabled"; }; - ssi2: ssi@0202c000 { + ssi2: ssi@202c000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; @@ -341,7 +373,7 @@ status = "disabled"; }; - ssi3: ssi@02030000 { + ssi3: ssi@2030000 { #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; @@ -355,7 +387,7 @@ status = "disabled"; }; - asrc: asrc@02034000 { + asrc: asrc@2034000 { reg = <0x02034000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_ASRC_MEM>, @@ -372,7 +404,7 @@ }; }; - pwm1: pwm@02080000 { + pwm1: pwm@2080000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = ; @@ -382,7 +414,7 @@ #pwm-cells = <2>; }; - pwm2: pwm@02084000 { + pwm2: pwm@2084000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = ; @@ -392,7 +424,7 @@ #pwm-cells = <2>; }; - pwm3: pwm@02088000 { + pwm3: pwm@2088000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = ; @@ -402,7 +434,7 @@ #pwm-cells = <2>; }; - pwm4: pwm@0208c000 { + pwm4: pwm@208c000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = ; @@ -412,28 +444,30 @@ #pwm-cells = <2>; }; - flexcan1: can@02090000 { + flexcan1: can@2090000 { compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; reg = <0x02090000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_CAN1_IPG>, <&clks IMX6SX_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; - flexcan2: can@02094000 { + flexcan2: can@2094000 { compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; reg = <0x02094000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_CAN2_IPG>, <&clks IMX6SX_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; - gpt: gpt@02098000 { - compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt"; + gpt: gpt@2098000 { + compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; reg = <0x02098000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_GPT_BUS>, @@ -441,7 +475,7 @@ clock-names = "ipg", "per"; }; - gpio1: gpio@0209c000 { + gpio1: gpio@209c000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x0209c000 0x4000>; interrupts = , @@ -453,7 +487,7 @@ gpio-ranges = <&iomuxc 0 5 26>; }; - gpio2: gpio@020a0000 { + gpio2: gpio@20a0000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020a0000 0x4000>; interrupts = , @@ -465,7 +499,7 @@ gpio-ranges = <&iomuxc 0 31 20>; }; - gpio3: gpio@020a4000 { + gpio3: gpio@20a4000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020a4000 0x4000>; interrupts = , @@ -477,7 +511,7 @@ gpio-ranges = <&iomuxc 0 51 29>; }; - gpio4: gpio@020a8000 { + gpio4: gpio@20a8000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020a8000 0x4000>; interrupts = , @@ -489,7 +523,7 @@ gpio-ranges = <&iomuxc 0 80 32>; }; - gpio5: gpio@020ac000 { + gpio5: gpio@20ac000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020ac000 0x4000>; interrupts = , @@ -501,7 +535,7 @@ gpio-ranges = <&iomuxc 0 112 24>; }; - gpio6: gpio@020b0000 { + gpio6: gpio@20b0000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020b0000 0x4000>; interrupts = , @@ -513,7 +547,7 @@ gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; }; - gpio7: gpio@020b4000 { + gpio7: gpio@20b4000 { compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; reg = <0x020b4000 0x4000>; interrupts = , @@ -525,40 +559,40 @@ gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; }; - kpp: kpp@020b8000 { + kpp: kpp@20b8000 { compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; + clocks = <&clks IMX6SX_CLK_IPG>; status = "disabled"; }; - wdog1: wdog@020bc000 { + wdog1: wdog@20bc000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; + clocks = <&clks IMX6SX_CLK_IPG>; }; - wdog2: wdog@020c0000 { + wdog2: wdog@20c0000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; + clocks = <&clks IMX6SX_CLK_IPG>; status = "disabled"; }; - clks: ccm@020c4000 { + clks: ccm@20c4000 { compatible = "fsl,imx6sx-ccm"; reg = <0x020c4000 0x4000>; interrupts = , ; #clock-cells = <1>; - clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; - clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; }; - anatop: anatop@020c8000 { + anatop: anatop@20c8000 { compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", "syscon", "simple-bus"; reg = <0x020c8000 0x1000>; @@ -566,11 +600,11 @@ , ; - regulator-1p1 { + reg_vdd1p1: regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1375000>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; regulator-always-on; anatop-reg-offset = <0x110>; anatop-vol-bit-shift = <8>; @@ -578,9 +612,10 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_vdd3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -592,13 +627,14 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; - regulator-2p5 { + reg_vdd2p5: regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2875000>; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2750000>; regulator-always-on; anatop-reg-offset = <0x130>; anatop-vol-bit-shift = <8>; @@ -606,6 +642,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2875000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { @@ -659,15 +696,7 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; - interrupts = ; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; - }; - - usbphy1: usbphy@020c9000 { + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = ; @@ -675,7 +704,7 @@ fsl,anatop = <&anatop>; }; - usbphy2: usbphy@020ca000 { + usbphy2: usbphy@20ca000 { compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = ; @@ -683,7 +712,7 @@ fsl,anatop = <&anatop>; }; - snvs: snvs@020cc000 { + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -698,6 +727,7 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; + value = <0x60>; mask = <0x60>; status = "disabled"; }; @@ -708,20 +738,21 @@ interrupts = ; linux,keycode = ; wakeup-source; + status = "disabled"; }; }; - epit1: epit@020d0000 { + epit1: epit@20d0000 { reg = <0x020d0000 0x4000>; interrupts = ; }; - epit2: epit@020d4000 { + epit2: epit@20d4000 { reg = <0x020d4000 0x4000>; interrupts = ; }; - src: src@020d8000 { + src: src@20d8000 { compatible = "fsl,imx6sx-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = , @@ -729,31 +760,68 @@ #reset-cells = <1>; }; - gpc: gpc@020dc000 { + gpc: gpc@20dc000 { compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; reg = <0x020dc000 0x4000>; interrupt-controller; #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + clocks = <&clks IMX6SX_CLK_IPG>; + clock-names = "ipg"; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + power-domain@0 { + reg = <0>; + #power-domain-cells = <0>; + }; + + pd_pu: power-domain@1 { + reg = <1>; + #power-domain-cells = <0>; + power-supply = <®_soc>; + clocks = <&clks IMX6SX_CLK_GPU>; + }; + + pd_disp: power-domain@2 { + reg = <2>; + #power-domain-cells = <0>; + clocks = <&clks IMX6SX_CLK_PXP_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>, + <&clks IMX6SX_CLK_LCDIF1_PIX>, + <&clks IMX6SX_CLK_LCDIF_APB>, + <&clks IMX6SX_CLK_LCDIF2_PIX>, + <&clks IMX6SX_CLK_CSI>, + <&clks IMX6SX_CLK_VADC>; + }; + + pd_pci: power-domain@3 { + reg = <3>; + #power-domain-cells = <0>; + power-supply = <®_pcie>; + }; + }; }; - iomuxc: iomuxc@020e0000 { + iomuxc: iomuxc@20e0000 { compatible = "fsl,imx6sx-iomuxc"; reg = <0x020e0000 0x4000>; }; - gpr: iomuxc-gpr@020e4000 { + gpr: iomuxc-gpr@20e4000 { compatible = "fsl,imx6sx-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e4000 0x4000>; }; - sdma: sdma@020ec000 { + sdma: sdma@20ec000 { compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_SDMA>, + clocks = <&clks IMX6SX_CLK_IPG>, <&clks IMX6SX_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; @@ -762,7 +830,7 @@ }; }; - aips2: aips-bus@02100000 { + aips2: aips-bus@2100000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -771,7 +839,6 @@ crypto: caam@2100000 { compatible = "fsl,sec-v4.0"; - fsl,sec-era = <4>; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; @@ -796,7 +863,7 @@ }; }; - usbotg1: usb@02184000 { + usbotg1: usb@2184000 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = ; @@ -810,7 +877,7 @@ status = "disabled"; }; - usbotg2: usb@02184200 { + usbotg2: usb@2184200 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184200 0x200>; interrupts = ; @@ -823,11 +890,12 @@ status = "disabled"; }; - usbh: usb@02184400 { + usbh: usb@2184400 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184400 0x200>; interrupts = ; clocks = <&clks IMX6SX_CLK_USBOH3>; + fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc 2>; phy_type = "hsic"; fsl,anatop = <&anatop>; @@ -838,16 +906,17 @@ status = "disabled"; }; - usbmisc: usbmisc@02184800 { + usbmisc: usbmisc@2184800 { #index-cells = <1>; compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6SX_CLK_USBOH3>; }; - fec1: ethernet@02188000 { + fec1: ethernet@2188000 { compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; + interrupt-names = "int0", "pps"; interrupts = , ; clocks = <&clks IMX6SX_CLK_ENET>, @@ -857,12 +926,12 @@ <&clks IMX6SX_CLK_ENET_PTP>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; status = "disabled"; - }; + }; - mlb: mlb@0218c000 { + mlb: mlb@218c000 { reg = <0x0218c000 0x4000>; interrupts = , , @@ -871,7 +940,7 @@ status = "disabled"; }; - usdhc1: usdhc@02190000 { + usdhc1: usdhc@2190000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02190000 0x4000>; interrupts = ; @@ -883,7 +952,7 @@ status = "disabled"; }; - usdhc2: usdhc@02194000 { + usdhc2: usdhc@2194000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02194000 0x4000>; interrupts = ; @@ -895,7 +964,7 @@ status = "disabled"; }; - usdhc3: usdhc@02198000 { + usdhc3: usdhc@2198000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x02198000 0x4000>; interrupts = ; @@ -907,7 +976,7 @@ status = "disabled"; }; - usdhc4: usdhc@0219c000 { + usdhc4: usdhc@219c000 { compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; reg = <0x0219c000 0x4000>; interrupts = ; @@ -919,7 +988,7 @@ status = "disabled"; }; - i2c1: i2c@021a0000 { + i2c1: i2c@21a0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -929,7 +998,7 @@ status = "disabled"; }; - i2c2: i2c@021a4000 { + i2c2: i2c@21a4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -939,7 +1008,7 @@ status = "disabled"; }; - i2c3: i2c@021a8000 { + i2c3: i2c@21a8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -949,14 +1018,16 @@ status = "disabled"; }; - mmdc: mmdc@021b0000 { + memory-controller@21b0000 { compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; + clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; }; - fec2: ethernet@021b4000 { + fec2: ethernet@21b4000 { compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; reg = <0x021b4000 0x4000>; + interrupt-names = "int0", "pps"; interrupts = , ; clocks = <&clks IMX6SX_CLK_ENET>, @@ -969,20 +1040,34 @@ status = "disabled"; }; - weim: weim@021b8000 { + weim: weim@21b8000 { + #address-cells = <2>; + #size-cells = <1>; compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_EIM_SLOW>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; }; - ocotp: ocotp@021bc000 { + ocotp: ocotp@21bc000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx6sx-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SX_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; - sai1: sai@021d4000 { + sai1: sai@21d4000 { compatible = "fsl,imx6sx-sai"; reg = <0x021d4000 0x4000>; interrupts = ; @@ -995,13 +1080,13 @@ status = "disabled"; }; - audmux: audmux@021d8000 { + audmux: audmux@21d8000 { compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; reg = <0x021d8000 0x4000>; status = "disabled"; }; - sai2: sai@021dc000 { + sai2: sai@21dc000 { compatible = "fsl,imx6sx-sai"; reg = <0x021dc000 0x4000>; interrupts = ; @@ -1014,7 +1099,7 @@ status = "disabled"; }; - qspi1: qspi@021e0000 { + qspi1: spi@21e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-qspi"; @@ -1027,7 +1112,7 @@ status = "disabled"; }; - qspi2: qspi@021e4000 { + qspi2: spi@21e4000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-qspi"; @@ -1040,8 +1125,9 @@ status = "disabled"; }; - uart2: serial@021e8000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + uart2: serial@21e8000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021e8000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1052,8 +1138,9 @@ status = "disabled"; }; - uart3: serial@021ec000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + uart3: serial@21ec000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1064,8 +1151,9 @@ status = "disabled"; }; - uart4: serial@021f0000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + uart4: serial@21f0000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f0000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1076,8 +1164,9 @@ status = "disabled"; }; - uart5: serial@021f4000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + uart5: serial@21f4000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x021f4000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1088,7 +1177,7 @@ status = "disabled"; }; - i2c4: i2c@021f8000 { + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; @@ -1099,21 +1188,21 @@ }; }; - aips3: aips-bus@02200000 { + aips3: aips-bus@2200000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02200000 0x100000>; ranges; - spba-bus@02200000 { + spba-bus@2240000 { compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; reg = <0x02240000 0x40000>; ranges; - csi1: csi@02214000 { + csi1: csi@2214000 { reg = <0x02214000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, @@ -1123,16 +1212,17 @@ status = "disabled"; }; - pxp: pxp@02218000 { + pxp: pxp@2218000 { + compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; reg = <0x02218000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_PXP_AXI>, - <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pxp-axi", "disp-axi"; + clocks = <&clks IMX6SX_CLK_PXP_AXI>; + clock-names = "axi"; + power-domains = <&pd_disp>; status = "disabled"; }; - csi2: csi@0221c000 { + csi2: csi@221c000 { reg = <0x0221c000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, @@ -1142,39 +1232,42 @@ status = "disabled"; }; - lcdif1: lcdif@02220000 { + lcdif1: lcdif@2220000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02220000 0x4000>; - interrupts = ; + interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; status = "disabled"; }; - lcdif2: lcdif@02224000 { + lcdif2: lcdif@2224000 { compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02224000 0x4000>; - interrupts = ; + interrupts = ; clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + power-domains = <&pd_disp>; status = "disabled"; }; - vadc: vadc@02228000 { + vadc: vadc@2228000 { reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; reg-names = "vadc-vafe", "vadc-vdec"; clocks = <&clks IMX6SX_CLK_VADC>, <&clks IMX6SX_CLK_CSI>; clock-names = "vadc", "csi"; + power-domains = <&pd_disp>; status = "disabled"; }; }; - adc1: adc@02280000 { + adc1: adc@2280000 { compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; reg = <0x02280000 0x4000>; interrupts = ; @@ -1183,9 +1276,9 @@ fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; - }; + }; - adc2: adc@02284000 { + adc2: adc@2284000 { compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; reg = <0x02284000 0x4000>; interrupts = ; @@ -1194,17 +1287,17 @@ fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; - }; + }; - wdog3: wdog@02288000 { + wdog3: wdog@2288000 { compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; reg = <0x02288000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_DUMMY>; + clocks = <&clks IMX6SX_CLK_IPG>; status = "disabled"; }; - ecspi5: ecspi@0228c000 { + ecspi5: spi@228c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; @@ -1216,8 +1309,9 @@ status = "disabled"; }; - uart6: serial@022a0000 { - compatible = "fsl,imx6sx-uart", "fsl,imx21-uart"; + uart6: serial@22a0000 { + compatible = "fsl,imx6sx-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; reg = <0x022a0000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_UART_IPG>, @@ -1228,7 +1322,7 @@ status = "disabled"; }; - pwm5: pwm@022a4000 { + pwm5: pwm@22a4000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x022a4000 0x4000>; interrupts = ; @@ -1238,7 +1332,7 @@ #pwm-cells = <2>; }; - pwm6: pwm@022a8000 { + pwm6: pwm@22a8000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x022a8000 0x4000>; interrupts = ; @@ -1248,7 +1342,7 @@ #pwm-cells = <2>; }; - pwm7: pwm@022ac000 { + pwm7: pwm@22ac000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x022ac000 0x4000>; interrupts = ; @@ -1258,7 +1352,7 @@ #pwm-cells = <2>; }; - pwm8: pwm@0022b0000 { + pwm8: pwm@22b0000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x0022b0000 0x4000>; interrupts = ; @@ -1269,32 +1363,33 @@ }; }; - pcie: pcie@0x08000000 { + pcie: pcie@8ffc000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; - reg = <0x08ffc000 0x4000>; /* DBI */ + reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - /* configuration space */ - ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000 - /* downstream I/O */ - 0x81000000 0 0 0x08f80000 0 0x00010000 - /* non-prefetchable memory */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, - <&clks IMX6SX_CLK_PCIE_AXI>, + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_PCIE_AXI>, <&clks IMX6SX_CLK_LVDS1_OUT>, + <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; - clock-names = "pcie_ref_125m", "pcie_axi", - "lvds_gate", "display_axi"; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; + power-domains = <&pd_disp>, <&pd_pci>; + power-domain-names = "pcie", "pcie_phy"; status = "disabled"; }; }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu>; - }; }; diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h index 36f0324902..1c64997d61 100644 --- a/include/dt-bindings/clock/imx6sx-clock.h +++ b/include/dt-bindings/clock/imx6sx-clock.h @@ -1,10 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * */ #ifndef __DT_BINDINGS_CLOCK_IMX6SX_H @@ -275,6 +271,11 @@ #define IMX6SX_PLL6_BYPASS 262 #define IMX6SX_PLL7_BYPASS 263 #define IMX6SX_CLK_SPDIF_GCLK 264 -#define IMX6SX_CLK_CLK_END 265 +#define IMX6SX_CLK_LVDS2_SEL 265 +#define IMX6SX_CLK_LVDS2_OUT 266 +#define IMX6SX_CLK_LVDS2_IN 267 +#define IMX6SX_CLK_ANACLK2 268 +#define IMX6SX_CLK_MMDC_P1_IPG 269 +#define IMX6SX_CLK_CLK_END 270 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */ From a29d79da437aff68cbbaf126754d173a98568a4c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 19 Feb 2020 09:56:27 -0300 Subject: [PATCH 07/23] ARM: dts: imx6sx-sdb: Sync with kernel 5.4.16 Sync the imx6sx-sdb dts files with kernel 5.4.16. Signed-off-by: Fabio Estevam --- arch/arm/dts/imx6sx-sdb-u-boot.dtsi | 16 -- arch/arm/dts/imx6sx-sdb.dts | 35 +++- arch/arm/dts/imx6sx-sdb.dtsi | 276 +++++++++++++++++----------- 3 files changed, 196 insertions(+), 131 deletions(-) delete mode 100644 arch/arm/dts/imx6sx-sdb-u-boot.dtsi diff --git a/arch/arm/dts/imx6sx-sdb-u-boot.dtsi b/arch/arm/dts/imx6sx-sdb-u-boot.dtsi deleted file mode 100644 index 8f9236da0f..0000000000 --- a/arch/arm/dts/imx6sx-sdb-u-boot.dtsi +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -&qspi2 { - num-cs = <2>; - - flash0: n25q256a@0 { - compatible = "jedec,spi-nor"; - }; - - flash1: n25q256a@1 { - compatible = "jedec,spi-nor"; - }; -}; diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts index 6dd9bebfe0..5a63ca6157 100644 --- a/arch/arm/dts/imx6sx-sdb.dts +++ b/arch/arm/dts/imx6sx-sdb.dts @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. #include "imx6sx-sdb.dtsi" @@ -117,15 +113,19 @@ #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; reg = <0>; }; - flash1: n25q256a@1 { + flash1: n25q256a@2 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; - reg = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + reg = <2>; }; }; @@ -136,3 +136,20 @@ ®_soc { vin-supply = <&sw1a_reg>; }; + +®_vdd1p1 { + vin-supply = <&vgen6_reg>; +}; + +®_vdd2p5 { + vin-supply = <&vgen6_reg>; +}; + +®_can_stby { + /* Transceiver EN/STBY is active low on RevB board */ + gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; +}; + +&snvs_pwrkey { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6sx-sdb.dtsi b/arch/arm/dts/imx6sx-sdb.dtsi index da815527a7..f6972deb5e 100644 --- a/arch/arm/dts/imx6sx-sdb.dtsi +++ b/arch/arm/dts/imx6sx-sdb.dtsi @@ -1,10 +1,6 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2014 Freescale Semiconductor, Inc. /dts-v1/; @@ -20,11 +16,12 @@ stdout-path = &uart1; }; - memory { + memory@80000000 { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; - backlight { + backlight_display: backlight-display { compatible = "pwm-backlight"; pwms = <&pwm3 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -40,95 +37,118 @@ label = "Volume Up"; gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; volume-down { label = "Volume Down"; gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; linux,code = ; + wakeup-source; }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + vcc_sd3: regulator-vcc-sd3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - vcc_sd3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_otg1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_otg2_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_psu_5v: regulator-psu-5v { + compatible = "regulator-fixed"; + regulator-name = "PSU-5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; - reg_psu_5v: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "PSU-5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + reg_lcd_3v3: regulator-lcd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + }; - reg_lcd_3v3: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "lcd-3v3"; - gpio = <&gpio3 27 0>; - enable-active-high; - }; + reg_peri_3v3: regulator-peri-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_peri_3v3>; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; - reg_peri_3v3: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_peri_3v3>; - regulator-name = "peri_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; + reg_enet_3v3: regulator-enet-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_3v3>; + regulator-name = "enet_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; + regulator-boot-on; + regulator-always-on; + }; - reg_enet_3v3: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_3v3>; - regulator-name = "enet_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; - }; + reg_pcie_gpio: regulator-pcie-gpio { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lcd_5v: regulator-lcd-5v { + compatible = "regulator-fixed"; + regulator-name = "lcd-5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_can_en: regulator-can-en { + compatible = "regulator-fixed"; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_can_stby: regulator-can-stby { + compatible = "regulator-fixed"; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; sound { @@ -146,6 +166,19 @@ mux-int-port = <2>; mux-ext-port = <6>; }; + + panel { + compatible = "sii,43wvf1g"; + backlight = <&backlight_display>; + dvdd-supply = <®_lcd_3v3>; + avdd-supply = <®_lcd_5v>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; }; &audmux { @@ -158,8 +191,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; phy-supply = <®_enet_3v3>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy1>; + phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; status = "okay"; mdio { @@ -184,6 +218,20 @@ status = "okay"; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + &i2c3 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -212,34 +260,22 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_gpio>; + status = "okay"; +}; + &lcdif1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; - lcd-supply = <®_lcd_3v3>; - display = <&display0>; status = "okay"; - display0: display0 { - bits-per-pixel = <16>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <33500000>; - hactive = <800>; - vactive = <480>; - hback-porch = <89>; - hfront-porch = <164>; - vback-porch = <23>; - vfront-porch = <10>; - hsync-len = <10>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; @@ -365,6 +401,8 @@ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + /* phy reset */ + MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x10b0 >; }; @@ -391,6 +429,20 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059 @@ -453,6 +505,18 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0 + >; + }; + pinctrl_peri_3v3: peri3v3grp { fsl,pins = < MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 From 823c4cd74901d760f2cd82435664c36583e8bb16 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Wed, 5 Feb 2020 17:49:59 +0100 Subject: [PATCH 08/23] imx: mx6ul_14x14_evk: configure for 24bpp display Before DM_VIDEO conversion this board used 24bpp display configuration, so use it again. Signed-off-by: Anatolij Gustschin Reviewed-by: Fabio Estevam --- arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi index e9efdb9831..d0cbf79e33 100644 --- a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi @@ -31,7 +31,7 @@ u-boot,dm-pre-reloc; display0: display@0 { - bits-per-pixel = <16>; + bits-per-pixel = <24>; bus-width = <24>; display-timings { From 229f078512a329a9606eb341bccb8e56ead11014 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Sat, 1 Feb 2020 15:29:45 +0100 Subject: [PATCH 09/23] configs: imxrt1050-evk: enable D/I cache Soc supports cache so let's enable it. Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 102e663886..71970552c0 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -1,6 +1,4 @@ CONFIG_ARM=y -CONFIG_SYS_ICACHE_OFF=y -CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_IMXRT=y CONFIG_SYS_TEXT_BASE=0x80002000 CONFIG_SPL_GPIO_SUPPORT=y From 827f0a3f228ace3edbd1fd73c1cf73560724b034 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 19 Feb 2020 09:56:28 -0300 Subject: [PATCH 10/23] mx6sxsabresd: Enable DM_PCI Enale DM_PCI support in order to avoid board removal from the project. Signed-off-by: Fabio Estevam --- configs/mx6sxsabresd_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 5150e3a837..7cf672948d 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -51,6 +51,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_DM_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y From 789ddde11326a5afc64e8ccad5b3fc2694005afc Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Wed, 26 Feb 2020 12:15:24 +0000 Subject: [PATCH 11/23] imx: Makefile: added missing ahab.o added missing ahab.o in Makefile Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Simon Glass Cc: Ye Li Cc: uboot-imx Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/imx8/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 39e384d5c7..7ffb7e95b2 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -6,6 +6,7 @@ obj-y += cpu.o iomux.o misc.o lowlevel_init.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o +obj-$(CONFIG_AHAB_BOOT) += ahab.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o From 064e49ff5e433235ab10b2c29885be7039c1d719 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Tue, 4 Feb 2020 18:57:08 +0200 Subject: [PATCH 12/23] mx6cuboxi: don't disable fdt relocation fdt_high value of 0xffffffff disables fdt relocation on boot. We don't need that for Cubox-i/Hummingboard. Rely on generic code to find the optimal fdt location at boot time. Signed-off-by: Baruch Siach --- include/configs/mx6cuboxi.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 6d47e28fc7..a6690367f8 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -66,7 +66,6 @@ "ramdisk_addr_r=0x13000000\0" \ "ramdiskaddr=0x13000000\0" \ "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ "ip_dyn=yes\0" \ "console=" CONSOLE_DEV ",115200\0" \ "bootm_size=0x10000000\0" \ From 291e3ab9044f65209043195ca22a97626d3402f7 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 5 Feb 2020 11:45:28 +0000 Subject: [PATCH 13/23] imx8mm/mn: Add missing root clock entry for ARM core clock The current implementation in arch/arm/mach-imx/cpu.c uses non-DM code to retrieve the core clock frequency. As the root clock is not listed we currently get: CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz Fix this by adding the missing entry, which results in: CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz Signed-off-by: Frieder Schrempf Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/imx8m/clock_slice.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c index 31925ccaba..8b7a4dad65 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c +++ b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -477,6 +477,11 @@ static struct clk_root_map root_array[] = { }; #elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) static struct clk_root_map root_array[] = { + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0, + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK} + }, {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2, {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK, From 289dd9f0720dbbefd6092b9388ad60cc42cb358a Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 31 Jan 2020 14:39:47 +0100 Subject: [PATCH 14/23] serial_lpuart: make clock failure less verbose Some device may enable CONFIG_CLK but not still support this clock in CC, so better use debug() in place of dev_warn() otherwise a lot of boards will throw useless dev_warn()s. Signed-off-by: Giulio Benetti Reviewed-by: Simon Glass --- drivers/serial/serial_lpuart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index d7907a228f..3b53f5a97b 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -499,7 +499,7 @@ static int lpuart_serial_probe(struct udevice *dev) return ret; } } else { - dev_warn(dev, "Failed to get per clk: %d\n", ret); + debug("%s: Failed to get per clk: %d\n", __func__, ret); } #endif From 0c45a51970cd3f9b46f50e606da35b6223c47a8d Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Fri, 14 Feb 2020 14:36:43 +0200 Subject: [PATCH 15/23] ARM: dts: imx8mm-verdin: dm-spl for pinctrl_usdhc1 node Let pinctrl configuration for eMMC node (usdhc1) also be accessible in SPL. Signed-off-by: Igor Opaniuk Reviewed-by: Peng Fan Reviewed-by: Oleksandr Suvorov --- arch/arm/dts/imx8mm-verdin-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi index d091577a96..e60b9faee4 100644 --- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi @@ -69,6 +69,10 @@ u-boot,dm-spl; }; +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + &pinctrl_usdhc2 { u-boot,dm-spl; }; From d40aa43f3f25e407cb12236b6171a186491d2f11 Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Fri, 14 Feb 2020 14:36:44 +0200 Subject: [PATCH 16/23] ARM: dts: imx8mm-verdin: drop rgmii_rxc_dly/txc_dly The FEC in the i.MX8MM doesn't support this feature. So don't pretend one can use it. Signed-off-by: Max Krummenacher Signed-off-by: Igor Opaniuk Acked-by: Peng Fan Reviewed-by: Oleksandr Suvorov --- arch/arm/dts/imx8mm-verdin.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/imx8mm-verdin.dts b/arch/arm/dts/imx8mm-verdin.dts index 2980053e82..b86f46e03e 100644 --- a/arch/arm/dts/imx8mm-verdin.dts +++ b/arch/arm/dts/imx8mm-verdin.dts @@ -153,8 +153,6 @@ &fec1 { fsl,magic-packet; - fsl,rgmii_rxc_dly; - fsl,rgmii_txc_dly; phy-handle = <ðphy0>; phy-mode = "rgmii"; phy-supply = <®_ethphy>; From d1d78db1dbcb699192bc2251addc0b6a8d32993b Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Thu, 19 Dec 2019 14:25:53 +0000 Subject: [PATCH 17/23] imx: imx8qm_rom7720: added missing USDHC Base address defines Added missing USDHC Base address defines Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Simon Glass Cc: Ye Li Cc: uboot-imx Reviewed-by: Fabio Estevam --- include/configs/imx8qm_rom7720.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 865863eb7c..8e1427da8a 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -18,6 +18,10 @@ #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_ENV_OVERWRITE From 02ee7a4aa57b37d6003263b69b1852c4cda5975e Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Mon, 10 Feb 2020 11:28:01 -0300 Subject: [PATCH 18/23] mx6sabresd: Convert ethernet to driver model Convert imx6sabresd ethernet to driver model to fix the following warning: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Alifer Moraes Reviewed-by: Fabio Estevam --- board/freescale/mx6sabresd/mx6sabresd.c | 36 ------------------------- configs/mx6sabresd_defconfig | 5 ++++ include/configs/mx6sabresd.h | 9 ------- 3 files changed, 5 insertions(+), 45 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 4a208277ac..07d3b0edb3 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include @@ -44,9 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) @@ -73,31 +69,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* AR8031 PHY Reset */ - IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; - -static void setup_iomux_enet(void) -{ - SETUP_IOMUX_PADS(enet_pads); -} - static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -495,13 +466,6 @@ int overwrite_console(void) return 1; } -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - - return cpu_eth_init(bis); -} - #ifdef CONFIG_USB_EHCI_MX6 static void setup_usb(void) { diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 8629554fba..f218408832 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -81,6 +81,11 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_PCI=y diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index d810202117..ec1537541a 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -62,13 +62,4 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 - -#define CONFIG_PHY_ATHEROS - - #endif /* __MX6SABRESD_CONFIG_H */ From a604b67b877371e6d62b7ec30c858d964c3d4b93 Mon Sep 17 00:00:00 2001 From: Alifer Moraes Date: Fri, 14 Feb 2020 16:18:50 -0300 Subject: [PATCH 19/23] arm: dts: imx8mq-evk: add phy-reset-gpios for fec1 Instead of resetting the ethernet phy through functions in imx8mq_evk.c, let the driver reset the phy via dts description adding a reset duration of 10 ms following atheros 8031's datasheet recommendation. Signed-off-by: Alifer Moraes --- arch/arm/dts/imx8mq-evk.dts | 2 ++ board/freescale/imx8mq_evk/imx8mq_evk.c | 18 ------------------ 2 files changed, 2 insertions(+), 18 deletions(-) diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts index 3693933451..55294ba9c8 100644 --- a/arch/arm/dts/imx8mq-evk.dts +++ b/arch/arm/dts/imx8mq-evk.dts @@ -104,6 +104,8 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; fsl,magic-packet; status = "okay"; diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index cb39d0f2d6..b2f464abb1 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -64,29 +64,11 @@ int dram_init(void) } #ifdef CONFIG_FEC_MXC -#define FEC_RST_PAD IMX_GPIO_NR(1, 9) -static iomux_v3_cfg_t const fec1_rst_pads[] = { - IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, - ARRAY_SIZE(fec1_rst_pads)); - - gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); - gpio_direction_output(IMX_GPIO_NR(1, 9), 0); - udelay(500); - gpio_direction_output(IMX_GPIO_NR(1, 9), 1); -} - static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - setup_iomux_fec(); - /* Use 125M anatop REF_CLK1 for ENET1, not from external */ clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); return set_clk_enet(ENET_125MHZ); From 182716371bd4f5008ca9f1884c97c8ca1c30f709 Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Wed, 12 Feb 2020 12:01:17 +0000 Subject: [PATCH 20/23] imx: imx8qm: enable relocation of fdt and initrd Set CONFIG_SYS_BOOTMAPSZ to the amount of memory available which is needed to relocate the kernel, device tree and initrd. Remove 'fdt_high' and 'initrd_high' environment variables from default environment which prevents relocation of FDT and initrd. Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Simon Glass Cc: Ye Li Cc: uboot-imx Reviewed-by: Tom Rini --- include/configs/imx8qm_rom7720.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 8e1427da8a..ac25549a18 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -17,6 +17,7 @@ #undef CONFIG_BOOTM_NETBSD #define CONFIG_FSL_USDHC +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 @@ -67,11 +68,9 @@ "panel=NULL\0" \ "console=ttyLP0\0" \ "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ "fdt_file=imx8qm-rom7720-a1.dtb\0" \ "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ From 60559d35751c57de61a6720265cc6b8a09d692ed Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 18 Feb 2020 16:09:59 -0300 Subject: [PATCH 21/23] mx7dsabresd: Boot in non secure by default Booting a mainline kernel in secure mode on i.MX7D causes only one CPU to be brought up. Change it to booting in non secure mode by default, which allows the two CPUs to be brought up. It does have a side effect of not probing the CAAM driver. If CAAM driver is needed then a secure world OS such as OPTEE needs to be used. Signed-off-by: Fabio Estevam --- configs/mx7dsabresd_defconfig | 1 - configs/mx7dsabresd_qspi_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 02f1d2a115..e948091a92 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -6,7 +6,6 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y CONFIG_TARGET_MX7DSABRESD=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 9d6a598c99..23a1c45837 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -6,7 +6,6 @@ CONFIG_ENV_OFFSET=0xC0000 CONFIG_DM_GPIO=y CONFIG_TARGET_MX7DSABRESD=y CONFIG_NR_DRAM_BANKS=1 -CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y From 905dbe23b92cd9a6631091546f206b602c958750 Mon Sep 17 00:00:00 2001 From: Pedro Jardim Date: Thu, 13 Feb 2020 14:59:43 -0300 Subject: [PATCH 22/23] mx6sabreauto: Convert to DM_ETH This fixes the following warning: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Pedro Jardim Reviewed-by: Fabio Estevam --- board/freescale/mx6sabreauto/mx6sabreauto.c | 42 --------------------- configs/mx6sabreauto_defconfig | 5 +++ include/configs/mx6sabreauto.h | 8 ---- 3 files changed, 5 insertions(+), 50 deletions(-) diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index 140f24459d..de19a562eb 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -76,23 +75,6 @@ static iomux_v3_cfg_t const uart4_pads[] = { IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), -}; /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ static struct i2c_pads_info mx6q_i2c_pad_info1 = { @@ -259,10 +241,6 @@ static void setup_iomux_eimnor(void) } #endif -static void setup_iomux_enet(void) -{ - SETUP_IOMUX_PADS(enet_pads); -} static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -340,26 +318,6 @@ static void setup_gpmi_nand(void) } #endif -static void setup_fec(void) -{ - if (is_mx6dqp()) { - /* - * select ENET MAC0 TX clock from PLL - */ - imx_iomux_set_gpr_register(5, 9, 1, 1); - enable_fec_anatop_clock(0, ENET_125MHZ); - } - - setup_iomux_enet(); -} - -int board_eth_init(bd_t *bis) -{ - setup_fec(); - - return cpu_eth_init(bis); -} - u32 get_board_rev(void) { int rev = nxp_board_rev(); diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 723e1c32d8..06835f203a 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -97,3 +97,8 @@ CONFIG_DM_VIDEO=y # CONFIG_VIDEO_BPP32 is not set CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_VIDEO_IPUV3=y +CONFIG_FEC_MXC=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_RGMII=y diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index c07b03984a..e444930dc8 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -75,12 +75,4 @@ #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 - -#define CONFIG_PHY_ATHEROS - #endif /* __MX6SABREAUTO_CONFIG_H */ From 9f656fbee3b433ae1e9daf5d92d46bbdcc9551eb Mon Sep 17 00:00:00 2001 From: Pedro Jardim Date: Thu, 13 Feb 2020 09:25:32 -0300 Subject: [PATCH 23/23] mx6slevk: Convert to DM_ETH This fixes the following warning: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Signed-off-by: Pedro Jardim Reviewed-by: Fabio Estevam --- board/freescale/mx6slevk/mx6slevk.c | 31 ----------------------------- configs/mx6slevk_defconfig | 3 +++ include/configs/mx6slevk.h | 7 ------- 3 files changed, 3 insertions(+), 38 deletions(-) diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 453f281418..43029e4245 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include "../common/pfuze.h" @@ -102,35 +101,11 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { }; #endif -static iomux_v3_cfg_t const fec_pads[] = { - MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -static void setup_iomux_fec(void) -{ - imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); - - /* Power up LAN8720 PHY */ - gpio_request(ETH_PHY_POWER, "eth_pwr"); - gpio_direction_output(ETH_PHY_POWER , 1); - udelay(15000); -} - int board_mmc_get_env_dev(int devno) { return devno; @@ -179,12 +154,6 @@ int power_init_board(void) #endif #ifdef CONFIG_FEC_MXC -int board_eth_init(bd_t *bis) -{ - setup_iomux_fec(); - - return cpu_eth_init(bis); -} static int setup_fec(void) { diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index dc22e830a3..163cb1a7ae 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -61,3 +61,6 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_PHY_SMSC=y diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 6b2a174e7a..193931b91b 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -32,13 +32,6 @@ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PHY_SMSC - #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \