Fix PCI-Express on PPC440SPe rev. A.
This commit is contained in:
committed by
Rafal Jaworowski
parent
692519b1ed
commit
36b904a7fd
@@ -148,30 +148,28 @@ static void ppc440spe_setup_utl(u32 port) {
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*/
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switch (port) {
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case 0:
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mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000d);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x60000400);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xFFFFFC01);
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mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
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utl_base = (unsigned int *)(CFG_PCIE1_REGBASE);
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break;
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case 1:
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mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000d);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x60001400);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xFFFFFC01);
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mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
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utl_base = (unsigned int *)(CFG_PCIE3_REGBASE);
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break;
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case 2:
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mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000d);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x60002400);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0xFFFFFC01);
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mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
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mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
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mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
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mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
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utl_base = (unsigned int *)(CFG_PCIE5_REGBASE);
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break;
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}
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utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
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/*
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* Set buffer allocations and then assert VRB and TXE.
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*/
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@@ -182,7 +180,7 @@ static void ppc440spe_setup_utl(u32 port) {
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out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
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out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
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out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
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out_be32(utl_base + PEUTL_PCTL, 0x8080007d);
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out_be32(utl_base + PEUTL_PCTL, 0x80800066);
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}
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static int check_error(void)
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@@ -420,6 +418,7 @@ int ppc440spe_init_pcie_rootport(int port)
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* PCIE1: 0xd_2000_0000
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* PCIE2: 0xd_4000_0000
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*/
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switch (port) {
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case 0:
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if (ppc440spe_revB()) {
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