From 6500c5760ccf8dffbb21cd74df8eabffb13d70dd Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Mon, 11 Jul 2022 19:45:50 +0200 Subject: [PATCH 01/21] configs: stm32m15: support STM32MP_BOARD_EXTRA_ENV for st boards Correctly handle STM32MP_BOARD_EXTRA_ENV define in stm32mp15_st_common.h; the STM32MP_BOARD_EXTRA_ENV is added in CONFIG_EXTRA_ENV_SETTINGS definition, as it is done "stm32mp15_st_common.h" Without this patch, the content of STM32MP_BOARD_EXTRA_ENV is not used in the default environment for STMicroelectronics boards. Fixes: 806c4dd31532 ("configs: stm32mp1: set the console variable for extlinux.conf") Reported-by: Gatien CHEVALLIER Signed-off-by: Patrick Delaunay --- include/configs/stm32mp15_st_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 37b216e6e9..6bdc286cfc 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -48,7 +48,8 @@ ST_STM32MP1_BOOTCMD \ STM32MP_PARTS_DEFAULT \ BOOTENV \ - STM32MP_EXTRA + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV #endif #endif From 0b69ce6a816c39502941deb90543e23619e02896 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 6 Jul 2022 18:20:24 +0200 Subject: [PATCH 02/21] ARM: dts: stm32mp13: add OP-TEE nodes Add the node for OP-TEE firmware with the associated reserved memory nodes Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-u-boot.dtsi | 4 ++++ arch/arm/dts/stm32mp131.dtsi | 7 +++++++ arch/arm/dts/stm32mp135f-dk.dts | 11 +++++++++++ 3 files changed, 22 insertions(+) diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 1b5b358690..adc7e67ee5 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -82,6 +82,10 @@ u-boot,dm-pre-reloc; }; +&optee { + u-boot,dm-pre-reloc; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 950e172e45..652743fd06 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -27,6 +27,13 @@ interrupt-parent = <&intc>; }; + firmware { + optee: optee { + method = "smc"; + compatible = "linaro,optee-tz"; + }; + }; + clocks { clk_axi: clk-axi { #clock-cells = <0>; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index ee100d108e..31c510f976 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -23,6 +23,17 @@ reg = <0xc0000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; From 44db098ae1d91bde3bd52097ab3a1a52f5b4ed84 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 6 Jul 2022 18:20:25 +0200 Subject: [PATCH 03/21] ARM: dts: stm32mp13: add SCMI nodes Add the node for SCMI firmware with the associated reserved memory nodes Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp13-u-boot.dtsi | 20 +++++++++++++++++++ arch/arm/dts/stm32mp131.dtsi | 31 ++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index adc7e67ee5..01552adb7c 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -90,6 +90,26 @@ u-boot,dm-pre-reloc; }; +&scmi { + u-boot,dm-pre-reloc; +}; + +&scmi_clk { + u-boot,dm-pre-reloc; +}; + +&scmi_reset { + u-boot,dm-pre-reloc; +}; + +&scmi_shm { + u-boot,dm-pre-reloc; +}; + +&scmi_sram { + u-boot,dm-pre-reloc; +}; + &syscfg { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 652743fd06..8f7af65e3e 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -27,11 +27,42 @@ interrupt-parent = <&intc>; }; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi_shm@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + firmware { optee: optee { method = "smc"; compatible = "linaro,optee-tz"; }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; }; clocks { From 5f1e6b639b47eea5177b1128c384da76dce2dbe6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:01:45 +0200 Subject: [PATCH 04/21] mmc: stm32_sdmmc2: cosmetic: rename stm32_sdmmc_bind Rename stm32_sdmmc_bind to stm32_sdmmc2_bind as all other functions in SDMMCv2 driver Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard Change-Id: Ic51acdfbbba6e971809c1029dd2227038bfe879d --- drivers/mmc/stm32_sdmmc2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 81b07609a9..e3853b7fbf 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -763,7 +763,7 @@ clk_free: return ret; } -static int stm32_sdmmc_bind(struct udevice *dev) +static int stm32_sdmmc2_bind(struct udevice *dev) { struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); @@ -781,7 +781,7 @@ U_BOOT_DRIVER(stm32_sdmmc2) = { .of_match = stm32_sdmmc2_ids, .ops = &stm32_sdmmc2_ops, .probe = stm32_sdmmc2_probe, - .bind = stm32_sdmmc_bind, + .bind = stm32_sdmmc2_bind, .priv_auto = sizeof(struct stm32_sdmmc2_priv), .plat_auto = sizeof(struct stm32_sdmmc2_plat), }; From efd77dbca304d6cceb40675365485d84cce40ccd Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:01:46 +0200 Subject: [PATCH 05/21] mmc: stm32_sdmmc2: remove privdata All the elements of privdata are static and build from device tree, they are moved in platdata to prepare the support of ops of_to_plat. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/mmc/stm32_sdmmc2.c | 145 ++++++++++++++++++------------------- 1 file changed, 70 insertions(+), 75 deletions(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index e3853b7fbf..41f375b9d3 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -30,9 +30,6 @@ struct stm32_sdmmc2_plat { struct mmc_config cfg; struct mmc mmc; -}; - -struct stm32_sdmmc2_priv { fdt_addr_t base; struct clk clk; struct reset_ctl reset_ctl; @@ -208,7 +205,7 @@ static void stm32_sdmmc2_start_data(struct udevice *dev, struct mmc_data *data, struct stm32_sdmmc2_ctx *ctx) { - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); u32 data_ctrl, idmabase0; /* Configure the SDMMC DPSM (Data Path State Machine) */ @@ -224,10 +221,10 @@ static void stm32_sdmmc2_start_data(struct udevice *dev, } /* Set the SDMMC DataLength value */ - writel(ctx->data_length, priv->base + SDMMC_DLEN); + writel(ctx->data_length, plat->base + SDMMC_DLEN); /* Write to SDMMC DCTRL */ - writel(data_ctrl, priv->base + SDMMC_DCTRL); + writel(data_ctrl, plat->base + SDMMC_DCTRL); /* Cache align */ ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN); @@ -242,19 +239,19 @@ static void stm32_sdmmc2_start_data(struct udevice *dev, flush_dcache_range(ctx->cache_start, ctx->cache_end); /* Enable internal DMA */ - writel(idmabase0, priv->base + SDMMC_IDMABASE0); - writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL); + writel(idmabase0, plat->base + SDMMC_IDMABASE0); + writel(SDMMC_IDMACTRL_IDMAEN, plat->base + SDMMC_IDMACTRL); } static void stm32_sdmmc2_start_cmd(struct udevice *dev, struct mmc_cmd *cmd, u32 cmd_param, struct stm32_sdmmc2_ctx *ctx) { - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); u32 timeout = 0; - if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN) - writel(0, priv->base + SDMMC_CMD); + if (readl(plat->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN) + writel(0, plat->base + SDMMC_CMD); cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN; if (cmd->resp_type & MMC_RSP_PRESENT) { @@ -277,30 +274,30 @@ static void stm32_sdmmc2_start_cmd(struct udevice *dev, if (ctx->data_length) { timeout = SDMMC_CMD_TIMEOUT; } else { - writel(0, priv->base + SDMMC_DCTRL); + writel(0, plat->base + SDMMC_DCTRL); if (cmd->resp_type & MMC_RSP_BUSY) timeout = SDMMC_CMD_TIMEOUT; } /* Set the SDMMC Data TimeOut value */ - writel(timeout, priv->base + SDMMC_DTIMER); + writel(timeout, plat->base + SDMMC_DTIMER); /* Clear flags */ - writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); + writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR); /* Set SDMMC argument value */ - writel(cmd->cmdarg, priv->base + SDMMC_ARG); + writel(cmd->cmdarg, plat->base + SDMMC_ARG); /* Set SDMMC command parameters */ - writel(cmd_param, priv->base + SDMMC_CMD); + writel(cmd_param, plat->base + SDMMC_CMD); } static int stm32_sdmmc2_end_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct stm32_sdmmc2_ctx *ctx) { - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); u32 mask = SDMMC_STA_CTIMEOUT; u32 status; int ret; @@ -314,7 +311,7 @@ static int stm32_sdmmc2_end_cmd(struct udevice *dev, } /* Polling status register */ - ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask, + ret = readl_poll_timeout(plat->base + SDMMC_STA, status, status & mask, 10000); if (ret < 0) { @@ -339,11 +336,11 @@ static int stm32_sdmmc2_end_cmd(struct udevice *dev, } if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) { - cmd->response[0] = readl(priv->base + SDMMC_RESP1); + cmd->response[0] = readl(plat->base + SDMMC_RESP1); if (cmd->resp_type & MMC_RSP_136) { - cmd->response[1] = readl(priv->base + SDMMC_RESP2); - cmd->response[2] = readl(priv->base + SDMMC_RESP3); - cmd->response[3] = readl(priv->base + SDMMC_RESP4); + cmd->response[1] = readl(plat->base + SDMMC_RESP2); + cmd->response[2] = readl(plat->base + SDMMC_RESP3); + cmd->response[3] = readl(plat->base + SDMMC_RESP4); } /* Wait for BUSYD0END flag if busy status is detected */ @@ -352,7 +349,7 @@ static int stm32_sdmmc2_end_cmd(struct udevice *dev, mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END; /* Polling status register */ - ret = readl_poll_timeout(priv->base + SDMMC_STA, + ret = readl_poll_timeout(plat->base + SDMMC_STA, status, status & mask, SDMMC_BUSYD0END_TIMEOUT_US); @@ -380,7 +377,7 @@ static int stm32_sdmmc2_end_data(struct udevice *dev, struct mmc_data *data, struct stm32_sdmmc2_ctx *ctx) { - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT | SDMMC_STA_IDMATE | SDMMC_STA_DATAEND; u32 status; @@ -390,9 +387,9 @@ static int stm32_sdmmc2_end_data(struct udevice *dev, else mask |= SDMMC_STA_TXUNDERR; - status = readl(priv->base + SDMMC_STA); + status = readl(plat->base + SDMMC_STA); while (!(status & mask)) - status = readl(priv->base + SDMMC_STA); + status = readl(plat->base + SDMMC_STA); /* * Need invalidate the dcache again to avoid any @@ -404,7 +401,7 @@ static int stm32_sdmmc2_end_data(struct udevice *dev, if (status & SDMMC_STA_DCRCFAIL) { dev_dbg(dev, "error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n", status, cmd->cmdidx); - if (readl(priv->base + SDMMC_DCOUNT)) + if (readl(plat->base + SDMMC_DCOUNT)) ctx->dpsm_abort = true; return -EILSEQ; } @@ -443,7 +440,7 @@ static int stm32_sdmmc2_end_data(struct udevice *dev, static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) { - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); struct stm32_sdmmc2_ctx ctx; u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0; int ret, retry = 3; @@ -470,9 +467,9 @@ retry_cmd: ret = stm32_sdmmc2_end_data(dev, cmd, data, &ctx); /* Clear flags */ - writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); + writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR); if (data) - writel(0x0, priv->base + SDMMC_IDMACTRL); + writel(0x0, plat->base + SDMMC_IDMACTRL); /* * To stop Data Path State Machine, a stop_transmission command @@ -493,7 +490,7 @@ retry_cmd: SDMMC_CMD_CMDSTOP, &ctx); stm32_sdmmc2_end_cmd(dev, &stop_cmd, &ctx); - writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); + writel(SDMMC_ICR_STATIC_FLAGS, plat->base + SDMMC_ICR); } if ((ret != -ETIMEDOUT) && (ret != 0) && retry) { @@ -512,17 +509,17 @@ retry_cmd: * This will reset the SDMMC to the reset state and the CPSM and DPSM * to the Idle state. SDMMC is disabled, Signals Hiz. */ -static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv) +static void stm32_sdmmc2_reset(struct stm32_sdmmc2_plat *plat) { - if (reset_valid(&priv->reset_ctl)) { + if (reset_valid(&plat->reset_ctl)) { /* Reset */ - reset_assert(&priv->reset_ctl); + reset_assert(&plat->reset_ctl); udelay(2); - reset_deassert(&priv->reset_ctl); + reset_deassert(&plat->reset_ctl); } /* init the needed SDMMC register after reset */ - writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER); + writel(plat->pwr_reg_msk, plat->base + SDMMC_POWER); } /* @@ -531,13 +528,13 @@ static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv) * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being * supplied through the signal lines. */ -static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv) +static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_plat *plat) { - if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) == + if ((readl(plat->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) == SDMMC_POWER_PWRCTRL_CYCLE) return; - stm32_sdmmc2_reset(priv); + stm32_sdmmc2_reset(plat); } /* @@ -546,10 +543,10 @@ static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv) * Reset => Power-Cycle => Power-Off => Power * PWRCTRL=10 PWCTRL=00 PWCTRL=11 */ -static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv) +static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_plat *plat) { u32 pwrctrl = - readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK; + readl(plat->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK; if (pwrctrl == SDMMC_POWER_PWRCTRL_ON) return; @@ -558,21 +555,21 @@ static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv) * it is the reset state here = the only managed by the driver */ if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) { - writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk, - priv->base + SDMMC_POWER); + writel(SDMMC_POWER_PWRCTRL_CYCLE | plat->pwr_reg_msk, + plat->base + SDMMC_POWER); } /* * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE * switch to Power-Off state: SDMCC disable, signals drive 1 */ - writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk, - priv->base + SDMMC_POWER); + writel(SDMMC_POWER_PWRCTRL_OFF | plat->pwr_reg_msk, + plat->base + SDMMC_POWER); /* After the 1ms delay set the SDMMC to power-on */ mdelay(1); - writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk, - priv->base + SDMMC_POWER); + writel(SDMMC_POWER_PWRCTRL_ON | plat->pwr_reg_msk, + plat->base + SDMMC_POWER); /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */ } @@ -581,18 +578,18 @@ static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv) static int stm32_sdmmc2_set_ios(struct udevice *dev) { struct mmc *mmc = mmc_get_mmc_dev(dev); - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); u32 desired = mmc->clock; - u32 sys_clock = clk_get_rate(&priv->clk); + u32 sys_clock = clk_get_rate(&plat->clk); u32 clk = 0; dev_dbg(dev, "bus_with = %d, clock = %d\n", mmc->bus_width, mmc->clock); if (mmc->clk_disable) - stm32_sdmmc2_pwrcycle(priv); + stm32_sdmmc2_pwrcycle(plat); else - stm32_sdmmc2_pwron(priv); + stm32_sdmmc2_pwron(plat); /* * clk_div = 0 => command and data generated on SDMMCCLK falling edge @@ -602,7 +599,7 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) * SDMMCCLK falling edge */ if (desired && ((sys_clock > desired) || - IS_RISING_EDGE(priv->clk_reg_msk))) { + IS_RISING_EDGE(plat->clk_reg_msk))) { clk = DIV_ROUND_UP(sys_clock, 2 * desired); if (clk > SDMMC_CLKCR_CLKDIV_MAX) clk = SDMMC_CLKCR_CLKDIV_MAX; @@ -613,30 +610,30 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) if (mmc->bus_width == 8) clk |= SDMMC_CLKCR_WIDBUS_8; - writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN, - priv->base + SDMMC_CLKCR); + writel(clk | plat->clk_reg_msk | SDMMC_CLKCR_HWFC_EN, + plat->base + SDMMC_CLKCR); return 0; } static int stm32_sdmmc2_getcd(struct udevice *dev) { - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); dev_dbg(dev, "%s called\n", __func__); - if (dm_gpio_is_valid(&priv->cd_gpio)) - return dm_gpio_get_value(&priv->cd_gpio); + if (dm_gpio_is_valid(&plat->cd_gpio)) + return dm_gpio_get_value(&plat->cd_gpio); return 1; } static int stm32_sdmmc2_host_power_cycle(struct udevice *dev) { - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); - writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk, - priv->base + SDMMC_POWER); + writel(SDMMC_POWER_PWRCTRL_CYCLE | plat->pwr_reg_msk, + plat->base + SDMMC_POWER); return 0; } @@ -650,7 +647,7 @@ static const struct dm_mmc_ops stm32_sdmmc2_ops = { static int stm32_sdmmc2_probe_level_translator(struct udevice *dev) { - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); struct gpio_desc cmd_gpio; struct gpio_desc ck_gpio; struct gpio_desc ckin_gpio; @@ -660,7 +657,7 @@ static int stm32_sdmmc2_probe_level_translator(struct udevice *dev) * Assume the level translator is present if st,use-ckin is set. * This is to cater for DTs which do not implement this test. */ - priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN; + plat->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN; ret = gpio_request_by_name(dev, "st,cmd-gpios", 0, &cmd_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); @@ -694,7 +691,7 @@ static int stm32_sdmmc2_probe_level_translator(struct udevice *dev) /* Level translator is present if CK signal is propagated to CKIN */ if (!clk_hi || clk_lo) - priv->clk_reg_msk &= ~SDMMC_CLKCR_SELCLKRX_CKIN; + plat->clk_reg_msk &= ~SDMMC_CLKCR_SELCLKRX_CKIN; dm_gpio_free(dev, &ckin_gpio); @@ -712,34 +709,33 @@ static int stm32_sdmmc2_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); - struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; int ret; - priv->base = dev_read_addr(dev); - if (priv->base == FDT_ADDR_T_NONE) + plat->base = dev_read_addr(dev); + if (plat->base == FDT_ADDR_T_NONE) return -EINVAL; if (dev_read_bool(dev, "st,neg-edge")) - priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; + plat->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; if (dev_read_bool(dev, "st,sig-dir")) - priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL; + plat->pwr_reg_msk |= SDMMC_POWER_DIRPOL; if (dev_read_bool(dev, "st,use-ckin")) stm32_sdmmc2_probe_level_translator(dev); - ret = clk_get_by_index(dev, 0, &priv->clk); + ret = clk_get_by_index(dev, 0, &plat->clk); if (ret) return ret; - ret = clk_enable(&priv->clk); + ret = clk_enable(&plat->clk); if (ret) goto clk_free; - ret = reset_get_by_index(dev, 0, &priv->reset_ctl); + ret = reset_get_by_index(dev, 0, &plat->reset_ctl); if (ret) dev_dbg(dev, "No reset provided\n"); - gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, + gpio_request_by_name(dev, "cd-gpios", 0, &plat->cd_gpio, GPIOD_IS_IN); cfg->f_min = 400000; @@ -754,11 +750,11 @@ static int stm32_sdmmc2_probe(struct udevice *dev) upriv->mmc = &plat->mmc; /* SDMMC init */ - stm32_sdmmc2_reset(priv); + stm32_sdmmc2_reset(plat); return 0; clk_free: - clk_free(&priv->clk); + clk_free(&plat->clk); return ret; } @@ -782,6 +778,5 @@ U_BOOT_DRIVER(stm32_sdmmc2) = { .ops = &stm32_sdmmc2_ops, .probe = stm32_sdmmc2_probe, .bind = stm32_sdmmc2_bind, - .priv_auto = sizeof(struct stm32_sdmmc2_priv), .plat_auto = sizeof(struct stm32_sdmmc2_plat), }; From cb8edb996bf20be09b88b2b17520beec433067cd Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:01:47 +0200 Subject: [PATCH 06/21] mmc: stm32_sdmmc2: introduce of_to_plat ops Add the uclass ops of_to_plat to parse the device tree properties to respect the expected sequence by the driver model. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/mmc/stm32_sdmmc2.c | 95 ++++++++++++++++++++------------------ 1 file changed, 50 insertions(+), 45 deletions(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 41f375b9d3..bfce8a2e4a 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -645,6 +645,47 @@ static const struct dm_mmc_ops stm32_sdmmc2_ops = { .host_power_cycle = stm32_sdmmc2_host_power_cycle, }; +static int stm32_sdmmc2_of_to_plat(struct udevice *dev) +{ + struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); + struct mmc_config *cfg = &plat->cfg; + int ret; + + plat->base = dev_read_addr(dev); + if (plat->base == FDT_ADDR_T_NONE) + return -EINVAL; + + if (dev_read_bool(dev, "st,neg-edge")) + plat->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; + if (dev_read_bool(dev, "st,sig-dir")) + plat->pwr_reg_msk |= SDMMC_POWER_DIRPOL; + if (dev_read_bool(dev, "st,use-ckin")) + plat->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN; + + cfg->f_min = 400000; + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + cfg->name = "STM32 SD/MMC"; + cfg->host_caps = 0; + cfg->f_max = 52000000; + ret = mmc_of_parse(dev, cfg); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 0, &plat->clk); + if (ret) + return ret; + + ret = reset_get_by_index(dev, 0, &plat->reset_ctl); + if (ret) + dev_dbg(dev, "No reset provided\n"); + + gpio_request_by_name(dev, "cd-gpios", 0, &plat->cd_gpio, + GPIOD_IS_IN); + + return 0; +} + static int stm32_sdmmc2_probe_level_translator(struct udevice *dev) { struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); @@ -653,12 +694,6 @@ static int stm32_sdmmc2_probe_level_translator(struct udevice *dev) struct gpio_desc ckin_gpio; int clk_hi, clk_lo, ret; - /* - * Assume the level translator is present if st,use-ckin is set. - * This is to cater for DTs which do not implement this test. - */ - plat->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN; - ret = gpio_request_by_name(dev, "st,cmd-gpios", 0, &cmd_gpio, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); if (ret) @@ -709,54 +744,23 @@ static int stm32_sdmmc2_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); - struct mmc_config *cfg = &plat->cfg; int ret; - plat->base = dev_read_addr(dev); - if (plat->base == FDT_ADDR_T_NONE) - return -EINVAL; - - if (dev_read_bool(dev, "st,neg-edge")) - plat->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; - if (dev_read_bool(dev, "st,sig-dir")) - plat->pwr_reg_msk |= SDMMC_POWER_DIRPOL; - if (dev_read_bool(dev, "st,use-ckin")) - stm32_sdmmc2_probe_level_translator(dev); - - ret = clk_get_by_index(dev, 0, &plat->clk); - if (ret) - return ret; - ret = clk_enable(&plat->clk); - if (ret) - goto clk_free; - - ret = reset_get_by_index(dev, 0, &plat->reset_ctl); - if (ret) - dev_dbg(dev, "No reset provided\n"); - - gpio_request_by_name(dev, "cd-gpios", 0, &plat->cd_gpio, - GPIOD_IS_IN); - - cfg->f_min = 400000; - cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; - cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - cfg->name = "STM32 SD/MMC"; - - cfg->host_caps = 0; - cfg->f_max = 52000000; - mmc_of_parse(dev, cfg); + if (ret) { + clk_free(&plat->clk); + return ret; + } upriv->mmc = &plat->mmc; + if (plat->clk_reg_msk & SDMMC_CLKCR_SELCLKRX_CKIN) + stm32_sdmmc2_probe_level_translator(dev); + /* SDMMC init */ stm32_sdmmc2_reset(plat); + return 0; - -clk_free: - clk_free(&plat->clk); - - return ret; } static int stm32_sdmmc2_bind(struct udevice *dev) @@ -778,5 +782,6 @@ U_BOOT_DRIVER(stm32_sdmmc2) = { .ops = &stm32_sdmmc2_ops, .probe = stm32_sdmmc2_probe, .bind = stm32_sdmmc2_bind, + .of_to_plat = stm32_sdmmc2_of_to_plat, .plat_auto = sizeof(struct stm32_sdmmc2_plat), }; From 69ef98b209e7e392d4a31d99cb4fa249f8a58ac0 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 5 Jul 2022 16:55:54 +0200 Subject: [PATCH 07/21] ARM: dts: stm32mp15: alignment with v5.19 Device tree alignment with Linux kernel v5.19-rc1 - ARM: dts: stm32: Add alternate pinmux for ethernet0 pins - ARM: dts: stm32: Add alternate pinmux for mco2 pins - ARM: dts: stm32: fix pinctrl node name warnings (MPU soc) - ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group - dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 - dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 - dt-bindings: clock: stm32mp15: rename CK_SCMI define - dt-bindings: reset: stm32mp15: rename RST_SCMI define - dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 - dt-bindings: clk: cleanup comments - ARM: dts: align SPI NOR node name with dtschema - ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15 - ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 + patch from stm32-dt-for-v5.19-fixes-2 - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 - ARM: dts: stm32: fix pwr regulators references to use scmi - ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 - ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board - ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI - ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15 Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp15-pinctrl.dtsi | 64 ++++++++++++ arch/arm/dts/stm32mp15-scmi.dtsi | 109 ++++++++++++++++++++ arch/arm/dts/stm32mp151.dtsi | 10 +- arch/arm/dts/stm32mp157a-dk1-scmi.dts | 79 ++++++++++++++ arch/arm/dts/stm32mp157c-dk2-scmi.dts | 85 +++++++++++++++ arch/arm/dts/stm32mp157c-ed1-scmi.dts | 84 +++++++++++++++ arch/arm/dts/stm32mp157c-ev1-scmi.dts | 90 ++++++++++++++++ arch/arm/dts/stm32mp157c-ev1.dts | 4 +- include/dt-bindings/clock/stm32fx-clock.h | 4 +- include/dt-bindings/clock/stm32mp1-clks.h | 23 +++++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 + include/dt-bindings/reset/stm32mp1-resets.h | 14 +++ 12 files changed, 558 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/stm32mp15-scmi.dtsi create mode 100644 arch/arm/dts/stm32mp157a-dk1-scmi.dts create mode 100644 arch/arm/dts/stm32mp157c-dk2-scmi.dts create mode 100644 arch/arm/dts/stm32mp157c-ed1-scmi.dts create mode 100644 arch/arm/dts/stm32mp157c-ev1-scmi.dts diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index b92a149a18..d3ed10335d 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -379,6 +379,40 @@ }; }; + ethernet0_rmii_pins_c: rmii-2 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ @@ -889,6 +923,21 @@ }; }; + mco2_pins_a: mco2-0 { + pins { + pinmux = ; /* MCO2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + mco2_sleep_pins_a: mco2-sleep-0 { + pins { + pinmux = ; /* MCO2 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = ; /* CAN1_TX */ @@ -2331,4 +2380,19 @@ bias-disable; }; }; + + spi1_pins_b: spi1-1 { + pins1 { + pinmux = , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI1_MISO */ + bias-disable; + }; + }; }; diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi new file mode 100644 index 0000000000..37d4547b3e --- /dev/null +++ b/arch/arm/dts/stm32mp15-scmi.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_reguls: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_reg11: reg11@0 { + reg = <0>; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + scmi_reg18: reg18@1 { + voltd-name = "reg18"; + reg = <1>; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + scmi_usb33: usb33@2 { + reg = <2>; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; + }; + + soc { + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + }; +}; + +®11 { + status = "disabled"; +}; + +®18 { + status = "disabled"; +}; + +&usb33 { + status = "disabled"; +}; + +&usbotg_hs { + usb33d-supply = <&scmi_usb33>; +}; + +&usbphyc { + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; +}; + +/delete-node/ &clk_hse; +/delete-node/ &clk_hsi; +/delete-node/ &clk_lse; +/delete-node/ &clk_lsi; +/delete-node/ &clk_csi; +/delete-node/ ®11; +/delete-node/ ®18; +/delete-node/ &usb33; +/delete-node/ &pwr_regulators; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index e74a5faf4a..a5ac62c83d 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -583,7 +583,7 @@ compatible = "st,stm32-cec"; reg = <0x40016000 0x400>; interrupts = ; - clocks = <&rcc CEC_K>, <&clk_lse>; + clocks = <&rcc CEC_K>, <&rcc CEC>; clock-names = "cec", "hdmi-cec"; status = "disabled"; }; @@ -1504,7 +1504,7 @@ usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; - clocks = <&rcc USBH>, <&usbphyc>; + clocks = <&usbphyc>, <&rcc USBH>; resets = <&rcc USBH_R>; interrupts = ; status = "disabled"; @@ -1513,7 +1513,7 @@ usbh_ehci: usb@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; - clocks = <&rcc USBH>; + clocks = <&usbphyc>, <&rcc USBH>; resets = <&rcc USBH_R>; interrupts = ; companion = <&usbh_ohci>; @@ -1656,7 +1656,7 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-pinctrl"; @@ -1788,7 +1788,7 @@ }; }; - pinctrl_z: pin-controller-z@54004000 { + pinctrl_z: pinctrl@54004000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dts new file mode 100644 index 0000000000..e539cc80be --- /dev/null +++ b/arch/arm/dts/stm32mp157a-dk1-scmi.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157a-dk1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; + compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dts new file mode 100644 index 0000000000..97e4f94b0a --- /dev/null +++ b/arch/arm/dts/stm32mp157c-dk2-scmi.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-dk2.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; + compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + phy-dsi-supply = <&scmi_reg18>; + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/dts/stm32mp157c-ed1-scmi.dts new file mode 100644 index 0000000000..9cf0a44d2f --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ed1-scmi.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ed1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; + compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dts new file mode 100644 index 0000000000..3b9dd6f4cc --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ev1-scmi.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ev1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; + compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", + "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + phy-dsi-supply = <&scmi_reg18>; + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&m_can1 { + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index e222d2d2cb..d142dd30e1 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -262,7 +262,7 @@ #size-cells = <0>; status = "okay"; - flash0: mx66l51235l@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; @@ -271,7 +271,7 @@ #size-cells = <1>; }; - flash1: mx66l51235l@1 { + flash1: flash@1 { compatible = "jedec,spi-nor"; reg = <1>; spi-rx-bus-width = <4>; diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h index 1cc89c5485..e5dad050d5 100644 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -7,10 +7,10 @@ */ /* - * List of clocks wich are not derived from system clock (SYSCLOCK) + * List of clocks which are not derived from system clock (SYSCLOCK) * * The index of these clocks is the secondary index of DT bindings - * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt) + * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) * * e.g: ; diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 4cdaf13582..25e8cfd434 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,4 +248,27 @@ #define STM32MP1_LAST_CLK 232 +/* SCMI clock identifiers */ +#define CK_SCMI_HSE 0 +#define CK_SCMI_HSI 1 +#define CK_SCMI_CSI 2 +#define CK_SCMI_LSE 3 +#define CK_SCMI_LSI 4 +#define CK_SCMI_PLL2_Q 5 +#define CK_SCMI_PLL2_R 6 +#define CK_SCMI_MPU 7 +#define CK_SCMI_AXI 8 +#define CK_SCMI_BSEC 9 +#define CK_SCMI_CRYP1 10 +#define CK_SCMI_GPIOZ 11 +#define CK_SCMI_HASH1 12 +#define CK_SCMI_I2C4 13 +#define CK_SCMI_I2C6 14 +#define CK_SCMI_IWDG1 15 +#define CK_SCMI_RNG1 16 +#define CK_SCMI_RTC 17 +#define CK_SCMI_RTCAPB 18 +#define CK_SCMI_SPI6 19 +#define CK_SCMI_USART1 20 + #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e6e0780789..e6fb8ada3f 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -39,3 +39,4 @@ #define STM32MP_PKG_AD 0x8 #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ + diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index 702da37a2e..4ffa7c3612 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -106,4 +106,18 @@ #define GPIOJ_R 19785 #define GPIOK_R 19786 +/* SCMI reset domain identifiers */ +#define RST_SCMI_SPI6 0 +#define RST_SCMI_I2C4 1 +#define RST_SCMI_I2C6 2 +#define RST_SCMI_USART1 3 +#define RST_SCMI_STGEN 4 +#define RST_SCMI_GPIOZ 5 +#define RST_SCMI_CRYP1 6 +#define RST_SCMI_HASH1 7 +#define RST_SCMI_RNG1 8 +#define RST_SCMI_MDMA 9 +#define RST_SCMI_MCU 10 +#define RST_SCMI_MCU_HOLD_BOOT 11 + #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ From 43872790d8eeb2055aebc13b09fba3dbb2f8dcaf Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 5 Jul 2022 16:55:55 +0200 Subject: [PATCH 08/21] clk: stm32: add support compatible st, stm32mp1-rcc-secure Add support for new compatible st,stm32mp1-rcc-secure used when the RCC resource is managed by secured world (RCC_TZCR.TZEN=1) iand when SCMI is used. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/misc/stm32_rcc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index b816503bfa..c1e5428a6b 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -84,6 +84,7 @@ static const struct udevice_id stm32_rcc_ids[] = { {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 }, {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 }, {.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 }, + {.compatible = "st,stm32mp1-rcc-secure", .data = (ulong)&stm32_rcc_clk_mp1 }, {.compatible = "st,stm32mp13-rcc", .data = (ulong)&stm32_rcc_clk_mp13 }, { } }; From 7f4de655c0ff460c1a4ee6ea00208327ab54e22d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 5 Jul 2022 16:55:56 +0200 Subject: [PATCH 09/21] configs: stm32mp15: increase malloc size for pre-reloc With support of SCMI in OP-TEE, the early malloc usage increase, the associated defined CONFIG_SYS_MALLOC_F_LEN need to be increased. For example, for stm32mp15_defconfig and stm32mp157c-dk2-scmi.dtsi, we have: Early malloc usage: 14098 / 80000 Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp15_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 3452403c61..e5a2996c2c 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y -CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MALLOC_F_LEN=0x20000 CONFIG_ENV_OFFSET=0x480000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" From 6cccc8d396bfd68bbf695b3b3c92e60b8bdf8b77 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 5 Jul 2022 16:55:57 +0200 Subject: [PATCH 10/21] ARM: dts: stm32: add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) Add a "secure" version of STM32 boards based on SCMI when RCC_TZCR.TZEN=1. Only boards provided by STMicroelectronics are concerned: -STM32MP157A-DK1 -STM32MP157C-DK2 -STM32MP157C-ED1 -STM32MP157C-EV1 The resources secured by RCC_TZCR.TZEN=1 are managed by OP-TEE and the associated SCMI services, reset and clock. These device trees are only supported with stm32mp15_defconfig, with OP-TEE, SCMI and without SPL support. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/Makefile | 4 + arch/arm/dts/stm32mp15-scmi-u-boot.dtsi | 167 ++++++++++++++++++ arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 57 ++++++ arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi | 6 + arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 47 +++++ arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi | 17 ++ doc/board/st/stm32mp1.rst | 19 ++ 7 files changed, 317 insertions(+) create mode 100644 arch/arm/dts/stm32mp15-scmi-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8f7ecfd0f6..0fcd00fb49 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1171,13 +1171,17 @@ dtb-$(CONFIG_STM32MP13x) += \ dtb-$(CONFIG_STM32MP15x) += \ stm32mp157a-dk1.dtb \ + stm32mp157a-dk1-scmi.dtb \ stm32mp157a-icore-stm32mp1-ctouch2.dtb \ stm32mp157a-icore-stm32mp1-edimm2.2.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \ stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \ stm32mp157c-dk2.dtb \ + stm32mp157c-dk2-scmi.dtb \ stm32mp157c-ed1.dtb \ + stm32mp157c-ed1-scmi.dtb \ stm32mp157c-ev1.dtb \ + stm32mp157c-ev1-scmi.dtb \ stm32mp157c-odyssey.dtb \ stm32mp15xx-dhcom-drc02.dtb \ stm32mp15xx-dhcom-pdk2.dtb \ diff --git a/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi new file mode 100644 index 0000000000..314fc39a05 --- /dev/null +++ b/arch/arm/dts/stm32mp15-scmi-u-boot.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + gpio25 = &gpioz; + pinctrl0 = &pinctrl; + pinctrl1 = &pinctrl_z; + }; + + binman: binman { + multiple-images; + }; + + soc { + u-boot,dm-pre-reloc; + + ddr: ddr@5a003000 { + u-boot,dm-pre-reloc; + + compatible = "st,stm32mp1-ddr"; + + reg = <0x5a003000 0x550 + 0x5a004000 0x234>; + + status = "okay"; + }; + }; + + /* need PSCI for sysreset during board_f */ + psci { + u-boot,dm-pre-proper; + }; +}; + +&bsec { + u-boot,dm-pre-reloc; +}; + +&gpioa { + u-boot,dm-pre-reloc; +}; + +&gpiob { + u-boot,dm-pre-reloc; +}; + +&gpioc { + u-boot,dm-pre-reloc; +}; + +&gpiod { + u-boot,dm-pre-reloc; +}; + +&gpioe { + u-boot,dm-pre-reloc; +}; + +&gpiof { + u-boot,dm-pre-reloc; +}; + +&gpiog { + u-boot,dm-pre-reloc; +}; + +&gpioh { + u-boot,dm-pre-reloc; +}; + +&gpioi { + u-boot,dm-pre-reloc; +}; + +&gpioj { + u-boot,dm-pre-reloc; +}; + +&gpiok { + u-boot,dm-pre-reloc; +}; + +&gpioz { + u-boot,dm-pre-reloc; +}; + +&optee { + u-boot,dm-pre-proper; +}; + +&iwdg2 { + u-boot,dm-pre-reloc; +}; + +/* pre-reloc probe = reserve video frame buffer in video_reserve() */ +<dc { + u-boot,dm-pre-proper; +}; + +/* temp = waiting kernel update */ +&m4_rproc { + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl_z { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&scmi { + u-boot,dm-pre-proper; +}; + +&usart1 { + resets = <&rcc USART1_R>; +}; + +&usart2 { + resets = <&rcc USART2_R>; +}; + +&usart3 { + resets = <&rcc USART3_R>; +}; + +&uart4 { + resets = <&rcc UART4_R>; +}; + +&uart5 { + resets = <&rcc UART5_R>; +}; + +&usart6 { + resets = <&rcc USART6_R>; +}; + +&uart7 { + resets = <&rcc UART7_R>; +}; + +&uart8{ + resets = <&rcc UART8_R>; +}; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi new file mode 100644 index 0000000000..2db045e7ce --- /dev/null +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2022 + */ + +#include +#include "stm32mp15-scmi-u-boot.dtsi" +#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" + +/ { + aliases { + i2c3 = &i2c4; + usb0 = &usbotg_hs; + }; + + config { + u-boot,boot-led = "heartbeat"; + u-boot,error-led = "error"; + u-boot,mmc-env-partition = "u-boot-env"; + st,adc_usb_pd = <&adc1 18>, <&adc1 19>; + st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + led { + red { + label = "error"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + status = "okay"; + }; + }; +}; + +&adc { + status = "okay"; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + /* pull-up on rx to avoid floating level */ + bias-pull-up; + }; +}; + +&usbotg_hs { + u-boot,force-b-session-valid; +}; diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi new file mode 100644 index 0000000000..5a8fc15ab2 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2022 + */ + +#include "stm32mp157a-dk1-scmi-u-boot.dtsi" diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi new file mode 100644 index 0000000000..54662f7e29 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2022 + */ + +#include +#include "stm32mp15-scmi-u-boot.dtsi" +#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" + +/ { + aliases { + i2c3 = &i2c4; + }; + + config { + u-boot,boot-led = "heartbeat"; + u-boot,error-led = "error"; + u-boot,mmc-env-partition = "u-boot-env"; + st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + led { + red { + label = "error"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + status = "okay"; + }; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + /* pull-up on rx to avoid floating level */ + bias-pull-up; + }; +}; diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi new file mode 100644 index 0000000000..71a94f9130 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2022 + */ + +#include "stm32mp157c-ed1-scmi-u-boot.dtsi" + +/ { + aliases { + gpio26 = &stmfx_pinctrl; + i2c1 = &i2c2; + i2c4 = &i2c5; + pinctrl2 = &stmfx_pinctrl; + spi0 = &qspi; + usb0 = &usbotg_hs; + }; +}; diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index 00f9b45442..3759df353e 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -77,6 +77,16 @@ Currently the following boards are supported: + stm32mp157c-ev1.dts + stm32mp15xx-dhcor-avenger96.dts +The SCMI variant of each board is supported by a specific "scmi" device tree: + + stm32mp157a-dk1-scmi.dts + + stm32mp157c-dk2-scmi.dts + + stm32mp157c-ed1-scmi.dts + + stm32mp157c-ev1-scmi.dts + +SCMI variant is used only with stm32mp15_defconfig, when the resources are +secured with RCC_TZCR.TZEN=1 in OP-TEE. The access to these reset and clock +resources are provided by OP-TEE and the associated SCMI services. + STM32MP13x `````````` @@ -136,6 +146,9 @@ TF-A_ (BL2) initialize the DDR and loads the next stage binaries from a FIP file the secure monitor to access to secure resources. + HW_CONFIG: The hardware configuration file = the U-Boot device tree +The scmi variant of each device tree is only support with OP-TEE as secure +monitor, with stm32mp15_defconfig. + The **Basic** boot chain with SPL (for STM32MP15x) `````````````````````````````````````````````````` @@ -248,6 +261,12 @@ Build Procedure a) trusted boot with FIP on STM32MP15x ev1:: + # export KBUILD_OUTPUT=stm32mp15 + # make stm32mp15_defconfig + # make DEVICE_TREE=stm32mp157c-ev1-scmi all + + or without SCMI support + # export KBUILD_OUTPUT=stm32mp15 # make stm32mp15_defconfig # make DEVICE_TREE=stm32mp157c-ev1 all From d4d01d0e9998ab1c000ae0d578d33801b31cb845 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:20:14 +0200 Subject: [PATCH 11/21] i2c: stm32: add support for the st,stm32mp13 SOC The stm32mp13 soc differs from the stm32mp15 in terms of clear register offset for controlling the FMP (Fast Mode Plus). Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/i2c/stm32f7_i2c.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index c6ae65badb..bf2a6c9b4b 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -267,6 +267,10 @@ static const struct stm32_i2c_data stm32mp15_data = { .fmp_clr_offset = 0x40, }; +static const struct stm32_i2c_data stm32mp13_data = { + .fmp_clr_offset = 0x4, +}; + static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) { struct stm32_i2c_regs *regs = i2c_priv->regs; @@ -957,6 +961,7 @@ static const struct dm_i2c_ops stm32_i2c_ops = { static const struct udevice_id stm32_i2c_of_match[] = { { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data }, { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data }, + { .compatible = "st,stm32mp13-i2c", .data = (ulong)&stm32mp13_data }, {} }; From 12e11aae2d96d4c437c4c068e440ab4b7f08ceb0 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Thu, 30 Jun 2022 10:20:15 +0200 Subject: [PATCH 12/21] rng: stm32mp1_rng: add conditional reset feature for STM32MP13x New IP adds a conditional reset that impact the clock error management. It is now linked to a new compatible. Signed-off-by: Lionel Debieve Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/rng/stm32mp1_rng.c | 61 +++++++++++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 14 deletions(-) diff --git a/drivers/rng/stm32mp1_rng.c b/drivers/rng/stm32mp1_rng.c index 8ea00e3e89..89da78c6c8 100644 --- a/drivers/rng/stm32mp1_rng.c +++ b/drivers/rng/stm32mp1_rng.c @@ -18,22 +18,28 @@ #include #include -#define RNG_CR 0x00 -#define RNG_CR_RNGEN BIT(2) -#define RNG_CR_CED BIT(5) +#define RNG_CR 0x00 +#define RNG_CR_RNGEN BIT(2) +#define RNG_CR_CED BIT(5) +#define RNG_CR_CONDRST BIT(30) -#define RNG_SR 0x04 -#define RNG_SR_SEIS BIT(6) -#define RNG_SR_CEIS BIT(5) -#define RNG_SR_SECS BIT(2) -#define RNG_SR_DRDY BIT(0) +#define RNG_SR 0x04 +#define RNG_SR_SEIS BIT(6) +#define RNG_SR_CEIS BIT(5) +#define RNG_SR_SECS BIT(2) +#define RNG_SR_DRDY BIT(0) -#define RNG_DR 0x08 +#define RNG_DR 0x08 + +struct stm32_rng_data { + bool has_cond_reset; +}; struct stm32_rng_plat { fdt_addr_t base; struct clk clk; struct reset_ctl rst; + const struct stm32_rng_data *data; }; static int stm32_rng_read(struct udevice *dev, void *data, size_t len) @@ -83,18 +89,36 @@ static int stm32_rng_read(struct udevice *dev, void *data, size_t len) static int stm32_rng_init(struct stm32_rng_plat *pdata) { int err; + u32 cr, sr; err = clk_enable(&pdata->clk); if (err) return err; + cr = readl(pdata->base + RNG_CR); + /* Disable CED */ - writel(RNG_CR_RNGEN | RNG_CR_CED, pdata->base + RNG_CR); + cr |= RNG_CR_CED; + if (pdata->data->has_cond_reset) { + cr |= RNG_CR_CONDRST; + writel(cr, pdata->base + RNG_CR); + cr &= ~RNG_CR_CONDRST; + writel(cr, pdata->base + RNG_CR); + err = readl_poll_timeout(pdata->base + RNG_CR, cr, + (!(cr & RNG_CR_CONDRST)), 10000); + if (err) + return err; + } /* clear error indicators */ writel(0, pdata->base + RNG_SR); - return 0; + cr |= RNG_CR_RNGEN; + writel(cr, pdata->base + RNG_CR); + + err = readl_poll_timeout(pdata->base + RNG_SR, sr, + sr & RNG_SR_DRDY, 10000); + return err; } static int stm32_rng_cleanup(struct stm32_rng_plat *pdata) @@ -108,6 +132,8 @@ static int stm32_rng_probe(struct udevice *dev) { struct stm32_rng_plat *pdata = dev_get_plat(dev); + pdata->data = (struct stm32_rng_data *)dev_get_driver_data(dev); + reset_assert(&pdata->rst); udelay(20); reset_deassert(&pdata->rst); @@ -146,10 +172,17 @@ static const struct dm_rng_ops stm32_rng_ops = { .read = stm32_rng_read, }; +static const struct stm32_rng_data stm32mp13_rng_data = { + .has_cond_reset = true, +}; + +static const struct stm32_rng_data stm32_rng_data = { + .has_cond_reset = false, +}; + static const struct udevice_id stm32_rng_match[] = { - { - .compatible = "st,stm32-rng", - }, + {.compatible = "st,stm32mp13-rng", .data = (ulong)&stm32mp13_rng_data}, + {.compatible = "st,stm32-rng", .data = (ulong)&stm32_rng_data}, {}, }; From 50b371fd68afb3650fc285bca6ae88d639418a16 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:20:16 +0200 Subject: [PATCH 13/21] stm32mp: add support of STM32MP13x Rev.Y Add support of STM32MP13x Rev.Y for the Silicon revision REV_ID = 0x1003. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/include/mach/sys_proto.h | 1 + arch/arm/mach-stm32mp/stm32mp13x.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 4b564e86dc..f19a70e53e 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -41,6 +41,7 @@ u32 get_cpu_dev(void); #define CPU_REV1 0x1000 #define CPU_REV1_1 0x1001 +#define CPU_REV1_2 0x1003 #define CPU_REV2 0x2000 #define CPU_REV2_1 0x2001 diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp13x.c index bd3f24c349..845d973ad1 100644 --- a/arch/arm/mach-stm32mp/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp13x.c @@ -126,6 +126,9 @@ void get_soc_name(char name[SOC_NAME_SIZE]) case CPU_REV1_1: cpu_r = "Z"; break; + case CPU_REV1_2: + cpu_r = "Y"; + break; default: cpu_r = "?"; break; From 12d5a0626cf11acc3c9a59c91d87657eef726fdc Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:20:17 +0200 Subject: [PATCH 14/21] ARM: dts: stm32mp13: alignment with v5.19 Device tree alignment with Linux kernel v5.19-rc1 with: - ARM: dts: stm32: add UserPA13 button on stm32mp135f-dk - ARM: dts: stm32: add blue led (Linux heartbeat) on stm32mp135f-dk - ARM: dts: stm32: add EXTI interrupt-parent to pinctrl node on stm32mp131 - ARM: dts: stm32: enable RTC support on stm32mp135f-dk - ARM: dts: stm32: add RTC node on stm32mp131 - ARM: dts: stm32: fix pinctrl node name warnings (MPU soc) Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp131.dtsi | 19 ++++++++++++++++++- arch/arm/dts/stm32mp135f-dk.dts | 29 +++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 8f7af65e3e..84e16bb2f2 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -113,6 +113,12 @@ compatible = "fixed-clock"; clock-frequency = <99000000>; }; + + clk_rtc_k: clk-rtc-k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; }; intc: interrupt-controller@a0021000 { @@ -256,6 +262,15 @@ status = "disabled"; }; + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_pclk4>, <&clk_rtc_k>; + clock-names = "pclk", "rtc_ck"; + status = "disabled"; + }; + bsec: efuse@5c005000 { compatible = "st,stm32mp13-bsec"; reg = <0x5c005000 0x400>; @@ -277,11 +292,13 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp135-pinctrl"; ranges = <0 0x50002000 0x8400>; + interrupt-parent = <&exti>; + st,syscfg = <&exti 0x60 0xff>; pins-are-numbered; gpioa: gpio@50002000 { diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index 31c510f976..f436ffab99 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -6,6 +6,9 @@ /dts-v1/; +#include +#include +#include #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" #include "stm32mp13-pinctrl.dtsi" @@ -34,6 +37,28 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + user-pa13 { + label = "User-PA13"; + linux,code = ; + gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; @@ -48,6 +73,10 @@ status = "okay"; }; +&rtc { + status = "okay"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; From 6d647676ead2caecade3a7145302e98bfbc436f9 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:20:18 +0200 Subject: [PATCH 15/21] ARM: dts: stm32mp13: activate led on STM32MP13F-DK Activate the led managed in stm32mp1 board for U-Boot indication in STM32MP13F-DK device tree. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi index dfe5bbb2e3..cbe4eb5608 100644 --- a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi +++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi @@ -11,8 +11,18 @@ }; config { + u-boot,boot-led = "led-blue"; + u-boot,error-led = "led-red"; u-boot,mmc-env-partition = "u-boot-env"; }; + + leds { + led-red { + color = ; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; }; &uart4 { From eb67e63da4468195276c889a1866b43821128b25 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:20:19 +0200 Subject: [PATCH 16/21] configs: stm32mp13: Add support for baudrates higher than 115200 On STM32MP13x STMicroelectronics boards, the UART can reliably go up to 4000000 bauds when connected to the external ST-LINKV3. This patch adds the support of higher baudrates on STMicroelectronics STM32MP13x boards with ST-LINKV3. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- include/configs/stm32mp13_st_common.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/configs/stm32mp13_st_common.h b/include/configs/stm32mp13_st_common.h index ec64b12f7a..c51022b40d 100644 --- a/include/configs/stm32mp13_st_common.h +++ b/include/configs/stm32mp13_st_common.h @@ -14,4 +14,9 @@ #include +/* uart with on-board st-link */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 460800, 921600, \ + 1000000, 2000000, 4000000} + #endif From 72d7a302f634029ef2874d864c294fd9bfc48739 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:20:20 +0200 Subject: [PATCH 17/21] configs: stm32mp13: activate RNG support Activate the RNG driver provided by OP-TEE. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp13_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index f5b6262883..4707315b76 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_LOG=y CONFIG_OF_LIVE=y @@ -45,6 +46,8 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_SCMI=y CONFIG_RESET_SCMI=y +CONFIG_DM_RNG=y +CONFIG_RNG_OPTEE=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SYSRESET_PSCI=y CONFIG_TEE=y From 420f37a91faefcda64355805fbcb662cd0aac8e1 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:20:21 +0200 Subject: [PATCH 18/21] configs: stm32mp13: activate RTC support Activate the RTC driver in STM32MP13x config. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp13_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 4707315b76..5f88f0819a 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -48,6 +48,8 @@ CONFIG_DM_REGULATOR_SCMI=y CONFIG_RESET_SCMI=y CONFIG_DM_RNG=y CONFIG_RNG_OPTEE=y +CONFIG_DM_RTC=y +CONFIG_RTC_STM32=y CONFIG_SERIAL_RX_BUFFER=y CONFIG_SYSRESET_PSCI=y CONFIG_TEE=y From 33129f6130dc125582e09a03ec78afe53a1b27f3 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:20:22 +0200 Subject: [PATCH 19/21] configs: stm32mp13: activate I2C support Activate the I2C driver in STM32MP13x config. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp13_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 5f88f0819a..6d0b02b5e7 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y @@ -38,6 +39,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_CLK_SCMI=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y CONFIG_STM32_SDMMC2=y CONFIG_DM_ETH=y CONFIG_PINCONF=y From 257d001cb5a3e3e3a582fddb37478dedb1764811 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 30 Jun 2022 10:20:23 +0200 Subject: [PATCH 20/21] configs: stm32mp13: activate some command Activate useful commands in STM32MP13x config, already activated in stm32mp15_defconfig. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- configs/stm32mp13_defconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 6d0b02b5e7..673b468d31 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -21,17 +21,25 @@ CONFIG_SYS_PROMPT="STM32MP> " CONFIG_SYS_BOOTM_LEN=0x2000000 CONFIG_CMD_ADTIMG=y CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y +CONFIG_CMD_UNZIP=y CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_LSBLK=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y CONFIG_CMD_TIME=y CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y +CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y @@ -39,9 +47,16 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_CLK_SCMI=y +CONFIG_GPIO_HOG=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_DM_ETH=y CONFIG_PINCONF=y CONFIG_DM_REGULATOR=y @@ -59,6 +74,7 @@ CONFIG_TEE=y CONFIG_OPTEE=y # CONFIG_OPTEE_TA_AVB is not set CONFIG_ERRNO_STR=y +CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 From 48d9eaf6826a1816c5f9839a564ea6338da609a7 Mon Sep 17 00:00:00 2001 From: Johann Neuhauser Date: Thu, 30 Jun 2022 16:19:48 +0200 Subject: [PATCH 21/21] arm: dts: stm32mp1: Drop fastboot and stm32prog trigger gpios on DHCOM PA13 and PA14 are used for USB power control and can't be used to enforce fastboot or stm32prog mode by pressing a button. Defining CONFIG_FASTBOOT/CONFIG_CMD_STM32PROG without this patch applied results in fastboot/stm32prog always starting, because PA13/PA14 are always low during boot. So drop the wrong trigger gpios definitions. Signed-off-by: Johann Neuhauser Reviewed-by: Marek Vasut Reviewed-by: Patrick Delaunay --- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index d73967ac1b..ee747a52bb 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -27,8 +27,6 @@ config { u-boot,boot-led = "heartbeat"; u-boot,error-led = "error"; - st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>; dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; };