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ARM: uniphier: allow to enable multiple SoCs

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Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
2015-09-22 00:27:39 +09:00
parent 5451b777de
commit 323d1f9d5b
80 changed files with 1070 additions and 478 deletions
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50
include/configs/uniphier.h
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@@ -9,53 +9,6 @@
#ifndef __CONFIG_UNIPHIER_COMMON_H__
#define __CONFIG_UNIPHIER_COMMON_H__
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 1
#define CONFIG_DDR_NUM_CH2 1
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x20000000
#define CONFIG_SDRAM1_BASE 0xc0000000
#define CONFIG_SDRAM1_SIZE 0x20000000
#define CONFIG_SDRAM2_BASE 0xc0000000
#define CONFIG_SDRAM2_SIZE 0x10000000
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x10000000
#define CONFIG_SDRAM1_BASE 0x90000000
#define CONFIG_SDRAM1_SIZE 0x10000000
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x20000000
#define CONFIG_SDRAM1_BASE 0xa0000000
#define CONFIG_SDRAM1_SIZE 0x20000000
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
/* Physical start address of SDRAM */
#define CONFIG_SDRAM0_BASE 0x80000000
#define CONFIG_SDRAM0_SIZE 0x10000000
#define CONFIG_SDRAM1_BASE 0x90000000
#define CONFIG_SDRAM1_SIZE 0x10000000
#endif
#define CONFIG_I2C_EEPROM
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
@@ -285,8 +238,7 @@
defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define CONFIG_SPL_TEXT_BASE 0x00040000
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
#else
#define CONFIG_SPL_TEXT_BASE 0x00100000
#endif