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Merge branch 'master' of git://git.denx.de/u-boot-mips

Browse Source 
Please pull another update for Broadcom MIPS.
This contains new SoC's, new boards and new drivers and some bugfixes.
This commit is contained in:
Tom Rini
2017-05-31 22:28:06 -04:00
parent 1b87f9538f c93bb1d7bb
commit 31493dd5ff
49 changed files with 1550 additions and 20 deletions
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25
include/configs/bmips_bcm3380.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_BMIPS_BCM3380_H
#define __CONFIG_BMIPS_BCM3380_H
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
#endif
#endif /* __CONFIG_BMIPS_BCM3380_H */

30
include/configs/bmips_bcm6338.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_BMIPS_BCM6338_H
#define __CONFIG_BMIPS_BCM6338_H
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 120000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
#endif
#define CONFIG_SYS_FLASH_BASE 0xbfc00000
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#endif /* __CONFIG_BMIPS_BCM6338_H */

30
include/configs/bmips_bcm6348.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_BMIPS_BCM6348_H
#define __CONFIG_BMIPS_BCM6348_H
/* CPU */
#define CONFIG_SYS_MIPS_TIMER_FREQ 128000000
/* RAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* U-Boot */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
#if defined(CONFIG_BMIPS_BOOT_RAM)
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
#endif
#define CONFIG_SYS_FLASH_BASE 0xbfc00000
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#endif /* __CONFIG_BMIPS_BCM6348_H */

4
include/configs/bmips_common.h
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@@ -7,6 +7,10 @@
#ifndef __CONFIG_BMIPS_COMMON_H
#define __CONFIG_BMIPS_COMMON_H
/* UART */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
230400, 500000, 1500000 }
/* RAM */
#define CONFIG_SYS_MEMTEST_START 0xa0000000
#define CONFIG_SYS_MEMTEST_END 0xa2000000

20
include/configs/comtrend_ct5361.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6348.h>
#define CONFIG_REMAKE_ELF
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1

15
include/configs/netgear_cg3100d.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <configs/bmips_common.h>
#include <configs/bmips_bcm3380.h>
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP

15
include/configs/sagem_f@st1704.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <configs/bmips_common.h>
#include <configs/bmips_bcm6338.h>
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP

23
include/dt-bindings/clock/bcm3380-clock.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from Broadcom GPL Source Code:
* Copyright (C) Broadcom Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_CLOCK_BCM3380_H
#define __DT_BINDINGS_CLOCK_BCM3380_H
#define BCM3380_CLK0_DDR 0
#define BCM3380_CLK0_FPM 1
#define BCM3380_CLK0_CRYPTO 2
#define BCM3380_CLK0_EPHY 3
#define BCM3380_CLK0_PCIE 16
#define BCM3380_CLK0_SPI 17
#define BCM3380_CLK0_ENET0 18
#define BCM3380_CLK0_ENET1 19
#define BCM3380_CLK0_PCM 27
#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */

19
include/dt-bindings/clock/bcm6338-clock.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_CLOCK_BCM6338_H
#define __DT_BINDINGS_CLOCK_BCM6338_H
#define BCM6338_CLK_ADSL 0
#define BCM6338_CLK_MPI 1
#define BCM6338_CLK_SDRAM 2
#define BCM6338_CLK_ENET 4
#define BCM6338_CLK_SAR 5
#define BCM6338_CLK_SPI 9
#endif /* __DT_BINDINGS_CLOCK_BCM6338_H */

22
include/dt-bindings/clock/bcm6348-clock.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
#define __DT_BINDINGS_CLOCK_BCM6348_H
#define BCM6348_CLK_ADSL 0
#define BCM6348_CLK_MPI 1
#define BCM6348_CLK_SDRAM 2
#define BCM6348_CLK_M2M 3
#define BCM6348_CLK_ENET 4
#define BCM6348_CLK_SAR 5
#define BCM6348_CLK_USBS 6
#define BCM6348_CLK_USBH 8
#define BCM6348_CLK_SPI 9
#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */

16
include/dt-bindings/reset/bcm3380-reset.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from Broadcom GPL Source Code:
* Copyright (C) Broadcom Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_RESET_BCM3380_H
#define __DT_BINDINGS_RESET_BCM3380_H
#define BCM3380_RST0_SPI 0
#define BCM3380_RST0_PCM 13
#endif /* __DT_BINDINGS_RESET_BCM3380_H */

22
include/dt-bindings/reset/bcm6338-reset.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_RESET_BCM6338_H
#define __DT_BINDINGS_RESET_BCM6338_H
#define BCM6338_RST_SPI 0
#define BCM6338_RST_ENET 2
#define BCM6338_RST_USBH 3
#define BCM6338_RST_USBS 4
#define BCM6338_RST_ADSL 5
#define BCM6338_RST_DMAMEM 6
#define BCM6338_RST_SAR 7
#define BCM6338_RST_ACLC 8
#define BCM6338_RST_ADSL_MIPS 10
#endif /* __DT_BINDINGS_RESET_BCM6338_H */

22
include/dt-bindings/reset/bcm6348-reset.h Normal file
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/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_RESET_BCM6348_H
#define __DT_BINDINGS_RESET_BCM6348_H
#define BCM6348_RST_SPI 0
#define BCM6348_RST_ENET 2
#define BCM6348_RST_USBH 3
#define BCM6348_RST_USBS 4
#define BCM6348_RST_ADSL 5
#define BCM6348_RST_DMAMEM 6
#define BCM6348_RST_SAR 7
#define BCM6348_RST_ACLC 8
#define BCM6348_RST_ADSL_MIPS 10
#endif /* __DT_BINDINGS_RESET_BCM6348_H */