Move PHYLIB to Kconfig
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
committed by
Joe Hershberger
parent
ef1f61aa03
commit
3146f0c017
@@ -71,7 +71,6 @@
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 4
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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/* Serial Flash */
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@@ -51,7 +51,6 @@
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE
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#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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@@ -358,7 +358,6 @@
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/* Network. */
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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/* Enable Atheros phy driver */
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#define CONFIG_PHY_ATHEROS
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@@ -111,7 +111,6 @@
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#define CONFIG_CONS_INDEX 1
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/* Ethernet support */
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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/* NAND support */
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@@ -276,7 +276,6 @@
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ADDR 0
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#define CONFIG_PHY_SMSC
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@@ -101,7 +101,6 @@
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/* Network. */
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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#endif /* ! __CONFIG_AM335X_SL50_H */
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@@ -246,7 +246,6 @@
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#endif
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#define CONFIG_DRIVER_TI_CPSW
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#define CONFIG_PHYLIB
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
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#define CONFIG_SYS_RX_ETH_BUFFER 64
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@@ -85,7 +85,6 @@
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#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
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#define CONFIG_MII /* Required in net/eth.c */
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#define CONFIG_PHY_GIGE /* per-board part of CPSW */
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#define CONFIG_PHYLIB
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
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#define CONFIG_SUPPORT_EMMC_BOOT
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@@ -29,7 +29,6 @@
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#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
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#define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
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#define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL 1
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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@@ -86,7 +86,6 @@
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 6
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_PHY_MICREL_KSZ90X1
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#define CONFIG_IP_DEFRAG
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@@ -32,7 +32,6 @@
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_SPI_FLASH_MTD
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@@ -101,7 +101,6 @@
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#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
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#define CONFIG_SH_ETHER_SH7734_MII (0x01)
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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@@ -303,7 +303,6 @@
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/* Network. */
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ADDR 0
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#define CONFIG_PHY_SMSC
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#define CONFIG_MII
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@@ -522,7 +522,6 @@ DEFAULT_LINUX_BOOT_ENV \
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/* Network. */
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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/*
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@@ -31,7 +31,6 @@
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/* Network defines */
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#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
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#define CONFIG_MII /* Required in net/eth.c */
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_NATSEMI
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/*
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@@ -109,7 +109,6 @@
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 6
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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/* Command definition */
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@@ -206,7 +206,6 @@
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#endif
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/* Network. */
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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#endif /* ! __CONFIG_CHILIBOARD_H */
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@@ -102,7 +102,6 @@
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_PHYLIB
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#define CONFIG_SYS_RX_ETH_BUFFER 64
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#define PHY_ANEG_TIMEOUT 8000
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@@ -192,7 +192,6 @@
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_MII
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#define CONFIG_ETHPRIME "FEC0"
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@@ -103,7 +103,6 @@
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/* Network. */
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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/* NAND support */
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@@ -55,7 +55,6 @@
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#define CONFIG_NET_MULTI
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_PHYLIB
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#define CONFIG_SYS_RX_ETH_BUFFER 64
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/* USB support */
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@@ -72,7 +72,6 @@
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 1
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_IP_DEFRAG
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#define CONFIG_TFTP_BLOCKSIZE 16352
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@@ -32,7 +32,6 @@
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_IP_DEFRAG
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#define CONFIG_TFTP_BLOCKSIZE 16352
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@@ -66,7 +66,6 @@
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#define IMX_FEC_BASE ENET1_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_IPADDR 192.168.10.2
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@@ -84,7 +84,6 @@
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/* Ethernet */
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#define CONFIG_MACB
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#define CONFIG_PHYLIB
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#define CONFIG_RMII
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_AT91_WANTS_COMMON_PHY
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@@ -73,7 +73,6 @@
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#define CONFIG_RMII
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#define CONFIG_PHY_SMSC
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#define CONFIG_LPC32XX_ETH
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ADDR 0x1F
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#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
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@@ -113,7 +113,6 @@
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#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
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#define CONFIG_MII /* Required in net/eth.c */
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#define CONFIG_PHY_GIGE /* per-board part of CPSW */
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_TI
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/* SPI */
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@@ -53,7 +53,6 @@
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#define CONFIG_SH_ETHER_USE_PORT (0)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
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#define CONFIG_PHY_SMSC 1
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#define CONFIG_PHYLIB
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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@@ -51,7 +51,6 @@
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 4
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#ifdef CONFIG_CMD_SF
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@@ -91,7 +91,6 @@
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (1)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
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#define CONFIG_PHYLIB
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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@@ -77,7 +77,6 @@
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*/
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_FEC_MXC_PHYADDR 0x1
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@@ -94,7 +94,6 @@
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 4
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#endif
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@@ -50,7 +50,6 @@
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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@@ -30,7 +30,6 @@
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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@@ -346,7 +346,6 @@ int get_scl(void);
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/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
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#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
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#define CONFIG_SYS_TBIPA_VALUE 8
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#define CONFIG_PHYLIB /* recommended PHY management */
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#define CONFIG_ETHPRIME "FM1@DTSEC5"
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#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
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@@ -50,7 +50,6 @@
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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@@ -51,7 +51,6 @@
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#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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@@ -153,7 +153,6 @@
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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#endif
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@@ -200,7 +200,6 @@
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#define CONFIG_ETHPRIME "eTSEC2"
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_HAS_ETH0
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@@ -457,7 +457,6 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_REALTEK
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#define CONFIG_HAS_ETH0
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@@ -336,7 +336,6 @@
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_PHY_GIGE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#define CONFIG_HAS_ETH0
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@@ -50,7 +50,6 @@ unsigned long get_board_ddr_clk(void);
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_FMAN_ENET
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_VITESSE
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#define CONFIG_PHY_REALTEK
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#define CONFIG_PHYLIB_10G
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@@ -249,7 +249,6 @@
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#define AQR105_IRQ_MASK 0x40000000
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#ifdef CONFIG_NET
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
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#define CONFIG_PHY_VITESSE
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#define CONFIG_PHY_REALTEK
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@@ -70,7 +70,6 @@ unsigned long get_board_ddr_clk(void);
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_FMAN_ENET
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_VITESSE
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#define CONFIG_PHY_REALTEK
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#define CONFIG_PHYLIB_10G
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@@ -180,7 +180,6 @@
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#ifndef SPL_NO_FMAN
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#ifdef CONFIG_NET
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
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#define CONFIG_PHY_REALTEK
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#endif
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@@ -406,7 +406,6 @@ unsigned long get_board_ddr_clk(void);
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#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
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#define CONFIG_FSL_MEMAC
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#define CONFIG_PHYLIB
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#define CONFIG_PHYLIB_10G
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#define CONFIG_PHY_VITESSE
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#define CONFIG_PHY_REALTEK
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@@ -468,7 +468,6 @@ unsigned long get_board_sys_clk(void);
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#define CONFIG_PHYLIB_10G
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#define CONFIG_PHY_AQUANTIA
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#define CONFIG_PHY_CORTINA
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#define CONFIG_PHYLIB
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#define CONFIG_SYS_CORTINA_FW_IN_NOR
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_CORTINA_FW_ADDR 0x20980000
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@@ -116,7 +116,6 @@
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#define CONFIG_MII
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#define CONFIG_DISCOVER_PHY
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_ETHPRIME "FEC0"
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#endif
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@@ -108,7 +108,6 @@
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 1
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_PHY_MICREL_KSZ90X1
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@@ -37,7 +37,6 @@
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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/* Framebuffer */
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@@ -28,7 +28,6 @@
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 1
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#ifdef CONFIG_CMD_SF
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@@ -39,7 +39,6 @@
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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#define CONFIG_EXTRA_ENV_SETTINGS \
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@@ -141,7 +141,6 @@
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#ifdef CONFIG_CMD_USB
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@@ -163,7 +163,6 @@
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_ATHEROS
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#ifdef CONFIG_CMD_USB
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@@ -207,7 +207,6 @@
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#endif
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#define CONFIG_ETHPRIME "FEC"
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||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#endif
|
||||
|
||||
|
||||
@@ -26,7 +26,6 @@
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_BROADCOM
|
||||
/* ENET1 */
|
||||
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
|
||||
|
||||
@@ -65,7 +65,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 6
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ90X1
|
||||
|
||||
|
||||
@@ -72,7 +72,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x7
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ90X1
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
@@ -82,7 +82,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE MII100
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x5
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#ifndef CONFIG_SPL
|
||||
|
||||
@@ -141,7 +141,6 @@
|
||||
#endif /* CONFIG_USB_MUSB_GADGET */
|
||||
|
||||
#define CONFIG_PHY_GIGE
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#endif /* ! __CONFIG_PCM051_H */
|
||||
|
||||
@@ -61,7 +61,6 @@
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
|
||||
/* QSPI Configs*/
|
||||
|
||||
@@ -43,7 +43,6 @@
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 3
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ90X1
|
||||
|
||||
|
||||
@@ -191,7 +191,6 @@
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
/* Network */
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_RESET 1
|
||||
#define CONFIG_PHY_NATSEMI
|
||||
#define CONFIG_PHY_REALTEK
|
||||
|
||||
@@ -78,7 +78,6 @@
|
||||
|
||||
/* Ethernet support */
|
||||
#define CONFIG_PHY_GIGE
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ADDR 0
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ90X1
|
||||
|
||||
@@ -21,7 +21,6 @@
|
||||
#define IMX_FEC_BASE ENET2_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
|
||||
/* Size of malloc() pool */
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* ENET1 */
|
||||
|
||||
@@ -40,8 +40,6 @@
|
||||
#define CONFIG_MII
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
|
||||
/* USB config */
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
|
||||
@@ -52,7 +52,6 @@
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
@@ -27,7 +27,6 @@
|
||||
#define CONFIG_SH_ETHER 1
|
||||
#define CONFIG_SH_ETHER_USE_PORT (0)
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC 1
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
@@ -93,7 +93,6 @@
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#endif
|
||||
|
||||
|
||||
@@ -33,7 +33,6 @@
|
||||
/* FEC Ethernet on SoC */
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC
|
||||
#endif
|
||||
|
||||
|
||||
@@ -33,7 +33,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 6
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ90X1
|
||||
|
||||
|
||||
@@ -60,7 +60,6 @@
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 18
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
|
||||
#define CONFIG_SH_ETHER_USE_GETHER 1
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
|
||||
|
||||
@@ -60,7 +60,6 @@
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 18
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
|
||||
#define CONFIG_SH_ETHER_USE_GETHER 1
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
|
||||
|
||||
@@ -60,7 +60,6 @@
|
||||
#define CONFIG_SH_ETHER_USE_PORT 0
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 1
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
|
||||
|
||||
@@ -91,7 +91,6 @@
|
||||
#define CONFIG_SH_ETHER 1
|
||||
#define CONFIG_SH_ETHER_USE_PORT (1)
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
|
||||
|
||||
@@ -223,7 +223,6 @@
|
||||
#define CONFIG_DRIVER_TI_CPSW
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_PHY_GIGE
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_BOOTP_DEFAULT
|
||||
#define CONFIG_BOOTP_DNS
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
|
||||
@@ -52,7 +52,6 @@
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
@@ -117,7 +117,6 @@
|
||||
*
|
||||
*/
|
||||
#define CONFIG_MACB
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_USB_HOST_ETHER
|
||||
#define CONFIG_USB_ETHER_ASIX
|
||||
#define CONFIG_USB_ETHER_MCS7830
|
||||
|
||||
@@ -52,7 +52,6 @@
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_MACB
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_RMII
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_RESET_PHY_R
|
||||
|
||||
@@ -55,7 +55,6 @@
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
@@ -296,7 +296,6 @@ extern int soft_i2c_gpio_scl;
|
||||
#ifdef CONFIG_SUNXI_EMAC
|
||||
#define CONFIG_PHY_ADDR 1
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_PHYLIB
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SUNXI_GMAC
|
||||
|
||||
@@ -87,7 +87,6 @@
|
||||
|
||||
/* Ethernet */
|
||||
#define CONFIG_MACB
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_RMII
|
||||
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||
|
||||
|
||||
@@ -59,7 +59,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 4
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* Framebuffer */
|
||||
|
||||
@@ -179,7 +179,6 @@
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_NET_RETRY_COUNT 10
|
||||
#define CONFIG_PHY_GIGE
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ET1011C
|
||||
#define CONFIG_PHY_ET1011C_TX_CLK_FIX
|
||||
|
||||
|
||||
@@ -97,7 +97,6 @@
|
||||
#endif
|
||||
|
||||
/* Network Configuration */
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MARVELL
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_BOOTP_DEFAULT
|
||||
|
||||
@@ -45,7 +45,6 @@
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 4
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ90X1
|
||||
|
||||
|
||||
@@ -81,7 +81,6 @@
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_MII
|
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
@@ -61,7 +61,6 @@
|
||||
* Eth Configs
|
||||
*/
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
|
||||
@@ -41,7 +41,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 6
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_PHY_MICREL_KSZ90X1
|
||||
|
||||
|
||||
@@ -112,7 +112,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_ETHPRIME "FEC0"
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@@ -59,7 +59,6 @@
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
|
||||
/* QSPI Configs*/
|
||||
|
||||
@@ -72,7 +72,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
|
||||
@@ -60,7 +60,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* Framebuffer */
|
||||
|
||||
@@ -88,7 +88,6 @@
|
||||
*/
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1
|
||||
|
||||
|
||||
@@ -57,7 +57,6 @@
|
||||
|
||||
#define CONFIG_PHY_SMSC
|
||||
#define CONFIG_LPC32XX_ETH
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ADDR 0
|
||||
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
|
||||
/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
|
||||
|
||||
@@ -75,7 +75,6 @@
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x0
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_SMSC
|
||||
|
||||
#define CONFIG_IMX_THERMAL
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x10
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */
|
||||
|
||||
#endif /*__EL6Q_CONFIG_H */
|
||||
|
||||
Reference in New Issue
Block a user