Move PHYLIB to Kconfig

Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Alexandru Gagniuc
2017-08-01 17:19:59 -07:00
committed by Joe Hershberger
parent ef1f61aa03
commit 3146f0c017
603 changed files with 503 additions and 105 deletions

View File

@@ -71,7 +71,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* Serial Flash */

View File

@@ -51,7 +51,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

View File

@@ -358,7 +358,6 @@
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
/* Enable Atheros phy driver */
#define CONFIG_PHY_ATHEROS

View File

@@ -111,7 +111,6 @@
#define CONFIG_CONS_INDEX 1
/* Ethernet support */
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
/* NAND support */

View File

@@ -276,7 +276,6 @@
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_NET_MULTI
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC

View File

@@ -101,7 +101,6 @@
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_AM335X_SL50_H */

View File

@@ -246,7 +246,6 @@
#endif
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_PHYLIB
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
#define CONFIG_SYS_RX_ETH_BUFFER 64

View File

@@ -85,7 +85,6 @@
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_GIGE /* per-board part of CPSW */
#define CONFIG_PHYLIB
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */
#define CONFIG_SUPPORT_EMMC_BOOT

View File

@@ -29,7 +29,6 @@
#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
#define CONFIG_SH_ETHER_PHY_MODE (PHY_INTERFACE_MODE_GMII)
#define CONFIG_SH_ETHER_SH7734_MII (0x02) /* GMII */
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL 1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

View File

@@ -86,7 +86,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ90X1
#define CONFIG_IP_DEFRAG

View File

@@ -32,7 +32,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_SPI_FLASH_MTD

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@@ -101,7 +101,6 @@
#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
#define CONFIG_SH_ETHER_SH7734_MII (0x01)
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

View File

@@ -303,7 +303,6 @@
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
#define CONFIG_MII

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@@ -522,7 +522,6 @@ DEFAULT_LINUX_BOOT_ENV \
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
/*

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@@ -31,7 +31,6 @@
/* Network defines */
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHYLIB
#define CONFIG_PHY_NATSEMI
/*

View File

@@ -109,7 +109,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* Command definition */

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@@ -206,7 +206,6 @@
#endif
/* Network. */
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_CHILIBOARD_H */

View File

@@ -102,7 +102,6 @@
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_PHY_GIGE
#define CONFIG_PHY_ATHEROS
#define CONFIG_PHYLIB
#define CONFIG_SYS_RX_ETH_BUFFER 64
#define PHY_ANEG_TIMEOUT 8000

View File

@@ -192,7 +192,6 @@
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_FEC_XCV_TYPE RGMII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC0"

View File

@@ -103,7 +103,6 @@
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* NAND support */

View File

@@ -55,7 +55,6 @@
#define CONFIG_NET_MULTI
#define CONFIG_PHY_GIGE
#define CONFIG_PHY_ATHEROS
#define CONFIG_PHYLIB
#define CONFIG_SYS_RX_ETH_BUFFER 64
/* USB support */

View File

@@ -72,7 +72,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_IP_DEFRAG
#define CONFIG_TFTP_BLOCKSIZE 16352

View File

@@ -32,7 +32,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_IP_DEFRAG
#define CONFIG_TFTP_BLOCKSIZE 16352

View File

@@ -66,7 +66,6 @@
#define IMX_FEC_BASE ENET1_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_IPADDR 192.168.10.2

View File

@@ -84,7 +84,6 @@
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_PHYLIB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91_WANTS_COMMON_PHY

View File

@@ -73,7 +73,6 @@
#define CONFIG_RMII
#define CONFIG_PHY_SMSC
#define CONFIG_LPC32XX_ETH
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0x1F
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

View File

@@ -113,7 +113,6 @@
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_GIGE /* per-board part of CPSW */
#define CONFIG_PHYLIB
#define CONFIG_PHY_TI
/* SPI */

View File

@@ -53,7 +53,6 @@
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
#define CONFIG_PHY_SMSC 1
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

View File

@@ -51,7 +51,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_SF

View File

@@ -91,7 +91,6 @@
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x00)
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

View File

@@ -77,7 +77,6 @@
*/
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_FEC_MXC_PHYADDR 0x1

View File

@@ -94,7 +94,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#endif

View File

@@ -50,7 +50,6 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

View File

@@ -30,7 +30,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

View File

@@ -346,7 +346,6 @@ int get_scl(void);
/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
#define CONFIG_SYS_TBIPA_VALUE 8
#define CONFIG_PHYLIB /* recommended PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC5"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */

View File

@@ -50,7 +50,6 @@
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

View File

@@ -51,7 +51,6 @@
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

View File

@@ -153,7 +153,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#endif

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@@ -200,7 +200,6 @@
#define CONFIG_ETHPRIME "eTSEC2"
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#define CONFIG_HAS_ETH0

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@@ -457,7 +457,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_REALTEK
#define CONFIG_HAS_ETH0

View File

@@ -336,7 +336,6 @@
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#define CONFIG_HAS_ETH0

View File

@@ -50,7 +50,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHYLIB_10G

View File

@@ -249,7 +249,6 @@
#define AQR105_IRQ_MASK 0x40000000
#ifdef CONFIG_NET
#define CONFIG_PHYLIB
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK

View File

@@ -70,7 +70,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_FMAN_ENET
#define CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHYLIB_10G

View File

@@ -180,7 +180,6 @@
#ifndef SPL_NO_FMAN
#ifdef CONFIG_NET
#define CONFIG_PHYLIB
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#define CONFIG_PHY_REALTEK
#endif

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@@ -406,7 +406,6 @@ unsigned long get_board_ddr_clk(void);
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_FSL_MEMAC
#define CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK

View File

@@ -468,7 +468,6 @@ unsigned long get_board_sys_clk(void);
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_AQUANTIA
#define CONFIG_PHY_CORTINA
#define CONFIG_PHYLIB
#define CONFIG_SYS_CORTINA_FW_IN_NOR
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_CORTINA_FW_ADDR 0x20980000

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@@ -116,7 +116,6 @@
#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_ETHPRIME "FEC0"
#endif

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@@ -108,7 +108,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ90X1

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@@ -37,7 +37,6 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* Framebuffer */

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@@ -28,7 +28,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_SF

View File

@@ -39,7 +39,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#define CONFIG_EXTRA_ENV_SETTINGS \

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@@ -141,7 +141,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_USB

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@@ -163,7 +163,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_USB

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@@ -207,7 +207,6 @@
#endif
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#endif

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@@ -26,7 +26,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_BROADCOM
/* ENET1 */
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR

View File

@@ -65,7 +65,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ90X1

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@@ -72,7 +72,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x7
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ90X1
#define CONFIG_ARP_TIMEOUT 200UL

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@@ -82,7 +82,6 @@
#define CONFIG_FEC_XCV_TYPE MII100
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x5
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#ifndef CONFIG_SPL

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@@ -141,7 +141,6 @@
#endif /* CONFIG_USB_MUSB_GADGET */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_PCM051_H */

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@@ -61,7 +61,6 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
/* QSPI Configs*/

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@@ -43,7 +43,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 3
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ90X1

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@@ -191,7 +191,6 @@
#define CONFIG_NET_MULTI
/* Network */
#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET 1
#define CONFIG_PHY_NATSEMI
#define CONFIG_PHY_REALTEK

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@@ -78,7 +78,6 @@
/* Ethernet support */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ90X1

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@@ -21,7 +21,6 @@
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
/* Size of malloc() pool */

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@@ -25,7 +25,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* ENET1 */

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@@ -40,8 +40,6 @@
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_PHYLIB
/* USB config */
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

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@@ -52,7 +52,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

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@@ -27,7 +27,6 @@
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC 1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

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@@ -93,7 +93,6 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#endif

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@@ -33,7 +33,6 @@
/* FEC Ethernet on SoC */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#endif

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@@ -33,7 +33,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ90X1

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@@ -60,7 +60,6 @@
#define CONFIG_SH_ETHER_PHY_ADDR 18
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define CONFIG_SH_ETHER_USE_GETHER 1
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII

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@@ -60,7 +60,6 @@
#define CONFIG_SH_ETHER_PHY_ADDR 18
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define CONFIG_SH_ETHER_USE_GETHER 1
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII

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@@ -60,7 +60,6 @@
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

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@@ -91,7 +91,6 @@
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

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@@ -223,7 +223,6 @@
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2

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@@ -52,7 +52,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

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@@ -117,7 +117,6 @@
*
*/
#define CONFIG_MACB
#define CONFIG_PHYLIB
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_MCS7830

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@@ -52,7 +52,6 @@
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_PHYLIB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R

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@@ -55,7 +55,6 @@
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

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@@ -296,7 +296,6 @@ extern int soft_i2c_gpio_scl;
#ifdef CONFIG_SUNXI_EMAC
#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
#define CONFIG_PHYLIB
#endif
#ifdef CONFIG_SUNXI_GMAC

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@@ -87,7 +87,6 @@
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_PHYLIB
#define CONFIG_RMII
#define CONFIG_AT91_WANTS_COMMON_PHY

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@@ -59,7 +59,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* Framebuffer */

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@@ -179,7 +179,6 @@
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ET1011C
#define CONFIG_PHY_ET1011C_TX_CLK_FIX

View File

@@ -97,7 +97,6 @@
#endif
/* Network Configuration */
#define CONFIG_PHYLIB
#define CONFIG_PHY_MARVELL
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT

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@@ -45,7 +45,6 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ90X1

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@@ -81,7 +81,6 @@
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_PHYLIB
#define CONFIG_MII
#define CONFIG_ARP_TIMEOUT 200UL

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@@ -61,7 +61,6 @@
* Eth Configs
*/
#define CONFIG_MII
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#define CONFIG_FEC_MXC

View File

@@ -41,7 +41,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ90X1

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@@ -112,7 +112,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#endif /* __CONFIG_H */

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@@ -59,7 +59,6 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
/* QSPI Configs*/

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@@ -72,7 +72,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_USB

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@@ -60,7 +60,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* Framebuffer */

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@@ -88,7 +88,6 @@
*/
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR
#define CONFIG_PHYLIB
#define CONFIG_PHY_MICREL
#define CONFIG_FEC_MXC_PHYADDR 0x1

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@@ -57,7 +57,6 @@
#define CONFIG_PHY_SMSC
#define CONFIG_LPC32XX_ETH
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */

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@@ -75,7 +75,6 @@
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#define CONFIG_IMX_THERMAL

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@@ -25,7 +25,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x10
#define CONFIG_PHYLIB
#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */
#endif /*__EL6Q_CONFIG_H */