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Convert CONFIG_PHYLIB et al to Kconfig

Browse Source 
This converts the following to Kconfig:
   CONFIG_PHYLIB
   CONFIG_BITBANGMII
   CONFIG_MV88E6352_SWITCH
   CONFIG_MV88E61XX_SWITCH
   CONFIG_PHYLIB_10G
   CONFIG_PHY_AQUANTIA
   CONFIG_PHY_ATHEROS
   CONFIG_PHY_BROADCOM
   CONFIG_PHY_CORTINA
   CONFIG_PHY_DAVICOM
   CONFIG_PHY_ET1011C
   CONFIG_PHY_LXT
   CONFIG_PHY_MARVELL
   CONFIG_PHY_MICREL
   CONFIG_PHY_NATSEMI
   CONFIG_PHY_REALTEK
   CONFIG_RTL8211X_PHY_FORCE_MASTER
   CONFIG_PHY_SMSC
   CONFIG_PHY_TERANETICS
   CONFIG_PHY_TI
   CONFIG_PHY_VITESSE
   CONFIG_PHY_XILINX

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2020-04-24 15:35:53 -04:00
parent 69a229c6d4
commit 306881a0bf
562 changed files with 1970 additions and 191 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
include/config_phylib_all_drivers.h
View File

@@ -12,21 +12,4 @@
#ifndef _CONFIG_PHYLIB_ALL_H
#define _CONFIG_PHYLIB_ALL_H
#ifdef CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_BROADCOM
#define CONFIG_PHY_DAVICOM
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_NATSEMI
#define CONFIG_PHY_LXT
#define CONFIG_PHY_ATHEROS
#define CONFIG_PHY_SMSC
#ifdef CONFIG_PHYLIB_10G
#define CONFIG_PHY_TERANETICS
#endif /* CONFIG_PHYLIB_10G */
#endif /* CONFIG_PHYLIB */
#endif /*_CONFIG_PHYLIB_ALL_H */

3
include/configs/B4860QDS.h
View File

@@ -586,9 +586,6 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_TERANETICS
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x10
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E

2
include/configs/MPC8560ADS.h
View File

@@ -288,8 +288,6 @@
#define FETH3_RST 0x80
#endif /* CONFIG_ETHER_INDEX */
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
/*
* GPIO pins used for bit-banged MII communications
*/

4
include/configs/P1023RDB.h
View File

@@ -277,10 +277,6 @@ extern unsigned long get_clock_freq(void);
/* For FM */
#define CONFIG_SYS_DPAA_FMAN
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHY_ATHEROS
#endif
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000

6
include/configs/P2041RDB.h
View File

@@ -418,12 +418,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_TERANETICS
#endif
#ifdef CONFIG_PCI
#if !defined(CONFIG_DM_PCI)
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */

4
include/configs/T102xQDS.h
View File

@@ -653,10 +653,6 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3

1
include/configs/T102xRDB.h
View File

@@ -610,7 +610,6 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHY_REALTEK
#if defined(CONFIG_TARGET_T1024RDB)
#define RGMII_PHY1_ADDR 0x2
#define RGMII_PHY2_ADDR 0x6

4
include/configs/T1040QDS.h
View File

@@ -540,10 +540,6 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x10
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E

5
include/configs/T104xRDB.h
View File

@@ -654,11 +654,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#endif
#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB)
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03

3
include/configs/T208xQDS.h
View File

@@ -587,9 +587,6 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define FM1_10GEC1_PHY_ADDR 0x3

1
include/configs/T208xRDB.h
View File

@@ -536,7 +536,6 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHY_REALTEK
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
#define RGMII_PHY2_ADDR 0x02

3
include/configs/T4240QDS.h
View File

@@ -404,9 +404,6 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_TERANETICS
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E

3
include/configs/T4240RDB.h
View File

@@ -546,11 +546,8 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_CORTINA_FW_ADDR 0xefe00000
#define CONFIG_CORTINA_FW_LENGTH 0x40000
#define CONFIG_PHY_TERANETICS
#define SGMII_PHY_ADDR1 0x0
#define SGMII_PHY_ADDR2 0x1
#define SGMII_PHY_ADDR3 0x2

1
include/configs/advantech_dms-ba16.h
View File

@@ -55,7 +55,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHY_ATHEROS
/* Serial Flash */

1
include/configs/alt.h
View File

@@ -31,7 +31,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */

2
include/configs/am335x_evm.h
View File

@@ -285,9 +285,7 @@
/* SPI flash. */
/* Network. */
#define CONFIG_PHY_SMSC
/* Enable Atheros phy driver */
#define CONFIG_PHY_ATHEROS
/*
* NOR Size = 16 MiB

1
include/configs/am335x_igep003x.h
View File

@@ -101,7 +101,6 @@
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
/* Ethernet support */
#define CONFIG_PHY_SMSC
/* NAND support */
#define CONFIG_SYS_NAND_ONFI_DETECTION 1

1
include/configs/am335x_shc.h
View File

@@ -246,7 +246,6 @@
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_PHY_SMSC
/* I2C configuration */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */

1
include/configs/am335x_sl50.h
View File

@@ -81,6 +81,5 @@
#endif
/* Network. */
#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_AM335X_SL50_H */

2
include/configs/armadillo-800eva.h
View File

@@ -77,8 +77,6 @@
#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000
#define CONFIG_SH_ETHER_SH7734_MII (0x01)
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
#define CONFIG_PHY_SMSC
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */

1
include/configs/bav335x.h
View File

@@ -449,7 +449,6 @@ DEFAULT_LINUX_BOOT_ENV \
/* SPI flash. */
/* Network. */
#define CONFIG_PHY_SMSC
/*
* NOR Size = 16 MiB

1
include/configs/cgtqmx6eval.h
View File

@@ -79,7 +79,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 6
#define CONFIG_PHY_ATHEROS
/* Command definition */

1
include/configs/chiliboard.h
View File

@@ -167,6 +167,5 @@
#endif
/* Network. */
#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_CHILIBOARD_H */

2
include/configs/cl-som-imx7.h
View File

@@ -23,8 +23,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* ENET1 */
#define IMX_FEC_BASE ENET_IPS_BASE_ADDR

1
include/configs/cm_fx6.h
View File

@@ -165,7 +165,6 @@
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_FEC_XCV_TYPE RGMII
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_PHY_ATHEROS
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_NET_RETRY_COUNT 5

1
include/configs/cm_t335.h
View File

@@ -90,7 +90,6 @@
/* SPL */
/* Network. */
#define CONFIG_PHY_ATHEROS
/* NAND support */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE

1
include/configs/cm_t43.h
View File

@@ -45,7 +45,6 @@
/* CPSW Ethernet support */
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_PHY_ATHEROS
#define CONFIG_SYS_RX_ETH_BUFFER 64
/* USB support */

2
include/configs/condor.h
View File

@@ -12,7 +12,6 @@
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Environment compatibility */
@@ -24,7 +23,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */

1
include/configs/controlcenterdc.h
View File

@@ -54,7 +54,6 @@
/*
* Software (bit-bang) MII driver configuration
*/
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI
/* SPL */

6
include/configs/corenet_ds.h
View File

@@ -431,12 +431,6 @@
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_TERANETICS
#endif
#ifdef CONFIG_PCI
#if !defined(CONFIG_DM_PCI)
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */

1
include/configs/devkit3250.h
View File

@@ -65,7 +65,6 @@
* Ethernet
*/
#define CONFIG_RMII
#define CONFIG_PHY_SMSC
#define CONFIG_LPC32XX_ETH
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

1
include/configs/draak.h
View File

@@ -12,7 +12,6 @@
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Generic Timer Definitions (use in assembler source) */

2
include/configs/draco.h
View File

@@ -36,8 +36,6 @@
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
#define CONFIG_PHY_SMSC
#define CONFIG_FACTORYSET
/* Define own nand partitions */

1
include/configs/eagle.h
View File

@@ -12,7 +12,6 @@
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Environment compatibility */

1
include/configs/ebisu.h
View File

@@ -15,7 +15,6 @@
/* Ethernet RAVB */
#define CONFIG_NET_MULTI
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Generic Timer Definitions (use in assembler source) */

2
include/configs/embestmx6boards.h
View File

@@ -47,8 +47,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_PHY_ATHEROS
#define CONFIG_ARP_TIMEOUT 200UL
#define CONFIG_SYS_MEMTEST_START 0x10000000

2
include/configs/etamin.h
View File

@@ -93,8 +93,6 @@
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
#define CONFIG_PHY_SMSC
#define CONFIG_FACTORYSET
/* use both define to compile a SPL compliance test */

1
include/configs/gose.h
View File

@@ -27,7 +27,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */

1
include/configs/grpeach.h
View File

@@ -43,7 +43,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#endif /* __GRPEACH_H */

1
include/configs/helios4.h
View File

@@ -52,7 +52,6 @@
/* stay within first 1M */
#endif
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* Keep device tree and initrd in lower memory so the kernel can access them */

1
include/configs/hrcon.h
View File

@@ -293,7 +293,6 @@ void fpga_control_clear(unsigned int bus, int pin);
/*
* Software (bit-bang) MII driver configuration
*/
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI
/*

3
include/configs/imx8mq_evk.h
View File

@@ -82,9 +82,6 @@
#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#endif
#define CONFIG_MFG_ENV_SETTINGS \

2
include/configs/kmp204x.h
View File

@@ -318,8 +318,6 @@ int get_scl(void);
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
#define CONFIG_PHYLIB_10G
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */

1
include/configs/koelsch.h
View File

@@ -27,7 +27,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */

1
include/configs/lager.h
View File

@@ -28,7 +28,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */

2
include/configs/liteboard.h
View File

@@ -143,8 +143,6 @@
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_SMSC
#endif
#define CONFIG_IMX_THERMAL

2
include/configs/ls1021aiot.h
View File

@@ -174,8 +174,6 @@
#define CONFIG_ETHPRIME "eTSEC2"
#define CONFIG_PHY_ATHEROS
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2

2
include/configs/ls1021aqds.h
View File

@@ -419,8 +419,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_REALTEK
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2

3
include/configs/ls1043aqds.h
View File

@@ -35,9 +35,6 @@ unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHYLIB_10G
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C

5
include/configs/ls1043ardb.h
View File

@@ -258,11 +258,6 @@
#ifndef SPL_NO_FMAN
#define AQR105_IRQ_MASK 0x40000000
#ifdef CONFIG_NET
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2

3
include/configs/ls1046aqds.h
View File

@@ -52,9 +52,6 @@ unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHYLIB_10G
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C

5
include/configs/ls1046ardb.h
View File

@@ -170,11 +170,6 @@
#define AQR105_IRQ_MASK 0x80000000
/* FMan */
#ifndef SPL_NO_FMAN
#ifdef CONFIG_NET
#define CONFIG_PHY_REALTEK
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2

5
include/configs/ls1088aqds.h
View File

@@ -549,11 +549,6 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_FSL_MEMAC
#define CONFIG_PHYLIB
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
#define RGMII_PHY1_ADDR 0x1
#define RGMII_PHY2_ADDR 0x2
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C

3
include/configs/ls1088ardb.h
View File

@@ -522,9 +522,6 @@
/* MAC/PHY configuration */
#ifdef CONFIG_FSL_MC_ENET
#define CONFIG_PHYLIB
#define CONFIG_PHY_VITESSE
#define AQ_PHY_ADDR1 0x00
#define AQR105_IRQ_MASK 0x00000004

4
include/configs/ls2080aqds.h
View File

@@ -479,10 +479,6 @@ unsigned long get_board_ddr_clk(void);
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
#define CONFIG_FSL_MEMAC
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_VITESSE
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_TERANETICS
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E

1
include/configs/mx6cuboxi.h
View File

@@ -32,7 +32,6 @@
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_PHY_ATHEROS
/* Framebuffer */
#define CONFIG_VIDEO_BMP_RLE8

2
include/configs/mx6sxsabreauto.h
View File

@@ -134,8 +134,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

2
include/configs/mx6sxsabresd.h
View File

@@ -157,8 +157,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_ATHEROS
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)

1
include/configs/ot1200.h
View File

@@ -66,7 +66,6 @@
#define CONFIG_FEC_XCV_TYPE MII100
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x5
#define CONFIG_PHY_SMSC
#ifndef CONFIG_SPL
#define CONFIG_ENV_EEPROM_IS_ON_I2C

1
include/configs/p1_twr.h
View File

@@ -11,7 +11,6 @@
#if defined(CONFIG_TWR_P1025)
#define CONFIG_BOARDNAME "TWR-P1025"
#define CONFIG_PHY_ATHEROS
#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */
#define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */
#endif

2
include/configs/pcm051.h
View File

@@ -128,6 +128,4 @@
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_PCM051_H */

2
include/configs/pengwyn.h
View File

@@ -162,7 +162,5 @@
/* Network */
#define CONFIG_PHY_RESET 1
#define CONFIG_PHY_NATSEMI
#define CONFIG_PHY_REALTEK
#endif /* ! __CONFIG_PENGWYN_H */

1
include/configs/pic32mzdask.h
View File

@@ -57,7 +57,6 @@
/*-----------------------------------------------------------------------
* Networking Configuration
*/
#define CONFIG_PHY_SMSC
#define CONFIG_SYS_RX_ETH_BUFFER 8
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_ARP_TIMEOUT 500 /* millisec */

2
include/configs/pico-imx6.h
View File

@@ -146,8 +146,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 1
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
/* Framebuffer */
#define CONFIG_VIDEO_BMP_RLE8

1
include/configs/porter.h
View File

@@ -32,7 +32,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */

2
include/configs/pxm2.h
View File

@@ -36,8 +36,6 @@
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_PHY_ATHEROS
#define CONFIG_FACTORYSET
#ifndef CONFIG_SPL_BUILD

2
include/configs/rastaban.h
View File

@@ -41,8 +41,6 @@
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
#define CONFIG_PHY_SMSC
#define CONFIG_FACTORYSET
/* Define own nand partitions */

2
include/configs/rut.h
View File

@@ -31,8 +31,6 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
#define CONFIG_PHY_NATSEMI
#define CONFIG_FACTORYSET
/* Watchdog */

1
include/configs/salvator-x.h
View File

@@ -12,7 +12,6 @@
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Generic Timer Definitions (use in assembler source) */

1
include/configs/sc_sps_1.h
View File

@@ -28,7 +28,6 @@
/* FEC Ethernet on SoC */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
#define CONFIG_PHY_SMSC
#endif
/* USB */

2
include/configs/sh7752evb.h
View File

@@ -43,10 +43,8 @@
#define CONFIG_SH_ETHER_PHY_ADDR 18
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define CONFIG_SH_ETHER_USE_GETHER 1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
#define CONFIG_PHY_VITESSE
#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000
#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024)

2
include/configs/sh7753evb.h
View File

@@ -43,10 +43,8 @@
#define CONFIG_SH_ETHER_PHY_ADDR 18
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define CONFIG_SH_ETHER_USE_GETHER 1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
#define CONFIG_PHY_VITESSE
#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)

1
include/configs/sh7757lcr.h
View File

@@ -45,7 +45,6 @@
#define CONFIG_SH_ETHER_USE_PORT 0
#define CONFIG_SH_ETHER_PHY_ADDR 1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

1
include/configs/sh7763rdp.h
View File

@@ -64,7 +64,6 @@
/* Ether */
#define CONFIG_SH_ETHER_USE_PORT (1)
#define CONFIG_SH_ETHER_PHY_ADDR (0x01)
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

1
include/configs/silk.h
View File

@@ -32,7 +32,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */

1
include/configs/spear6xx_evb.h
View File

@@ -29,7 +29,6 @@
#define CONFIG_SYS_NAND_BASE 0xD2000000
/* Ethernet PHY configuration */
#define CONFIG_PHY_NATSEMI
/* Environment Settings */
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY

1
include/configs/stm32f746-disco.h
View File

@@ -33,7 +33,6 @@
#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8)
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_PHY_SMSC
#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */

1
include/configs/stout.h
View File

@@ -36,7 +36,6 @@
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */

1
include/configs/strider.h
View File

@@ -326,7 +326,6 @@ void fpga_control_clear(unsigned int bus, int pin);
/*
* Software (bit-bang) MII driver configuration
*/
#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI
/*

4
include/configs/sunxi-common.h
View File

@@ -272,10 +272,6 @@ extern int soft_i2c_gpio_scl;
/* Ethernet support */
#ifdef CONFIG_SUN7I_GMAC
#define CONFIG_PHY_REALTEK
#endif
#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1

1
include/configs/tb100.h
View File

@@ -38,7 +38,6 @@
* Until Realtek PHY driver is fixed fall back to generic PHY driver
* which implements all required functionality and behaves much more stable.
*
* #define CONFIG_PHY_REALTEK
*
*/

2
include/configs/thuban.h
View File

@@ -34,8 +34,6 @@
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
#define CONFIG_PHY_SMSC
#define CONFIG_FACTORYSET
/* Define own nand partitions */

1
include/configs/ti814x_evm.h
View File

@@ -152,7 +152,6 @@
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_PHY_ET1011C
#define CONFIG_PHY_ET1011C_TX_CLK_FIX
#endif /* ! __CONFIG_TI814X_EVM_H */

1
include/configs/tqma6_wru4.h
View File

@@ -10,7 +10,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0x01
#define CONFIG_PHY_SMSC
/* UART */
#define CONFIG_MXC_UART_BASE UART4_BASE

1
include/configs/ts4800.h
View File

@@ -50,7 +50,6 @@
/*
* Eth Configs
*/
#define CONFIG_PHY_SMSC
#define CONFIG_FEC_MXC
#define IMX_FEC_BASE FEC_BASE_ADDR

1
include/configs/turris_mox.h
View File

@@ -69,7 +69,6 @@
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_ARP_TIMEOUT 200
#define CONFIG_NET_RETRY_COUNT 50
#define CONFIG_PHY_MARVELL
#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3)

1
include/configs/ulcb.h
View File

@@ -12,7 +12,6 @@
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Generic Timer Definitions (use in assembler source) */

1
include/configs/vinco.h
View File

@@ -54,7 +54,6 @@
/* USB device */
/* Ethernet Hardware */
#define CONFIG_PHY_SMSC
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20

2
include/configs/vining_2000.h
View File

@@ -64,8 +64,6 @@
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_ATHEROS
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0

1
include/configs/work_92105.h
View File

@@ -46,7 +46,6 @@
* Ethernet Driver
*/
#define CONFIG_PHY_SMSC
#define CONFIG_LPC32XX_ETH
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */

1
include/configs/x530.h
View File

@@ -60,7 +60,6 @@
/* Environment in SPI NOR flash */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
/* PCIe support */

1
include/configs/xpress.h
View File

@@ -67,7 +67,6 @@
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_PHY_SMSC
#define CONFIG_IMX_THERMAL

1
include/configs/zc5202.h
View File

@@ -20,7 +20,6 @@
#define CONFIG_FEC_XCV_TYPE MII100
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_MV88E6352_SWITCH
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_PCIE_IMX