From 6a7b406aa8b98155597c408da0764fca85dec377 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 15 Jan 2019 22:26:37 +0800 Subject: [PATCH 01/40] fdt: support booting with dtb in Android image Some platforms choose to store device tree blob in Android image second area. Let's try to look for dtb from there when booting an Android image, and use it for booting if found. Signed-off-by: Shawn Guo --- common/image-fdt.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/common/image-fdt.c b/common/image-fdt.c index 5988808f18..94089b2215 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -268,6 +268,7 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, ulong load, load_end; ulong image_start, image_data, image_end; #endif + ulong img_addr; ulong fdt_addr; char *fdt_blob = NULL; void *buf; @@ -283,6 +284,9 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, *of_flat_tree = NULL; *of_size = 0; + img_addr = simple_strtoul(argv[0], NULL, 16); + buf = map_sysmem(img_addr, 0); + if (argc > 2) select = argv[2]; if (select || genimg_has_config(images)) { @@ -453,6 +457,23 @@ int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch, debug("## No Flattened Device Tree\n"); goto no_fdt; } +#ifdef CONFIG_ANDROID_BOOT_IMAGE + } else if (genimg_get_format(buf) == IMAGE_FORMAT_ANDROID) { + struct andr_img_hdr *hdr = buf; + ulong fdt_data, fdt_len; + + if (android_image_get_second(hdr, &fdt_data, &fdt_len) != 0) + goto no_fdt; + + fdt_blob = (char *)fdt_data; + if (fdt_check_header(fdt_blob) != 0) + goto no_fdt; + + if (fdt_totalsize(fdt_blob) != fdt_len) + goto error; + + debug("## Using FDT found in Android image second area\n"); +#endif } else { debug("## No Flattened Device Tree\n"); goto no_fdt; From 771ee9b6ede985f6d63a196885c799f616b90d08 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 28 Jan 2019 15:37:27 +0100 Subject: [PATCH 02/40] watchdog: bcm6345: switch to raw I/O functions This driver is used on several big endian mips board. So we could use raw I/O function instead of forcing big endian access. Signed-off-by: Philippe Reynes Reviewed-by: Daniel Schwierzeck --- drivers/watchdog/bcm6345_wdt.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/watchdog/bcm6345_wdt.c b/drivers/watchdog/bcm6345_wdt.c index e1bd73dfd4..44f5662038 100644 --- a/drivers/watchdog/bcm6345_wdt.c +++ b/drivers/watchdog/bcm6345_wdt.c @@ -32,8 +32,8 @@ static int bcm6345_wdt_reset(struct udevice *dev) { struct bcm6345_wdt_priv *priv = dev_get_priv(dev); - writel_be(WDT_CTL_START1_MASK, priv->regs + WDT_CTL_REG); - writel_be(WDT_CTL_START2_MASK, priv->regs + WDT_CTL_REG); + writel(WDT_CTL_START1_MASK, priv->regs + WDT_CTL_REG); + writel(WDT_CTL_START2_MASK, priv->regs + WDT_CTL_REG); return 0; } @@ -50,7 +50,7 @@ static int bcm6345_wdt_start(struct udevice *dev, u64 timeout, ulong flags) timeout = WDT_VAL_MAX; } - writel_be(timeout, priv->regs + WDT_VAL_REG); + writel(timeout, priv->regs + WDT_VAL_REG); return bcm6345_wdt_reset(dev); } @@ -64,8 +64,8 @@ static int bcm6345_wdt_stop(struct udevice *dev) { struct bcm6345_wdt_priv *priv = dev_get_priv(dev); - writel_be(WDT_CTL_STOP1_MASK, priv->regs + WDT_CTL_REG); - writel_be(WDT_CTL_STOP2_MASK, priv->regs + WDT_CTL_REG); + writel(WDT_CTL_STOP1_MASK, priv->regs + WDT_CTL_REG); + writel(WDT_CTL_STOP2_MASK, priv->regs + WDT_CTL_REG); return 0; } From 47b68d00a383daefdc233f4b92f016caf43d712b Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 28 Jan 2019 15:37:28 +0100 Subject: [PATCH 03/40] watchdog: bcm6345: allow to use this driver on arm bcm6858 This IP is also used on some arm SoC, so we allow to use it on arm bcm6858 too. Signed-off-by: Philippe Reynes --- drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 10fd3039aa..9456abd16b 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -88,7 +88,7 @@ config WDT_ASPEED config WDT_BCM6345 bool "BCM6345 watchdog timer support" - depends on WDT && ARCH_BMIPS + depends on WDT && (ARCH_BMIPS || ARCH_BCM6858) help Select this to enable watchdog timer for BCM6345 SoCs. The watchdog timer is stopped when initialized. From 09000365612298c6ef802f5a0eb25dd9b6a9583d Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 28 Jan 2019 15:37:29 +0100 Subject: [PATCH 04/40] dt: bcm6838: add watchdog This commit add watchdog and sysreset watchdog in the bcm6838 device tree. Signed-off-by: Philippe Reynes --- arch/mips/dts/brcm,bcm6838.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/mips/dts/brcm,bcm6838.dtsi b/arch/mips/dts/brcm,bcm6838.dtsi index 77d6a8e214..b6f9559147 100644 --- a/arch/mips/dts/brcm,bcm6838.dtsi +++ b/arch/mips/dts/brcm,bcm6838.dtsi @@ -73,6 +73,23 @@ status = "disabled"; }; + wdt0: watchdog@14e002d0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x14e002d0 0xc>; + clocks = <&periph_osc>; + }; + + wdt1: watchdog@14e002dc { + compatible = "brcm,bcm6345-wdt"; + reg = <0x14e002dc 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt0>; + }; + leds: led-controller@14e00f00 { compatible = "brcm,bcm6328-leds"; reg = <0x14e00f00 0x28>; From 8d6006f2ac8b58a936b4d6bb3a196a8f8ff39a6f Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 28 Jan 2019 15:37:30 +0100 Subject: [PATCH 05/40] dt: bcm6858: add watchdog This commit add watchdog and sysreset watchdog in the bcm6858 device tree. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm6858.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index d78d34d213..23b80c67a6 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -81,5 +81,22 @@ status = "disabled"; }; + + wdt1: watchdog@ff802780 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff802780 0x0 0x14>; + clocks = <&periph_osc>; + }; + + wdt2: watchdog@ff8027c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff8027c0 0x0 0x14>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; }; }; From c62bc60f11452a68b288bd6d79b0c9ab7f57856a Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 28 Jan 2019 15:37:31 +0100 Subject: [PATCH 06/40] bcm968380gerg: enable watchdog and reboot with watchdog Enable watchdog and reboot with watchdog in the configuration. Signed-off-by: Philippe Reynes --- configs/bcm968380gerg_ram_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig index 848d898ddf..61661bd756 100644 --- a/configs/bcm968380gerg_ram_defconfig +++ b/configs/bcm968380gerg_ram_defconfig @@ -44,4 +44,6 @@ CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_BCM6345=y CONFIG_LZO=y From 23463faa13672f3d7ec31c745a7e0b9c302ffc7b Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 28 Jan 2019 15:37:32 +0100 Subject: [PATCH 07/40] bcm968580: enable watchdog and reboot with watchdog Enable watchdog and reboot with watchdog in the configuration. Signed-off-by: Philippe Reynes --- configs/bcm968580_ram_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm968580_ram_defconfig b/configs/bcm968580_ram_defconfig index 56e0a56028..b23f960aaa 100644 --- a/configs/bcm968580_ram_defconfig +++ b/configs/bcm968580_ram_defconfig @@ -31,5 +31,7 @@ CONFIG_DM_SERIAL=y CONFIG_SERIAL_SEARCH_ALL=y CONFIG_BCM6345_SERIAL=y CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_BCM6345=y CONFIG_REGEX=y # CONFIG_GENERATE_SMBIOS_TABLE is not set From d8d250673d174c576fa65576bcec0bd6d75e9005 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 28 Jan 2019 11:43:22 -0600 Subject: [PATCH 08/40] defconfigs: dra7xx_hs_evm: Sync HS and non-HS defconfigs Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: Andrew F. Davis --- configs/dra7xx_hs_evm_defconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index f98ee470a9..3cf7659496 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_OMAP2PLUS=y CONFIG_TI_SECURE_DEVICE=y CONFIG_TI_COMMON_CMD_OPTIONS=y -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 CONFIG_OMAP54XX=y CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 @@ -37,13 +37,18 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 +CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y CONFIG_DWC_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y @@ -62,6 +67,7 @@ CONFIG_DM_MMC=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y From f5ca1cf79bffd47f2a4bb309cffc563da43e9249 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 28 Jan 2019 11:43:23 -0600 Subject: [PATCH 09/40] defconfigs: am57xx_hs_evm: Sync HS and non-HS defconfigs Additions have been made to the non-HS defconfig without the same being made to the HS defconfig, sync them. Signed-off-by: Andrew F. Davis --- configs/am57xx_hs_evm_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index f9805d24f3..7a0fd927b8 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_DMA_SUPPORT=y CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_PMIC is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" From 83ae64751201feea1536fd46b6dba5cebb4b0076 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 28 Jan 2019 11:43:24 -0600 Subject: [PATCH 10/40] defconfigs: Add config for DRA7xx High Security EVM with USB Boot support Add a new defconfig file for the DRA7xx High Security EVM. This config is specific for the case of USB booting. Signed-off-by: Andrew F. Davis Reviewed-by: Tom Rini --- MAINTAINERS | 1 + configs/dra7xx_hs_evm_usb_defconfig | 113 ++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 configs/dra7xx_hs_evm_usb_defconfig diff --git a/MAINTAINERS b/MAINTAINERS index 69131e4ffa..aa13aeda4d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -721,6 +721,7 @@ F: configs/am335x_hs_evm_uart_defconfig F: configs/am43xx_hs_evm_defconfig F: configs/am57xx_hs_evm_defconfig F: configs/dra7xx_hs_evm_defconfig +F: configs/dra7xx_hs_evm_usb_defconfig F: configs/k2hk_hs_evm_defconfig F: configs/k2e_hs_evm_defconfig F: configs/k2g_hs_evm_defconfig diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig new file mode 100644 index 0000000000..378b3d791c --- /dev/null +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_OMAP54XX=y +CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 +CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 +CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 +CONFIG_ISW_ENTRY_ADDR=0x40306d50 +CONFIG_TARGET_DRA7XX_EVM=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV7_LPAE=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_MISC_INIT_R is not set +CONFIG_VERSION_VARIABLE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DMA_SUPPORT=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" +CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm" +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 +CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_DWC_AHCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_PCF8575_GPIO=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_OMAP_HS=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_SPL_PHY=y +CONFIG_PIPE3_PHY=y +CONFIG_OMAP_USB2_PHY=y +CONFIG_PMIC_PALMAS=y +CONFIG_PMIC_LP873X=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_DM_REGULATOR_LP873X=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_TI_QSPI=y +CONFIG_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 From 995985c1fca633bda3b65a2bd3bdda6b9f1368e5 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 28 Jan 2019 11:43:25 -0600 Subject: [PATCH 11/40] defconfigs: Add config for AM57xx High Security EVM with USB/UART Boot support Add a new defconfig file for the AM57xx High Security EVM. This config is specific for the case of USB/UART booting. Signed-off-by: Andrew F. Davis Reviewed-by: Tom Rini --- MAINTAINERS | 1 + configs/am57xx_hs_evm_usb_defconfig | 98 +++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) create mode 100644 configs/am57xx_hs_evm_usb_defconfig diff --git a/MAINTAINERS b/MAINTAINERS index aa13aeda4d..29449ffed6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -720,6 +720,7 @@ F: configs/am335x_hs_evm_defconfig F: configs/am335x_hs_evm_uart_defconfig F: configs/am43xx_hs_evm_defconfig F: configs/am57xx_hs_evm_defconfig +F: configs/am57xx_hs_evm_usb_defconfig F: configs/dra7xx_hs_evm_defconfig F: configs/dra7xx_hs_evm_usb_defconfig F: configs/k2hk_hs_evm_defconfig diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig new file mode 100644 index 0000000000..6e4580ae39 --- /dev/null +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_TI_COMMON_CMD_OPTIONS=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_OMAP54XX=y +CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000 +CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 +CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 +CONFIG_ISW_ENTRY_ADDR=0x40306d50 +CONFIG_TARGET_AM57XX_EVM=y +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV7_LPAE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=beagle_x15board" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_MISC_INIT_R is not set +CONFIG_VERSION_VARIABLE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DMA_SUPPORT=y +# CONFIG_SPL_NAND_SUPPORT is not set +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SPL_YMODEM_SUPPORT=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_PMIC is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" +CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI_AHCI=y +# CONFIG_BLK is not set +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F000000 +CONFIG_FASTBOOT_USB_DEV=1 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_DRIVER_TI_CPSW=y +CONFIG_PHY=y +CONFIG_PIPE3_PHY=y +CONFIG_OMAP_USB2_PHY=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_PALMAS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_TI_QSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 From eca61ae70c80ce42272ab8b999750d925f0ad85c Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Mon, 28 Jan 2019 11:43:26 -0600 Subject: [PATCH 12/40] doc: ti-secure: Add ULO info for AM57xx/DRA7xx secure devices from TI Booting from UART and USB on HS devices is now supported for this platform. Update documentation for the same. Signed-off-by: Andrew F. Davis Reviewed-by: Tom Rini --- doc/README.ti-secure | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/doc/README.ti-secure b/doc/README.ti-secure index 4b5380c0f3..76950253ac 100644 --- a/doc/README.ti-secure +++ b/doc/README.ti-secure @@ -108,7 +108,8 @@ Booting of U-Boot SPL Invoking the script for DRA7xx/AM57xx Secure Devices ==================================================== - create-boot-image.sh + create-boot-image.sh \ + is a value that specifies the type of the image to generate OR the action the image generation tool will take. Valid @@ -116,7 +117,6 @@ Booting of U-Boot SPL X-LOADER - Generates an image for NOR or QSPI boot modes MLO - Generates an image for SD/MMC/eMMC boot modes ULO - Generates an image for USB/UART peripheral boot modes - Note: ULO is not yet used by the u-boot build process is the full path and filename of the public world boot loader binary file (for this platform, this is always u-boot-spl.bin). @@ -130,9 +130,13 @@ Booting of U-Boot SPL the device ROM bootloader requires for loading from the FAT partition of an SD card (same as on non-secure devices) + u-boot-spl_HS_ULO - boot image for USB/UART peripheral boot modes u-boot-spl_HS_X-LOADER - boot image for all other flash memories including QSPI and NOR flash + is the address at which SOC ROM should load the + + Invoking the script for Keystone2 Secure Devices ============================================= From 2dd0111adc8a5a03388f557d1ca91295276fbb54 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Wed, 30 Jan 2019 07:53:31 +0100 Subject: [PATCH 13/40] test: provide unit test for memory functions Memory functions may have architecture specific implementations. These should be tested. Provide unit tests for memset(), memcpy(), memmove(). Provide a 'ut lib' sub-command to execute the tests. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- include/test/lib.h | 14 +++ include/test/suites.h | 1 + test/Kconfig | 8 ++ test/cmd_ut.c | 6 ++ test/lib/Makefile | 2 + test/lib/cmd_ut_lib.c | 20 +++++ test/lib/string.c | 194 ++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 245 insertions(+) create mode 100644 include/test/lib.h create mode 100644 test/lib/cmd_ut_lib.c create mode 100644 test/lib/string.c diff --git a/include/test/lib.h b/include/test/lib.h new file mode 100644 index 0000000000..04b6241e54 --- /dev/null +++ b/include/test/lib.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Heinrich Schuchardt + */ + +#ifndef __TEST_LIB_H__ +#define __TEST_LIB_H__ + +#include + +/* Declare a new library function test */ +#define LIB_TEST(_name, _flags) UNIT_TEST(_name, _flags, lib_test) + +#endif /* __TEST_LIB_H__ */ diff --git a/include/test/suites.h b/include/test/suites.h index 77d863b4a6..01bee09346 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -27,6 +27,7 @@ int do_ut_bloblist(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ut_compression(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); int do_ut_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int do_ut_lib(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_overlay(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int do_ut_unicode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); diff --git a/test/Kconfig b/test/Kconfig index de16d179d0..48a0e501f8 100644 --- a/test/Kconfig +++ b/test/Kconfig @@ -6,6 +6,14 @@ menuconfig UNIT_TEST This does not require sandbox to be included, but it is most often used there. +config UT_LIB + bool "Unit tests for library functions" + depends on UNIT_TEST + default y + help + Enables the 'ut lib' command which tests library functions like + memcat(), memcyp(), memmove(). + config UT_TIME bool "Unit tests for time functions" depends on UNIT_TEST diff --git a/test/cmd_ut.c b/test/cmd_ut.c index 56924a5272..e3b89504e7 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -46,6 +46,9 @@ static cmd_tbl_t cmd_ut_sub[] = { #ifdef CONFIG_UT_OVERLAY U_BOOT_CMD_MKENT(overlay, CONFIG_SYS_MAXARGS, 1, do_ut_overlay, "", ""), #endif +#ifdef CONFIG_UT_LIB + U_BOOT_CMD_MKENT(lib, CONFIG_SYS_MAXARGS, 1, do_ut_lib, "", ""), +#endif #ifdef CONFIG_UT_TIME U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""), #endif @@ -108,6 +111,9 @@ static char ut_help_text[] = #ifdef CONFIG_UT_ENV "ut env [test-name]\n" #endif +#ifdef CONFIG_UT_LIB + "ut lib [test-name] - test library functions\n" +#endif #ifdef CONFIG_UT_OVERLAY "ut overlay [test-name]\n" #endif diff --git a/test/lib/Makefile b/test/lib/Makefile index 5a636aac74..308c61708e 100644 --- a/test/lib/Makefile +++ b/test/lib/Makefile @@ -2,5 +2,7 @@ # # (C) Copyright 2018 # Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc +obj-y += cmd_ut_lib.o obj-y += hexdump.o obj-y += lmb.o +obj-y += string.o diff --git a/test/lib/cmd_ut_lib.c b/test/lib/cmd_ut_lib.c new file mode 100644 index 0000000000..eb90e53914 --- /dev/null +++ b/test/lib/cmd_ut_lib.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Heinrich Schuchardt + * + * Unit tests for library functions + */ + +#include +#include +#include +#include +#include + +int do_ut_lib(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct unit_test *tests = ll_entry_start(struct unit_test, lib_test); + const int n_ents = ll_entry_count(struct unit_test, lib_test); + + return cmd_ut_category("lib", tests, n_ents, argc, argv); +} diff --git a/test/lib/string.c b/test/lib/string.c new file mode 100644 index 0000000000..8e246ab4ed --- /dev/null +++ b/test/lib/string.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Heinrich Schuchardt + * + * Unit tests for memory functions + * + * The architecture dependent implementations run through different lines of + * code depending on the alignment and length of memory regions copied or set. + * This has to be considered in testing. + */ + +#include +#include +#include +#include +#include + +/* Xor mask used for marking memory regions */ +#define MASK 0xA5 +/* Number of different alignment values */ +#define SWEEP 16 +/* Allow for copying up to 32 bytes */ +#define BUFLEN (SWEEP + 33) + +/** + * init_buffer() - initialize buffer + * + * The buffer is filled with incrementing values xor'ed with the mask. + * + * @buf: buffer + * @mask: xor mask + */ +static void init_buffer(u8 buf[], u8 mask) +{ + int i; + + for (i = 0; i < BUFLEN; ++i) + buf[i] = i ^ mask; +} + +/** + * test_memset() - test result of memset() + * + * @uts: unit test state + * @buf: buffer + * @mask: value set by memset() + * @offset: relative start of region changed by memset() in buffer + * @len: length of region changed by memset() + * Return: 0 = success, 1 = failure + */ +static int test_memset(struct unit_test_state *uts, u8 buf[], u8 mask, + int offset, int len) +{ + int i; + + for (i = 0; i < BUFLEN; ++i) { + if (i < offset || i >= offset + len) { + ut_asserteq(i, buf[i]); + } else { + ut_asserteq(mask, buf[i]); + } + } + return 0; +} + +/** + * lib_memset() - unit test for memset() + * + * Test memset() with varied alignment and length of the changed buffer. + * + * @uts: unit test state + * Return: 0 = success, 1 = failure + */ +static int lib_memset(struct unit_test_state *uts) +{ + u8 buf[BUFLEN]; + int offset, len; + void *ptr; + + for (offset = 0; offset <= SWEEP; ++offset) { + for (len = 1; len < BUFLEN - SWEEP; ++len) { + init_buffer(buf, 0); + ptr = memset(buf + offset, MASK, len); + ut_asserteq_ptr(buf + offset, (u8 *)ptr); + if (test_memset(uts, buf, MASK, offset, len)) { + debug("%s: failure %d, %d\n", + __func__, offset, len); + return CMD_RET_FAILURE; + } + } + } + return 0; +} + +LIB_TEST(lib_memset, 0); + +/** + * test_memmove() - test result of memcpy() or memmove() + * + * @uts: unit test state + * @buf: buffer + * @mask: xor mask used to initialize source buffer + * @offset1: relative start of copied region in source buffer + * @offset2: relative start of copied region in destination buffer + * @len: length of region changed by memset() + * Return: 0 = success, 1 = failure + */ +static int test_memmove(struct unit_test_state *uts, u8 buf[], u8 mask, + int offset1, int offset2, int len) +{ + int i; + + for (i = 0; i < BUFLEN; ++i) { + if (i < offset2 || i >= offset2 + len) { + ut_asserteq(i, buf[i]); + } else { + ut_asserteq((i + offset1 - offset2) ^ mask, buf[i]); + } + } + return 0; +} + +/** + * lib_memcpy() - unit test for memcpy() + * + * Test memcpy() with varied alignment and length of the copied buffer. + * + * @uts: unit test state + * Return: 0 = success, 1 = failure + */ +static int lib_memcpy(struct unit_test_state *uts) +{ + u8 buf1[BUFLEN]; + u8 buf2[BUFLEN]; + int offset1, offset2, len; + void *ptr; + + init_buffer(buf1, MASK); + + for (offset1 = 0; offset1 <= SWEEP; ++offset1) { + for (offset2 = 0; offset2 <= SWEEP; ++offset2) { + for (len = 1; len < BUFLEN - SWEEP; ++len) { + init_buffer(buf2, 0); + ptr = memcpy(buf2 + offset2, buf1 + offset1, + len); + ut_asserteq_ptr(buf2 + offset2, (u8 *)ptr); + if (test_memmove(uts, buf2, MASK, offset1, + offset2, len)) { + debug("%s: failure %d, %d, %d\n", + __func__, offset1, offset2, len); + return CMD_RET_FAILURE; + } + } + } + } + return 0; +} + +LIB_TEST(lib_memcpy, 0); + +/** + * lib_memmove() - unit test for memmove() + * + * Test memmove() with varied alignment and length of the copied buffer. + * + * @uts: unit test state + * Return: 0 = success, 1 = failure + */ +static int lib_memmove(struct unit_test_state *uts) +{ + u8 buf[BUFLEN]; + int offset1, offset2, len; + void *ptr; + + for (offset1 = 0; offset1 <= SWEEP; ++offset1) { + for (offset2 = 0; offset2 <= SWEEP; ++offset2) { + for (len = 1; len < BUFLEN - SWEEP; ++len) { + init_buffer(buf, 0); + ptr = memmove(buf + offset2, buf + offset1, + len); + ut_asserteq_ptr(buf + offset2, (u8 *)ptr); + if (test_memmove(uts, buf, 0, offset1, offset2, + len)) { + debug("%s: failure %d, %d, %d\n", + __func__, offset1, offset2, len); + return CMD_RET_FAILURE; + } + } + } + } + return 0; +} + +LIB_TEST(lib_memmove, 0); From 36fddec14b1447055d91b13a0ba3997e66ecec35 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 30 Jan 2019 20:19:28 +1300 Subject: [PATCH 14/40] omap3_cairo: remove empty #ifdef/#endif block The content between these guards was removed in commit 9baa2bce2890 ("Removed unused references to CONFIG_SERIALx"). Remove the now empty #ifdef/#endif block and the accompanying comment. Signed-off-by: Chris Packham --- include/configs/omap3_cairo.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h index 04bce2f8b4..ef69b24dd0 100644 --- a/include/configs/omap3_cairo.h +++ b/include/configs/omap3_cairo.h @@ -190,16 +190,6 @@ /* env defaults */ #define CONFIG_BOOTFILE "uImage" -/* Override OMAP3 common serial console configuration from UART3 - * to UART2. - * - * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) - * are needed and peripheral clocks for UART2 must be enabled in - * function per_clocks_enable(). - */ -#ifdef CONFIG_SPL_BUILD -#endif - /* Provide the MACH_TYPE value the vendor kernel requires */ #define CONFIG_MACH_TYPE 3063 From 4d9dbb1fbb7c47ebb4390d6aaa35aa4254db06d4 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 30 Jan 2019 20:23:16 +1300 Subject: [PATCH 15/40] moveconfig: add a second pass for empty #if/#endif blocks Moveconfig already attempts to remove empty #if/#endif blocks when there is a matching CONFIG_ being moved. Add a second pass which covers files without a match. Signed-off-by: Chris Packham --- tools/moveconfig.py | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/tools/moveconfig.py b/tools/moveconfig.py index caa81ac2ed..1a214c5605 100755 --- a/tools/moveconfig.py +++ b/tools/moveconfig.py @@ -545,6 +545,28 @@ def confirm(options, prompt): return True +def cleanup_empty_blocks(header_path, options): + """Clean up empty conditional blocks + + Arguments: + header_path: path to the cleaned file. + options: option flags. + """ + pattern = re.compile(r'^\s*#\s*if.*$\n^\s*#\s*endif.*$\n*', flags=re.M) + with open(header_path) as f: + data = f.read() + + new_data = pattern.sub('\n', data) + + show_diff(data.splitlines(True), new_data.splitlines(True), header_path, + options.color) + + if options.dry_run: + return + + with open(header_path, 'w') as f: + f.write(new_data) + def cleanup_one_header(header_path, patterns, options): """Clean regex-matched lines away from a file. @@ -626,8 +648,9 @@ def cleanup_headers(configs, options): continue for filename in filenames: if not fnmatch.fnmatch(filename, '*~'): - cleanup_one_header(os.path.join(dirpath, filename), - patterns, options) + header_path = os.path.join(dirpath, filename) + cleanup_one_header(header_path, patterns, options) + cleanup_empty_blocks(header_path, options) def cleanup_one_extra_option(defconfig_path, configs, options): """Delete config defines in CONFIG_SYS_EXTRA_OPTIONS in one defconfig file. From 9dfdbd9f0c69c6c8005bc41ac602c27023492ee8 Mon Sep 17 00:00:00 2001 From: Roman Kapl Date: Wed, 30 Jan 2019 11:39:54 +0100 Subject: [PATCH 16/40] hashtable: fix environment variable corruption Only first previously deleted entry was recognized, leading hsearch_r to think that there was no previously deleted entry. It then conluded that a free entry was found, even if there were no free entries and it overwrote a random entry. This patch makes sure all deleted or free entries are always found and also introduces constants for the 0 and -1 numbers. Unit tests to excersise a simple hash table usage and catch the corruption were added. To trash your environment, simply run this loop: setenv i 0 while true; do setenv v_$i $i setenv v_$i setexpr i $i + 1 done Signed-off-by: Roman Kapl --- lib/hashtable.c | 13 +++-- test/env/Makefile | 1 + test/env/hashtable.c | 125 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 136 insertions(+), 3 deletions(-) create mode 100644 test/env/hashtable.c diff --git a/lib/hashtable.c b/lib/hashtable.c index 50ff40a397..0d288d12d9 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -40,6 +40,9 @@ #define CONFIG_ENV_MAX_ENTRIES 512 #endif +#define USED_FREE 0 +#define USED_DELETED -1 + #include #include #include @@ -303,7 +306,7 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, */ unsigned hval2; - if (htab->table[idx].used == -1 + if (htab->table[idx].used == USED_DELETED && !first_deleted) first_deleted = idx; @@ -335,13 +338,17 @@ int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, if (idx == hval) break; + if (htab->table[idx].used == USED_DELETED + && !first_deleted) + first_deleted = idx; + /* If entry is found use it. */ ret = _compare_and_overwrite_entry(item, action, retval, htab, flag, hval, idx); if (ret != -1) return ret; } - while (htab->table[idx].used); + while (htab->table[idx].used != USED_FREE); } /* An empty bucket has been found. */ @@ -433,7 +440,7 @@ static void _hdelete(const char *key, struct hsearch_data *htab, ENTRY *ep, free(ep->data); ep->callback = NULL; ep->flags = 0; - htab->table[idx].used = -1; + htab->table[idx].used = USED_DELETED; --htab->filled; } diff --git a/test/env/Makefile b/test/env/Makefile index d71a11b6e2..5c8eae31b0 100644 --- a/test/env/Makefile +++ b/test/env/Makefile @@ -4,3 +4,4 @@ obj-y += cmd_ut_env.o obj-y += attr.o +obj-y += hashtable.o diff --git a/test/env/hashtable.c b/test/env/hashtable.c new file mode 100644 index 0000000000..8c87e65457 --- /dev/null +++ b/test/env/hashtable.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * (C) Copyright 2019 + * Roman Kapl, SYSGO, rka@sysgo.com + */ + +#include +#include +#include +#include +#include +#include + +#define SIZE 32 +#define ITERATIONS 10000 + +static int htab_fill(struct unit_test_state *uts, + struct hsearch_data *htab, size_t size) +{ + size_t i; + ENTRY item; + ENTRY *ritem; + char key[20]; + + for (i = 0; i < size; i++) { + sprintf(key, "%d", (int)i); + item.callback = NULL; + item.data = key; + item.flags = 0; + item.key = key; + ut_asserteq(1, hsearch_r(item, ENTER, &ritem, htab, 0)); + } + + return 0; +} + +static int htab_check_fill(struct unit_test_state *uts, + struct hsearch_data *htab, size_t size) +{ + size_t i; + ENTRY item; + ENTRY *ritem; + char key[20]; + + for (i = 0; i < size; i++) { + sprintf(key, "%d", (int)i); + item.callback = NULL; + item.flags = 0; + item.data = key; + item.key = key; + hsearch_r(item, FIND, &ritem, htab, 0); + ut_assert(ritem); + ut_asserteq_str(key, ritem->key); + ut_asserteq_str(key, ritem->data); + } + + return 0; +} + +static int htab_create_delete(struct unit_test_state *uts, + struct hsearch_data *htab, size_t iterations) +{ + size_t i; + ENTRY item; + ENTRY *ritem; + char key[20]; + + for (i = 0; i < iterations; i++) { + sprintf(key, "cd-%d", (int)i); + item.callback = NULL; + item.flags = 0; + item.data = key; + item.key = key; + hsearch_r(item, ENTER, &ritem, htab, 0); + ritem = NULL; + + hsearch_r(item, FIND, &ritem, htab, 0); + ut_assert(ritem); + ut_asserteq_str(key, ritem->key); + ut_asserteq_str(key, ritem->data); + + ut_asserteq(1, hdelete_r(key, htab, 0)); + } + + return 0; +} + +/* Completely fill up the hash table */ +static int env_test_htab_fill(struct unit_test_state *uts) +{ + struct hsearch_data htab; + + memset(&htab, 0, sizeof(htab)); + ut_asserteq(1, hcreate_r(SIZE, &htab)); + + ut_assertok(htab_fill(uts, &htab, SIZE)); + ut_assertok(htab_check_fill(uts, &htab, SIZE)); + ut_asserteq(SIZE, htab.filled); + + hdestroy_r(&htab); + return 0; +} + +ENV_TEST(env_test_htab_fill, 0); + +/* Fill the hashtable up halfway an repeateadly delete/create elements + * and check for corruption + */ +static int env_test_htab_deletes(struct unit_test_state *uts) +{ + struct hsearch_data htab; + + memset(&htab, 0, sizeof(htab)); + ut_asserteq(1, hcreate_r(SIZE, &htab)); + + ut_assertok(htab_fill(uts, &htab, SIZE / 2)); + ut_assertok(htab_create_delete(uts, &htab, ITERATIONS)); + ut_assertok(htab_check_fill(uts, &htab, SIZE / 2)); + ut_asserteq(SIZE / 2, htab.filled); + + hdestroy_r(&htab); + return 0; +} + +ENV_TEST(env_test_htab_deletes, 0); From ba8ba69b66923362a379822d77a6e78c117721e1 Mon Sep 17 00:00:00 2001 From: Vabhav Sharma Date: Wed, 30 Jan 2019 11:24:00 +0000 Subject: [PATCH 17/40] drivers: serial: dm: Enable DM_FLAG_PRE_RELOC in SBSA pl011 uart driver The DM_FLAG_PRE_RELOC shall be enabled in SBSA PL011 uart driver as this driver is used in NXP based SoCs It is necessary to have Serial console running before relocation The !CONFIG_IS_ENABLED(OF_CONTROL) [*] check is set as "workaround" for DM problem : 4687919684e This flag is set if board does not support device-tree and using platform data, In DM Model either of device tree or platform data can be used to fetch device configuration It is possible to use SBSA UART with CONFIG_DM_SERIAL but witout corresponding device tree description (OF_CONTROL) Other board/SoCs have this flag set unconditionally Signed-off-by: Vabhav Sharma --- drivers/serial/serial_pl01x.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index 12512f6578..2a5f256184 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -363,9 +363,7 @@ U_BOOT_DRIVER(serial_pl01x) = { .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata), .probe = pl01x_serial_probe, .ops = &pl01x_serial_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) .flags = DM_FLAG_PRE_RELOC, -#endif .priv_auto_alloc_size = sizeof(struct pl01x_priv), }; From 86617dd1402c506a989da74f1f9c13ce1580fa82 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Jan 2019 13:07:00 +0100 Subject: [PATCH 18/40] clk: stm32mp1: no more get ck_usbo_48m in device tree Remove support of ck_usbo_48m clock node in device tree, but force 48MHz frequency to prepare alignment with kernel device tree. Signed-off-by: Patrick Delaunay --- drivers/clk/clk_stm32mp1.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index b7c5d34fe0..88f453caa8 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -241,7 +241,6 @@ enum stm32mp1_parent_id { _LSI, _LSE, _I2S_CKIN, - _USB_PHY_48, NB_OSC, /* other parent source */ @@ -273,6 +272,7 @@ enum stm32mp1_parent_id { _CK_MPU, _CK_MCU, _DSI_PHY, + _USB_PHY_48, _PARENT_NB, _UNKNOWN_ID = 0xff, }; @@ -1079,7 +1079,7 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) break; /* other */ case _USB_PHY_48: - clock = stm32mp1_clk_get_fixed(priv, _USB_PHY_48); + clock = 48000000; break; case _DSI_PHY: { @@ -1859,7 +1859,7 @@ static void stm32mp1_osc_init(struct udevice *dev) [_HSE] = "clk-hse", [_CSI] = "clk-csi", [_I2S_CKIN] = "i2s_ckin", - [_USB_PHY_48] = "ck_usbo_48m"}; + }; for (i = 0; i < NB_OSC; i++) { stm32mp1_osc_clk_init(name[i], priv, i); From d661f61847696dc5ac54b397908f886bd3583484 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Jan 2019 13:07:01 +0100 Subject: [PATCH 19/40] clk: stm32mp1: add IPCC clock Add support for enable/disable of IPCC clock using AHB3 registers Signed-off-by: Patrick Delaunay --- drivers/clk/clk_stm32mp1.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 88f453caa8..a2ab5ed263 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -536,6 +536,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), From 63201281e5e51116676bf3a2b028035856d3f2a6 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Jan 2019 13:07:02 +0100 Subject: [PATCH 20/40] clk: stm32mp1: correct access to RCC_OCENSETR/RCC_OCENCLRR Remove unnecessary setbits on set/clear registers. Avoid to deactivate HSI with HSE. Signed-off-by: Patrick Delaunay --- drivers/clk/clk_stm32mp1.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index a2ab5ed263..39eaf64cdd 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -1180,10 +1180,7 @@ static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) { - if (enable) - setbits_le32(rcc + RCC_OCENSETR, mask_on); - else - setbits_le32(rcc + RCC_OCENCLRR, mask_on); + writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); } static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, @@ -1254,20 +1251,20 @@ static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable) static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css) { if (digbyp) - setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_DIGBYP); + writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR); if (bypass || digbyp) - setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSEBYP); + writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR); stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY); if (css) - setbits_le32(rcc + RCC_OCENSETR, RCC_OCENR_HSECSSON); + writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR); } static void stm32mp1_csi_set(fdt_addr_t rcc, int enable) { - stm32mp1_ls_osc_set(enable, rcc, RCC_OCENSETR, RCC_OCENR_CSION); + stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION); stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY); } From f3a23c26097144de9ad08644a4bfc9c238df873a Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Jan 2019 13:07:03 +0100 Subject: [PATCH 21/40] clk: stm32mp1: recalculate counter when switching freq Because stgen is initialized with HSI clock, we need to recalculate the counter when changing frequency. Signed-off-by: Lionel Debieve Signed-off-by: Patrick Delaunay --- drivers/clk/clk_stm32mp1.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 39eaf64cdd..916f9f9e8c 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -1469,10 +1469,15 @@ static void stgen_config(struct stm32mp1_clk_priv *priv) rate = stm32mp1_clk_get(priv, p); if (cntfid0 != rate) { + u64 counter; + pr_debug("System Generic Counter (STGEN) update\n"); clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); - writel(0x0, stgenc + STGENC_CNTCVL); - writel(0x0, stgenc + STGENC_CNTCVU); + counter = (u64)readl(stgenc + STGENC_CNTCVL); + counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32; + counter = lldiv(counter * (u64)rate, cntfid0); + writel((u32)counter, stgenc + STGENC_CNTCVL); + writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU); writel(rate, stgenc + STGENC_CNTFID0); setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); From 8d6310aa0ba2bee92e14c0702c5ceec64943383a Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Jan 2019 13:07:04 +0100 Subject: [PATCH 22/40] clk: stm32mp1: add debug information Add support of clk dump command and display information during probe (under CONFIG_DISPLAY_CPUINFO). Signed-off-by: Patrick Delaunay --- configs/stm32mp15_basic_defconfig | 1 + drivers/clk/clk_stm32mp1.c | 83 +++++++++++++++++++++++++++++-- 2 files changed, 80 insertions(+), 4 deletions(-) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 304688e56f..d20b2ab350 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 916f9f9e8c..09227cf8db 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -666,8 +666,8 @@ static const u8 stm32mp1_axi_div[8] = { 1, 2, 3, 4, 4, 4, 4, 4 }; -#ifdef DEBUG -static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { +static const __maybe_unused +char * const stm32mp1_clk_parent_name[_PARENT_NB] = { [_HSI] = "HSI", [_HSE] = "HSE", [_CSI] = "CSI", @@ -705,7 +705,8 @@ static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = { [_DSI_PHY] = "DSI_PHY_PLL", }; -static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { +static const __maybe_unused +char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { [_I2C12_SEL] = "I2C12", [_I2C35_SEL] = "I2C35", [_I2C46_SEL] = "I2C46", @@ -724,7 +725,6 @@ static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = { [_DSI_SEL] = "DSI", [_ADC12_SEL] = "ADC12", }; -#endif static const struct stm32mp1_clk_data stm32mp1_data = { .gate = stm32mp1_clk_gate, @@ -1870,6 +1870,54 @@ static void stm32mp1_osc_init(struct udevice *dev) } } +static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv) +{ + char buf[32]; + int i, s, p; + + printf("Clocks:\n"); + for (i = 0; i < _PARENT_NB; i++) { + printf("- %s : %s MHz\n", + stm32mp1_clk_parent_name[i], + strmhz(buf, stm32mp1_clk_get(priv, i))); + } + printf("Source Clocks:\n"); + for (i = 0; i < _PARENT_SEL_NB; i++) { + p = (readl(priv->base + priv->data->sel[i].offset) >> + priv->data->sel[i].src) & priv->data->sel[i].msk; + if (p < priv->data->sel[i].nb_parent) { + s = priv->data->sel[i].parent[p]; + printf("- %s(%d) => parent %s(%d)\n", + stm32mp1_clk_parent_sel_name[i], i, + stm32mp1_clk_parent_name[s], s); + } else { + printf("- %s(%d) => parent index %d is invalid\n", + stm32mp1_clk_parent_sel_name[i], i, p); + } + } +} + +#ifdef CONFIG_CMD_CLK +int soc_clk_dump(void) +{ + struct udevice *dev; + struct stm32mp1_clk_priv *priv; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(stm32mp1_clock), + &dev); + if (ret) + return ret; + + priv = dev_get_priv(dev); + + stm32mp1_clk_dump(priv); + + return 0; +} +#endif + static int stm32mp1_clk_probe(struct udevice *dev) { int result = 0; @@ -1893,6 +1941,33 @@ static int stm32mp1_clk_probe(struct udevice *dev) result = stm32mp1_clktree(dev); #endif +#ifndef CONFIG_SPL_BUILD +#if defined(DEBUG) + /* display debug information for probe after relocation */ + if (gd->flags & GD_FLG_RELOC) + stm32mp1_clk_dump(priv); +#endif + +#if defined(CONFIG_DISPLAY_CPUINFO) + if (gd->flags & GD_FLG_RELOC) { + char buf[32]; + + printf("Clocks:\n"); + printf("- MPU : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU))); + printf("- MCU : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU))); + printf("- AXI : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _ACLK))); + printf("- PER : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _CK_PER))); + /* DDRPHYC father */ + printf("- DDR : %s MHz\n", + strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R))); + } +#endif /* CONFIG_DISPLAY_CPUINFO */ +#endif + return result; } From e74b74c52876d776dda7a7ee5e2a8d555eaa5c4f Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Jan 2019 13:07:05 +0100 Subject: [PATCH 23/40] dts: stm32mp1: clock tree update - Add st,digbypass on clk_hse node (needed for board rev.C) - MLAHB/AHB max frequency increased from 200 to 209MHz, with: - PLL3P set to 208.8MHz for MCU sub-system - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S - PLL4P set to 99MHz for SDMMC and SPDIFRX - PLL4Q set to 74.25MHz for EVAL board Signed-off-by: Patrick Delaunay --- arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 27 +++++++++++++---------- include/dt-bindings/clock/stm32mp1-clks.h | 3 --- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 4898483e1d..70bbf66704 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -39,6 +39,10 @@ }; }; +&clk_hse { + st,digbypass; +}; + &uart4_pins_a { u-boot,dm-pre-reloc; pins1 { @@ -68,7 +72,6 @@ u-boot,dm-pre-reloc; }; -/* CLOCK init */ &rcc { st,clksrc = < CLK_MPU_PLL1P @@ -101,7 +104,7 @@ CLK_FMC_ACLK CLK_QSPI_ACLK CLK_ETH_DISABLED - CLK_SDMMC12_PLL3R + CLK_SDMMC12_PLL4P CLK_DSI_DSIPLL CLK_STGEN_HSE CLK_USBPHY_HSE @@ -110,7 +113,7 @@ CLK_SPI45_HSI CLK_SPI6_HSI CLK_I2C46_HSI - CLK_SDMMC3_PLL3R + CLK_SDMMC3_PLL4P CLK_USBO_USBPHY CLK_ADC_CKPER CLK_CEC_LSE @@ -121,17 +124,17 @@ CLK_UART35_HSI CLK_UART6_HSI CLK_UART78_HSI - CLK_SPDIF_PLL3Q + CLK_SPDIF_PLL4P CLK_FDCAN_PLL4Q CLK_SAI1_PLL3Q CLK_SAI2_PLL3Q CLK_SAI3_PLL3Q CLK_SAI4_PLL3Q - CLK_RNG1_CSI - CLK_RNG2_CSI + CLK_RNG1_LSI + CLK_RNG2_LSI CLK_LPTIM1_PCLK1 CLK_LPTIM23_PCLK3 - CLK_LPTIM45_PCLK3 + CLK_LPTIM45_LSE >; /* VCO = 1300.0 MHz => P = 650 (CPU) */ @@ -148,16 +151,16 @@ u-boot,dm-pre-reloc; }; - /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */ + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ pll3: st,pll@2 { - cfg = < 2 97 3 15 7 PQR(1,1,1) >; - frac = < 0x9ba >; + cfg = < 1 33 1 16 36 PQR(1,1,1) >; + frac = < 0x1a04 >; u-boot,dm-pre-reloc; }; - /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ + /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ pll4: st,pll@3 { - cfg = < 5 126 8 8 8 PQR(1,1,1) >; + cfg = < 3 98 5 7 7 PQR(1,1,1) >; u-boot,dm-pre-reloc; }; }; diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 90ec780bfc..4cdaf13582 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,7 +248,4 @@ #define STM32MP1_LAST_CLK 232 -#define LTDC_K LTDC_PX -#define ETHMAC_K ETHCK_K - #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ From bbd108a08225b1239b1ec1c10e8131fba6a3a95a Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 30 Jan 2019 13:07:06 +0100 Subject: [PATCH 24/40] clk: stm32mp1: correctly handle Clock Spreading Generator To activate the csg option, the driver need to set the bit2 of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator of PLLn enable. Signed-off-by: Patrick Delaunay --- doc/device-tree-bindings/clock/st,stm32mp1.txt | 10 +++++----- drivers/clk/clk_stm32mp1.c | 8 +++++++- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt index 6a9397e105..ffcf8cd31d 100644 --- a/doc/device-tree-bindings/clock/st,stm32mp1.txt +++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt @@ -132,15 +132,15 @@ Optional Properties: frac = < 0x810 >; }; st,pll@1 { - cfg = < 1 43 1 0 0 PQR(0,1,1)>; - csg = <10 20 1>; + cfg = < 1 43 1 0 0 PQR(0,1,1) >; + csg = < 10 20 1 >; }; st,pll@2 { - cfg = < 2 85 3 13 3 0>; - csg = <10 20 SSCG_MODE_CENTER_SPREAD>; + cfg = < 2 85 3 13 3 0 >; + csg = < 10 20 SSCG_MODE_CENTER_SPREAD >; }; st,pll@3 { - cfg = < 2 78 4 7 9 3>; + cfg = < 2 78 4 7 9 3 >; }; st,pkcs = < CLK_STGEN_HSE diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 09227cf8db..aebc6f0a34 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -165,6 +165,7 @@ /* used for ALL PLLNCR registers */ #define RCC_PLLNCR_PLLON BIT(0) #define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) #define RCC_PLLNCR_DIVPEN BIT(4) #define RCC_PLLNCR_DIVQEN BIT(5) #define RCC_PLLNCR_DIVREN BIT(6) @@ -1319,7 +1320,10 @@ static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id) { const struct stm32mp1_clk_pll *pll = priv->data->pll; - writel(RCC_PLLNCR_PLLON, priv->base + pll[pll_id].pllxcr); + clrsetbits_le32(priv->base + pll[pll_id].pllxcr, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | + RCC_PLLNCR_DIVREN, + RCC_PLLNCR_PLLON); } static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output) @@ -1438,6 +1442,8 @@ static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg) RCC_PLLNCSGR_SSCG_MODE_MASK); writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr); + + setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL); } static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) From 351a4aa050c834954498e2114cab3429597b7c92 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Wed, 30 Jan 2019 18:08:42 +0530 Subject: [PATCH 25/40] mmc: omap_hsmmc: Workaround errata regarding SDR104/HS200 tuning failures (i929) Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions (SPRZ426D - November 2014 - Revised February 2018 [1]) mentions unexpected tuning pattern errors. A small failure band may be present in the tuning range which may be missed by the current algorithm. Furthermore, the failure bands vary with temperature leading to different optimum tuning values for different temperatures. As suggested in the related Application Report (SPRACA9B - October 2017 - Revised July 2018 [2]), tuning should be done in two stages. In stage 1, assign the optimum ratio in the maximum pass window for the current temperature. In stage 2, if the chosen value is close to the small failure band, move away from it in the appropriate direction. References: [1] http://www.ti.com/lit/pdf/sprz426 [2] http://www.ti.com/lit/pdf/SPRACA9 Signed-off-by: Faiz Abbas --- drivers/mmc/omap_hsmmc.c | 92 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 5cb97eb02a..b11c71cae7 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -47,6 +47,7 @@ #endif #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -622,6 +623,10 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) u32 phase_delay = 0; u32 start_window = 0, max_window = 0; u32 length = 0, max_len = 0; + bool single_point_failure = false; + struct udevice *thermal_dev; + int temperature; + int i; mmc_base = priv->base_addr; val = readl(&mmc_base->capa2); @@ -632,9 +637,25 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50)))) return 0; + ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev); + if (ret) { + printf("Couldn't get thermal device for tuning\n"); + return ret; + } + ret = thermal_get_temp(thermal_dev, &temperature); + if (ret) { + printf("Couldn't get temperature for tuning\n"); + return ret; + } val = readl(&mmc_base->dll); val |= DLL_SWT; writel(val, &mmc_base->dll); + + /* + * Stage 1: Search for a maximum pass window ignoring any + * any single point failures. If the tuning value ends up + * near it, move away from it in stage 2 below + */ while (phase_delay <= MAX_PHASE_DELAY) { omap_hsmmc_set_dll(mmc, phase_delay); @@ -643,10 +664,16 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) if (cur_match) { if (prev_match) { length++; + } else if (single_point_failure) { + /* ignore single point failure */ + length++; + single_point_failure = false; } else { start_window = phase_delay; length = 1; } + } else { + single_point_failure = prev_match; } if (length > max_len) { @@ -668,8 +695,71 @@ static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode) ret = -EIO; goto tuning_error; } + /* + * Assign tuning value as a ratio of maximum pass window based + * on temperature + */ + if (temperature < -20000) + phase_delay = min(max_window + 4 * max_len - 24, + max_window + + DIV_ROUND_UP(13 * max_len, 16) * 4); + else if (temperature < 20000) + phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4; + else if (temperature < 40000) + phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4; + else if (temperature < 70000) + phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4; + else if (temperature < 90000) + phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4; + else if (temperature < 120000) + phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4; + else + phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4; + + /* + * Stage 2: Search for a single point failure near the chosen tuning + * value in two steps. First in the +3 to +10 range and then in the + * +2 to -10 range. If found, move away from it in the appropriate + * direction by the appropriate amount depending on the temperature. + */ + for (i = 3; i <= 10; i++) { + omap_hsmmc_set_dll(mmc, phase_delay + i); + if (mmc_send_tuning(mmc, opcode, NULL)) { + if (temperature < 10000) + phase_delay += i + 6; + else if (temperature < 20000) + phase_delay += i - 12; + else if (temperature < 70000) + phase_delay += i - 8; + else if (temperature < 90000) + phase_delay += i - 6; + else + phase_delay += i - 6; + + goto single_failure_found; + } + } + + for (i = 2; i >= -10; i--) { + omap_hsmmc_set_dll(mmc, phase_delay + i); + if (mmc_send_tuning(mmc, opcode, NULL)) { + if (temperature < 10000) + phase_delay += i + 12; + else if (temperature < 20000) + phase_delay += i + 8; + else if (temperature < 70000) + phase_delay += i + 8; + else if (temperature < 90000) + phase_delay += i + 10; + else + phase_delay += i + 12; + + goto single_failure_found; + } + } + +single_failure_found: - phase_delay = max_window + 4 * ((3 * max_len) >> 2); omap_hsmmc_set_dll(mmc, phase_delay); mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD); From a9484aa769b0f8312abbfa5698b685e188eea78e Mon Sep 17 00:00:00 2001 From: Hannes Schmelzer Date: Thu, 31 Jan 2019 09:24:45 +0100 Subject: [PATCH 26/40] board/BuR/brppt1: drop DM_I2C_COMPAT The TPS62517 PMIC driver has been partially converted to DM, so the legacy I2C access layer isn't needed anymore. Signed-off-by: Hannes Schmelzer --- board/BuR/brppt1/board.c | 5 ++--- board/BuR/brxre1/board.c | 2 +- board/BuR/common/bur_common.h | 2 +- board/BuR/common/common.c | 7 ++++--- configs/brppt1_mmc_defconfig | 1 - configs/brppt1_nand_defconfig | 1 - configs/brppt1_spi_defconfig | 1 - 7 files changed, 8 insertions(+), 11 deletions(-) diff --git a/board/BuR/brppt1/board.c b/board/BuR/brppt1/board.c index d2e7c72242..b8ab19c0e7 100644 --- a/board/BuR/brppt1/board.c +++ b/board/BuR/brppt1/board.c @@ -106,9 +106,8 @@ void am33xx_spl_board_init(void) /* setup I2C */ enable_i2c_pin_mux(); - i2c_set_bus_num(0); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - pmicsetup(0); + + pmicsetup(0, 0); /* peripheral reset */ rc = gpio_request(64 + 29, "GPMC_WAIT1"); diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c index 41ed28b4bc..82c53d5bc2 100644 --- a/board/BuR/brxre1/board.c +++ b/board/BuR/brxre1/board.c @@ -132,7 +132,7 @@ void am33xx_spl_board_init(void) puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n"); } - pmicsetup(0); + pmicsetup(0, 0); } const struct dpll_params *get_dpll_ddr_params(void) diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index 5f2d0d055f..f743194c34 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -15,7 +15,7 @@ int load_lcdtiming(struct am335x_lcdpanel *panel); void br_summaryscreen(void); -void pmicsetup(u32 mpupll); +void pmicsetup(u32 mpupll, unsigned int bus); void enable_uart0_pin_mux(void); void enable_i2c_pin_mux(void); void enable_board_pin_mux(void); diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index f3eae5cbc1..a1f7c44abf 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -269,13 +269,14 @@ int ft_board_setup(void *blob, bd_t *bd) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; -void pmicsetup(u32 mpupll) +void pmicsetup(u32 mpupll, unsigned int bus) { int mpu_vdd; int usb_cur_lim; - if (i2c_probe(TPS65217_CHIP_PM)) { - puts("PMIC (0x24) not found! skip further initalization.\n"); + if (power_tps65217_init(bus)) { + printf("WARN: cannot setup PMIC 0x24 @ bus #%d, not found!.\n", + bus); return; } diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 083b5f7e5f..f2d8220126 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -71,7 +71,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y CONFIG_DM_MMC=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 1cfd5fc709..275727d11f 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -73,7 +73,6 @@ CONFIG_BLK=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y # CONFIG_MMC is not set diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 37373967df..668c4c22c2 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -76,7 +76,6 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_MISC=y CONFIG_DM_MMC=y From 47870afab92fca6e672c03d0dea802a55e200675 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Thu, 31 Jan 2019 16:06:23 +0100 Subject: [PATCH 27/40] initcall: Move to inline function The board_r init function was complaining that we are looping through an array, calling all our tiny init stubs sequentially via indirect function calls (which can't be speculated, so they are slow). The solution to that is pretty easy though. All we need to do is inline the function that loops through the functions and the compiler will automatically convert almost all indirect calls into direct inlined code. With this patch, the overall code size drops (by 40 bytes on riscv64) and boot time should become measurably faster for every target. Signed-off-by: Alexander Graf --- common/board_r.c | 5 +---- include/initcall.h | 35 ++++++++++++++++++++++++++++++++++- lib/Makefile | 1 - lib/initcall.c | 39 --------------------------------------- 4 files changed, 35 insertions(+), 45 deletions(-) delete mode 100644 lib/initcall.c diff --git a/common/board_r.c b/common/board_r.c index 5f3d27aa9f..472987d5d5 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -633,10 +633,7 @@ static int run_main_loop(void) } /* - * Over time we hope to remove these functions with code fragments and - * stub functions, and instead call the relevant function directly. - * - * We also hope to remove most of the driver-related init and do it if/when + * We hope to remove most of the driver-related init and do it if/when * the driver is later used. * * TODO: perhaps reset the watchdog in the initcall function after each call? diff --git a/include/initcall.h b/include/initcall.h index 01f3f2833f..3ac01aa2cd 100644 --- a/include/initcall.h +++ b/include/initcall.h @@ -8,6 +8,39 @@ typedef int (*init_fnc_t)(void); -int initcall_run_list(const init_fnc_t init_sequence[]); +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static inline int initcall_run_list(const init_fnc_t init_sequence[]) +{ + const init_fnc_t *init_fnc_ptr; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + unsigned long reloc_ofs = 0; + int ret; + + if (gd->flags & GD_FLG_RELOC) + reloc_ofs = gd->reloc_off; +#ifdef CONFIG_EFI_APP + reloc_ofs = (unsigned long)image_base; +#endif + debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs); + if (gd->flags & GD_FLG_RELOC) + debug(" (relocated to %p)\n", (char *)*init_fnc_ptr); + else + debug("\n"); + ret = (*init_fnc_ptr)(); + if (ret) { + printf("initcall sequence %p failed at call %p (err=%d)\n", + init_sequence, + (char *)*init_fnc_ptr - reloc_ofs, ret); + return -1; + } + } + return 0; +} #endif diff --git a/lib/Makefile b/lib/Makefile index 61d7ff0678..47829bfed5 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -35,7 +35,6 @@ obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o obj-$(CONFIG_GZIP_COMPRESSED) += gzip.o obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o obj-$(CONFIG_IMAGE_SPARSE) += image-sparse.o -obj-y += initcall.o obj-y += ldiv.o obj-$(CONFIG_MD5) += md5.o obj-y += net_utils.o diff --git a/lib/initcall.c b/lib/initcall.c deleted file mode 100644 index 8f1dac68e4..0000000000 --- a/lib/initcall.c +++ /dev/null @@ -1,39 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2013 The Chromium OS Authors. - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int initcall_run_list(const init_fnc_t init_sequence[]) -{ - const init_fnc_t *init_fnc_ptr; - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - unsigned long reloc_ofs = 0; - int ret; - - if (gd->flags & GD_FLG_RELOC) - reloc_ofs = gd->reloc_off; -#ifdef CONFIG_EFI_APP - reloc_ofs = (unsigned long)image_base; -#endif - debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs); - if (gd->flags & GD_FLG_RELOC) - debug(" (relocated to %p)\n", (char *)*init_fnc_ptr); - else - debug("\n"); - ret = (*init_fnc_ptr)(); - if (ret) { - printf("initcall sequence %p failed at call %p (err=%d)\n", - init_sequence, - (char *)*init_fnc_ptr - reloc_ofs, ret); - return -1; - } - } - return 0; -} From ea1a7de532823820739db2fa2ca8d62214bf6ce8 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Thu, 31 Jan 2019 18:57:35 +0100 Subject: [PATCH 28/40] bcm63158: add initial support This add the initial support of the broadcom bcm63158 SoC family, only the cpu, dram and uart are supported. Signed-off-by: Philippe Reynes --- arch/arm/Kconfig | 6 +++ arch/arm/dts/bcm63158.dtsi | 85 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 arch/arm/dts/bcm63158.dtsi diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0edb10003..4316de0401 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -528,6 +528,12 @@ config ARCH_BCM283X imply CMD_DM imply FAT_WRITE +config ARCH_BCM63158 + bool "Broadcom BCM63158 family" + select DM + select OF_CONTROL + imply CMD_DM + config ARCH_BCM6858 bool "Broadcom BCM6858 family" select DM diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi new file mode 100644 index 0000000000..be68205dc6 --- /dev/null +++ b/arch/arm/dts/bcm63158.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Philippe Reynes + */ + +#include "skeleton64.dtsi" + +/ { + compatible = "brcm,bcm63158"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&l2>; + u-boot,dm-pre-reloc; + }; + + l2: l2-cache0 { + compatible = "cache"; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + u-boot,dm-pre-reloc; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0xbebc200>; + u-boot,dm-pre-reloc; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + + uart0: serial@ff812000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xff812000 0x0 0x1000>; + clock = <50000000>; + + status = "disabled"; + }; + }; +}; From be2fc084d92fcb8092f6e925604072ca949f192f Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Thu, 31 Jan 2019 18:57:36 +0100 Subject: [PATCH 29/40] bcm963158: add initial support This add the initial support of the broadcom reference board bcm963158 with a bcm63158 SoC. This board has 1 GB of ram, 512 MB of flash (nand), 2 usb port, 1 uart, 4 ethernet ports (LAN), 1 ethernet port (WAN). Signed-off-by: Philippe Reynes --- arch/arm/Kconfig | 1 + arch/arm/dts/bcm963158.dts | 31 ++++++++++++++ board/broadcom/bcm963158/Kconfig | 17 ++++++++ board/broadcom/bcm963158/MAINTAINERS | 6 +++ board/broadcom/bcm963158/Makefile | 3 ++ board/broadcom/bcm963158/bcm963158.c | 61 ++++++++++++++++++++++++++++ configs/bcm963158_ram_defconfig | 40 ++++++++++++++++++ include/configs/broadcom_bcm963158.h | 37 +++++++++++++++++ 8 files changed, 196 insertions(+) create mode 100644 arch/arm/dts/bcm963158.dts create mode 100644 board/broadcom/bcm963158/Kconfig create mode 100644 board/broadcom/bcm963158/MAINTAINERS create mode 100644 board/broadcom/bcm963158/Makefile create mode 100644 board/broadcom/bcm963158/bcm963158.c create mode 100644 configs/bcm963158_ram_defconfig create mode 100644 include/configs/broadcom_bcm963158.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4316de0401..455f06cfee 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1532,6 +1532,7 @@ source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/broadcom/bcm23550_w1d/Kconfig" source "board/broadcom/bcm28155_ap/Kconfig" +source "board/broadcom/bcm963158/Kconfig" source "board/broadcom/bcm968580xref/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts new file mode 100644 index 0000000000..dc5afb5a24 --- /dev/null +++ b/arch/arm/dts/bcm963158.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Philippe Reynes + */ + +/dts-v1/; + +#include "bcm63158.dtsi" + +/ { + model = "Broadcom bcm963158"; + compatible = "broadcom,bcm963158", "brcm,bcm63158"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/board/broadcom/bcm963158/Kconfig b/board/broadcom/bcm963158/Kconfig new file mode 100644 index 0000000000..41b6adbb80 --- /dev/null +++ b/board/broadcom/bcm963158/Kconfig @@ -0,0 +1,17 @@ +if ARCH_BCM63158 + +config SYS_VENDOR + default "broadcom" + +config SYS_BOARD + default "bcm963158" + +config SYS_CONFIG_NAME + default "broadcom_bcm963158" + +endif + +config TARGET_BCM963158 + bool "Support Broadcom bcm963158" + depends on ARCH_BCM63158 + select ARM64 diff --git a/board/broadcom/bcm963158/MAINTAINERS b/board/broadcom/bcm963158/MAINTAINERS new file mode 100644 index 0000000000..d28d971f9d --- /dev/null +++ b/board/broadcom/bcm963158/MAINTAINERS @@ -0,0 +1,6 @@ +BROADCOM BCM963158 +M: Philippe Reynes +S: Maintained +F: board/broadcom/bcm963158/ +F: include/configs/broadcom_bcm963158.h +F: configs/bcm963158_ram_defconfig diff --git a/board/broadcom/bcm963158/Makefile b/board/broadcom/bcm963158/Makefile new file mode 100644 index 0000000000..0a902c9cf6 --- /dev/null +++ b/board/broadcom/bcm963158/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += bcm963158.o diff --git a/board/broadcom/bcm963158/bcm963158.c b/board/broadcom/bcm963158/bcm963158.c new file mode 100644 index 0000000000..db82cd570d --- /dev/null +++ b/board/broadcom/bcm963158/bcm963158.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Philippe Reynes + */ + +#include +#include +#include + +#ifdef CONFIG_ARM64 +#include + +static struct mm_region broadcom_bcm963158_mem_map[] = { + { + /* RAM */ + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 8UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* SoC */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0xff80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = broadcom_bcm963158_mem_map; +#endif + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_mem_size_base() != 0) + printf("fdtdec_setup_mem_size_base() has failed\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int print_cpuinfo(void) +{ + return 0; +} diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig new file mode 100644 index 0000000000..6e3b688f3e --- /dev/null +++ b/configs/bcm963158_ram_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARM=y +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_BCM63158=y +CONFIG_SYS_TEXT_BASE=0x10000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_TARGET_BCM963158=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y +CONFIG_FIT_VERBOSE=y +CONFIG_IMAGE_FORMAT_LEGACY=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTEFI_SELFTEST=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_CACHE=y +CONFIG_DOS_PARTITION=y +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_DEFAULT_DEVICE_TREE="bcm963158" +# CONFIG_NET is not set +CONFIG_BLK=y +CONFIG_CLK=y +# CONFIG_MMC is not set +CONFIG_SPECIFY_CONSOLE_INDEX=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_CONS_INDEX=0 +CONFIG_DM_SERIAL=y +CONFIG_SERIAL_SEARCH_ALL=y +CONFIG_PL01X_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_REGEX=y +# CONFIG_GENERATE_SMBIOS_TABLE is not set diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h new file mode 100644 index 0000000000..5834e1e2a2 --- /dev/null +++ b/include/configs/broadcom_bcm963158.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Philippe Reynes + */ + +#include + +/* + * common + */ + +/* UART */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ + 230400, 500000, 1500000 } +/* Memory usage */ +#define CONFIG_SYS_MAXARGS 24 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) + +/* + * 63158 + */ + +/* RAM */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 + +/* U-Boot */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * bcm963158 + */ + +#define CONFIG_ENV_SIZE (8 * 1024) From dcae39e55f1e6987b4bd4732c17350a1f10eaa09 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Thu, 31 Jan 2019 18:57:37 +0100 Subject: [PATCH 30/40] watchdog: bcm6345: allow to use this driver on arm bcm63158 This IP is also used on some arm SoC, so we allow to use it on arm bcm63158 too. Signed-off-by: Philippe Reynes --- drivers/watchdog/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 9456abd16b..115fc4551f 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -88,7 +88,7 @@ config WDT_ASPEED config WDT_BCM6345 bool "BCM6345 watchdog timer support" - depends on WDT && (ARCH_BMIPS || ARCH_BCM6858) + depends on WDT && (ARCH_BMIPS || ARCH_BCM6858 || ARCH_BCM63158) help Select this to enable watchdog timer for BCM6345 SoCs. The watchdog timer is stopped when initialized. From 2f4a686f217756d99556fef1e7756946d7566deb Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Thu, 31 Jan 2019 18:57:38 +0100 Subject: [PATCH 31/40] dt: bcm63158: add watchdog This commit add watchdog and sysreset watchdog in the bcm63158 device tree. Signed-off-by: Philippe Reynes --- arch/arm/dts/bcm63158.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi index be68205dc6..6a3fbc9093 100644 --- a/arch/arm/dts/bcm63158.dtsi +++ b/arch/arm/dts/bcm63158.dtsi @@ -81,5 +81,22 @@ status = "disabled"; }; + + wdt1: watchdog@ff800480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff800480 0x0 0x14>; + clocks = <&periph_osc>; + }; + + wdt2: watchdog@ff8004c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x0 0xff8004c0 0x0 0x14>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; }; }; From a765adc08f624dc229a83ac0c81f61af2d33246a Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Thu, 31 Jan 2019 18:57:39 +0100 Subject: [PATCH 32/40] bcm963158: enable watchdog and reboot with watchdog Enable watchdog and reboot with watchdog in the configuration. Signed-off-by: Philippe Reynes --- configs/bcm963158_ram_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig index 6e3b688f3e..9083f1dc9f 100644 --- a/configs/bcm963158_ram_defconfig +++ b/configs/bcm963158_ram_defconfig @@ -36,5 +36,7 @@ CONFIG_DM_SERIAL=y CONFIG_SERIAL_SEARCH_ALL=y CONFIG_PL01X_SERIAL=y CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_WDT_BCM6345=y CONFIG_REGEX=y # CONFIG_GENERATE_SMBIOS_TABLE is not set From f3885649657b4dfb669ae4505a0516c3affb8694 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 1 Feb 2019 16:01:07 +0100 Subject: [PATCH 33/40] dm: device: fail uclass_find_first_device() if list_empty While uclass_find_device() fails with -ENODEV in case of list_empty strangely uclass_find_first_device() returns 0. Fix uclass_find_first_device() to also fail with -ENODEV instead. Signed-off-by: Marcel Ziswiler Reviewed-by: Simon Glass --- drivers/core/uclass.c | 2 +- test/dm/core.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index a622f07941..fc3157de39 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -225,7 +225,7 @@ int uclass_find_first_device(enum uclass_id id, struct udevice **devp) if (ret) return ret; if (list_empty(&uc->dev_head)) - return 0; + return -ENODEV; *devp = list_first_entry(&uc->dev_head, struct udevice, uclass_node); diff --git a/test/dm/core.c b/test/dm/core.c index 260f6494a2..edd55b05d6 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -749,6 +749,10 @@ static int dm_test_uclass_devices_find(struct unit_test_state *uts) ut_assert(dev); } + ret = uclass_find_first_device(UCLASS_TEST_DUMMY, &dev); + ut_assert(ret == -ENODEV); + ut_assert(!dev); + return 0; } DM_TEST(dm_test_uclass_devices_find, DM_TESTF_SCAN_PDATA); From b3860bfe779f71708f380392ef195e137981d7ad Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 1 Feb 2019 16:01:08 +0100 Subject: [PATCH 34/40] cmd: sata: add null pointer check for dev Calling sata_scan() with a null pointer probably won't make much sense. Signed-off-by: Marcel Ziswiler Reviewed-by: Simon Glass --- cmd/sata.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cmd/sata.c b/cmd/sata.c index 6d62ba8f74..a73cc54bd3 100644 --- a/cmd/sata.c +++ b/cmd/sata.c @@ -60,6 +60,10 @@ int sata_probe(int devnum) printf("Cannot probe SATA device %d (err=%d)\n", devnum, rc); return CMD_RET_FAILURE; } + if (!dev) { + printf("No SATA device found!\n"); + return CMD_RET_FAILURE; + } rc = sata_scan(dev); if (rc) { printf("Cannot scan SATA device %d (err=%d)\n", devnum, rc); From e8cc366ca7c9f1b07f706772e13be6b84ca5521a Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 1 Feb 2019 15:04:56 -0600 Subject: [PATCH 35/40] configs: am65x_evm_r5: Enable GPT support The second loader stages may be stored on GPT partitions, enable support for this here. Signed-off-by: Andrew F. Davis Reviewed-by: Tom Rini Reviewed-by: Lokesh Vutla --- configs/am65x_evm_r5_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig index d2ec2dd7fe..49498b13b6 100644 --- a/configs/am65x_evm_r5_defconfig +++ b/configs/am65x_evm_r5_defconfig @@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_REMOTEPROC=y # CONFIG_CMD_SETEXPR is not set From 64176a8f5c24037b3b5b1a997f19304dff65bc97 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 1 Feb 2019 15:04:57 -0600 Subject: [PATCH 36/40] am65x_evm: Allow bootm to load larger kernels Bootm will fail to load kernels over 8MB, this is not enough for our 64bit kernel images. Increase this to 64MB. Signed-off-by: Andrew F. Davis Reviewed-by: Tom Rini Reviewed-by: Lokesh Vutla --- include/configs/am65x_evm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 31749c6d06..9ce5b6e824 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -37,6 +37,8 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4) +#define CONFIG_SYS_BOOTM_LEN SZ_64M + /* U-Boot general configuration */ #define EXTRA_ENV_AM65X_BOARD_SETTINGS \ "findfdt=" \ From 45b7f5b408181c7c5c9bbb01d258f9fa2a8825e5 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 1 Feb 2019 15:04:58 -0600 Subject: [PATCH 37/40] armv7R: K3: am654: Fix order of debug elements in x509 template The first element in the debug section is expected to be debugUID. ROM will not parse this correctly when out of order, fix this here. Signed-off-by: Andrew F. Davis Reviewed-by: Tom Rini Reviewed-by: Lokesh Vutla --- tools/k3_x509template.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/k3_x509template.txt b/tools/k3_x509template.txt index bd3a9ab056..f176ff3ad2 100644 --- a/tools/k3_x509template.txt +++ b/tools/k3_x509template.txt @@ -42,7 +42,7 @@ # salt = FORMAT:HEX,OCT:TEST_IMAGE_KEY_DERIVE_SALT [ debug ] + debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000 debugType = INTEGER:4 coreDbgEn = INTEGER:0 coreDbgSecEn = INTEGER:0 - debugUID = FORMAT:HEX,OCT:0000000000000000000000000000000000000000000000000000000000000000 From 5f137b5a58e6adac488cd8e73ba3e605f8eeb4e9 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 4 Feb 2019 15:14:17 +0100 Subject: [PATCH 38/40] bcm968580: rename to bcm968580xref The name of the board is bcm968580xref, so rename the config to bcm968580xref too. Signed-off-by: Philippe Reynes --- board/broadcom/bcm968580xref/MAINTAINERS | 4 ++-- .../{bcm968580_ram_defconfig => bcm968580xref_ram_defconfig} | 0 2 files changed, 2 insertions(+), 2 deletions(-) rename configs/{bcm968580_ram_defconfig => bcm968580xref_ram_defconfig} (100%) diff --git a/board/broadcom/bcm968580xref/MAINTAINERS b/board/broadcom/bcm968580xref/MAINTAINERS index 1ecdfbc0bb..5ee0c4dd4e 100644 --- a/board/broadcom/bcm968580xref/MAINTAINERS +++ b/board/broadcom/bcm968580xref/MAINTAINERS @@ -1,6 +1,6 @@ -BROADCOM BCM968580XREF +BCM968580XREF BOARD M: Philippe Reynes S: Maintained F: board/broadcom/bcm968580xref/ F: include/configs/broadcom_bcm968580xref.h -F: configs/bcm968580_ram_defconfig +F: configs/bcm968580xref_ram_defconfig diff --git a/configs/bcm968580_ram_defconfig b/configs/bcm968580xref_ram_defconfig similarity index 100% rename from configs/bcm968580_ram_defconfig rename to configs/bcm968580xref_ram_defconfig From eefc01d5905c252c333d4632bf2b312fac5bcb83 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Mon, 4 Feb 2019 15:14:18 +0100 Subject: [PATCH 39/40] bcm968580xref: switch to CONFIG_OF_SEPARATE The option OF_EMBED is deprecated, so we switch to CONFIG_OF_SEPARATE Signed-off-by: Philippe Reynes --- configs/bcm968580xref_ram_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig index b23f960aaa..1f433a3d39 100644 --- a/configs/bcm968580xref_ram_defconfig +++ b/configs/bcm968580xref_ram_defconfig @@ -18,7 +18,6 @@ CONFIG_CMD_BOOTEFI_SELFTEST=y CONFIG_DOS_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y -CONFIG_OF_EMBED=y CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref" # CONFIG_NET is not set CONFIG_BLK=y From 4a1fa524e95a1c81674d8a368035b522fd4a99d6 Mon Sep 17 00:00:00 2001 From: Andreas Dannenberg Date: Mon, 4 Feb 2019 12:58:47 -0600 Subject: [PATCH 40/40] arm: mach-k3: common: Clean up ATF image startup function Perform some cosmetic cleanup of the ATF image startup function, namely fixing a spelling mistake, capitalization of a few words, spacing, as well aligning how errors are printed and as using panic() for cases that were using a combination of printf() + hang(). Signed-off-by: Andreas Dannenberg Reviewed-by: Lokesh Vutla --- arch/arm/mach-k3/common.c | 28 ++++++++++------------------ 1 file changed, 10 insertions(+), 18 deletions(-) diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index cc89d4a296..5909bbfa8f 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -19,33 +19,25 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) /* * It is assumed that remoteproc device 1 is the corresponding - * cortex A core which runs ATF. Make sure DT reflects the same. + * Cortex-A core which runs ATF. Make sure DT reflects the same. */ ret = rproc_dev_init(1); - if (ret) { - printf("%s: ATF failed to Initialize on rproc: ret= %d\n", - __func__, ret); - hang(); - } + if (ret) + panic("%s: ATF failed to initialize on rproc (%d)\n", __func__, + ret); ret = rproc_load(1, spl_image->entry_point, 0x200); - if (ret) { - printf("%s: ATF failed to load on rproc: ret= %d\n", - __func__, ret); - hang(); - } + if (ret) + panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret); - /* Add an extra newline to differentiate the ATF logs from SPL*/ + /* Add an extra newline to differentiate the ATF logs from SPL */ printf("Starting ATF on ARM64 core...\n\n"); ret = rproc_start(1); - if (ret) { - printf("%s: ATF failed to start on rproc: ret= %d\n", - __func__, ret); - hang(); - } + if (ret) + panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret); - debug("ATF started. Wait indefiniely\n"); + debug("ATF started. Waiting indefinitely...\n"); while (1) asm volatile("wfe"); }