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Merge commit 'wd/master'

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This commit is contained in:
Jon Loeliger
2008-01-03 09:46:55 -06:00
parent f743931f9b ce37422d00
commit 2c3536425d
426 changed files with 25584 additions and 6614 deletions
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4
include/405_mal.h
View File

@@ -92,7 +92,9 @@
#define MAL_ESR_PBEI 0x00000001
/* ^^ ^^ */
/* Mal IER */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define MAL_IER_PT 0x00000080
#define MAL_IER_PRE 0x00000040
#define MAL_IER_PWE 0x00000020

2
include/4xx_i2c.h
View File

@@ -43,7 +43,7 @@
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS)
#elif defined(CONFIG_440)
#elif defined(CONFIG_440) || defined(CONFIG_405EX)
/* all remaining 440 variants */
#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS)
#else

26
include/asm-arm/io.h
View File

@@ -33,6 +33,32 @@ static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
/*
* Generic virtual read/write. Note that we don't support half-word
* read/writes. We define __arch_*[bl] here, and leave __arch_*w

34
include/asm-avr32/arch-at32ap700x/chip-features.h Normal file
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@@ -0,0 +1,34 @@
/*
* Copyright (C) 2007 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_AVR32_ARCH_CHIP_FEATURES_H__
#define __ASM_AVR32_ARCH_CHIP_FEATURES_H__
/* Currently, all the AP700x chips have these */
#define AT32AP700x_CHIP_HAS_USART
#define AT32AP700x_CHIP_HAS_MMCI
/* Only AP7000 has ethernet interface */
#ifdef CONFIG_AT32AP7000
#define AT32AP700x_CHIP_HAS_MACB
#endif
#endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */

8
include/asm-avr32/arch-at32ap7000/clk.h → include/asm-avr32/arch-at32ap700x/clk.h
View File

@@ -22,6 +22,8 @@
#ifndef __ASM_AVR32_ARCH_CLK_H__
#define __ASM_AVR32_ARCH_CLK_H__
#include <asm/arch/chip-features.h>
#ifdef CONFIG_PLL
#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
#else
@@ -50,10 +52,13 @@ static inline unsigned long get_sdram_clk_rate(void)
{
return get_hsb_clk_rate();
}
#ifdef AT32AP700x_CHIP_HAS_USART
static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
{
return get_pba_clk_rate();
}
#endif
#ifdef AT32AP700x_CHIP_HAS_USART
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
return get_pbb_clk_rate();
@@ -62,9 +67,12 @@ static inline unsigned long get_macb_hclk_rate(unsigned int dev_id)
{
return get_hsb_clk_rate();
}
#endif
#ifdef AT32AP700x_CHIP_HAS_MMCI
static inline unsigned long get_mci_clk_rate(void)
{
return get_pbb_clk_rate();
}
#endif
#endif /* __ASM_AVR32_ARCH_CLK_H__ */

8
include/asm-avr32/arch-at32ap7000/gpio.h → include/asm-avr32/arch-at32ap700x/gpio.h
View File

@@ -22,6 +22,7 @@
#ifndef __ASM_AVR32_ARCH_GPIO_H__
#define __ASM_AVR32_ARCH_GPIO_H__
#include <asm/arch/chip-features.h>
#include <asm/arch/memory-map.h>
#define NR_GPIO_CONTROLLERS 5
@@ -201,12 +202,19 @@ void gpio_select_periph_A(unsigned int pin, int use_pullup);
void gpio_select_periph_B(unsigned int pin, int use_pullup);
void gpio_enable_ebi(void);
#ifdef AT32AP700x_CHIP_HAS_USART
void gpio_enable_usart0(void);
void gpio_enable_usart1(void);
void gpio_enable_usart2(void);
void gpio_enable_usart3(void);
#endif
#ifdef AT32AP700x_CHIP_HAS_MACB
void gpio_enable_macb0(void);
void gpio_enable_macb1(void);
#endif
#ifdef AT32AP700x_CHIP_HAS_MMCI
void gpio_enable_mmci(void);
#endif
#endif /* __ASM_AVR32_ARCH_GPIO_H__ */

0
include/asm-avr32/arch-at32ap7000/hmatrix2.h → include/asm-avr32/arch-at32ap700x/hmatrix2.h
View File

0
include/asm-avr32/arch-at32ap7000/memory-map.h → include/asm-avr32/arch-at32ap700x/memory-map.h
View File

0
include/asm-avr32/arch-at32ap7000/mmc.h → include/asm-avr32/arch-at32ap700x/mmc.h
View File

32
include/asm-avr32/io.h
View File

@@ -93,4 +93,36 @@ static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*
* This implementation works for memory below 512MiB (flash, etc.) as
* well as above 3.5GiB (internal peripherals.)
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (1 << 7)
#define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9))
#define MAP_WRTHROUGH (MAP_WRBACK | (1 << 0))
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
if (flags == MAP_WRBACK)
return (void *)P1SEGADDR(paddr);
else
return (void *)P2SEGADDR(paddr);
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long len)
{
}
#endif /* __ASM_AVR32_IO_H */

26
include/asm-blackfin/io.h
View File

@@ -40,6 +40,32 @@ static inline void sync(void)
__builtin_bfin_ssync();
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
/*
* These are for ISA/PCI shared memory _only_ and should never be used
* on any other type of memory, including Zorro memory. They are meant to

26
include/asm-i386/io.h
View File

@@ -205,4 +205,30 @@ static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
#endif

41
include/asm-m68k/io.h
View File

@@ -28,6 +28,20 @@
#include <asm/byteorder.h>
/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
* two accesses to memory, which may be undesirable for some devices.
*/
#define __raw_readb(addr) \
({ u8 __v = (*(volatile u8 *) (addr)); __v; })
#define __raw_readw(addr) \
({ u16 __v = (*(volatile u16 *) (addr)); __v; })
#define __raw_readl(addr) \
({ u32 __v = (*(volatile u32 *) (addr)); __v; })
#define __raw_writeb(addr,b) (void)((*(volatile u8 *) (addr)) = (b))
#define __raw_writew(addr,w) (void)((*(volatile u16 *) (addr)) = (w))
#define __raw_writel(addr,l) (void)((*(volatile u32 *) (addr)) = (l))
#define readb(addr) in_8((volatile u8 *)(addr))
#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
#if !defined(__BIG_ENDIAN)
@@ -218,4 +232,31 @@ static inline void sync(void)
* compatibility (CFI driver)
*/
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
#endif /* __ASM_M68K_IO_H__ */

26
include/asm-microblaze/io.h
View File

@@ -129,4 +129,30 @@ static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
#endif /* __MICROBLAZE_IO_H__ */

26
include/asm-mips/io.h
View File

@@ -465,4 +465,30 @@ static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
#endif /* _ASM_IO_H */

34
include/asm-nios/io.h
View File

@@ -23,6 +23,14 @@
#ifndef __ASM_NIOS_IO_H_
#define __ASM_NIOS_IO_H_
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
#define readb(addr)\
({unsigned char val;\
asm volatile( " pfxio 0 \n"\
@@ -101,4 +109,30 @@ static inline void sync(void)
{
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
#endif /* __ASM_NIOS_IO_H_ */

34
include/asm-nios2/io.h
View File

@@ -29,10 +29,44 @@ static inline void sync(void)
__asm__ __volatile__ ("sync" : : : "memory");
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
extern unsigned char inb (unsigned char *port);
extern unsigned short inw (unsigned short *port);
extern unsigned inl (unsigned port);
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
#define __raw_readb(a) (*(volatile unsigned char *)(a))
#define __raw_readw(a) (*(volatile unsigned short *)(a))
#define __raw_readl(a) (*(volatile unsigned int *)(a))
#define readb(addr)\
({unsigned char val;\
asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})

0
include/405gp_pci.h → include/asm-ppc/4xx_pci.h
View File

336
include/asm-ppc/4xx_pcie.h Normal file
View File

@@ -0,0 +1,336 @@
/*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
* Roland Dreier <rolandd@cisco.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <ppc4xx.h>
#ifndef __4XX_PCIE_H
#define __4XX_PCIE_H
#define DCRN_SDR0_CFGADDR 0x00e
#define DCRN_SDR0_CFGDATA 0x00f
#if defined(CONFIG_440SPE)
#define CFG_PCIE_NR_PORTS 3
#define CFG_PCIE_ADDR_HIGH 0x0000000d
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
#define DCRN_PCIE2_BASE 0x140
#define PCIE0_SDR 0x300
#define PCIE1_SDR 0x340
#define PCIE2_SDR 0x370
#endif
#if defined(CONFIG_405EX)
#define CFG_PCIE_NR_PORTS 2
#define CFG_PCIE_ADDR_HIGH 0x00000000
#define DCRN_PCIE0_BASE 0x040
#define DCRN_PCIE1_BASE 0x060
#define PCIE0_SDR 0x400
#define PCIE1_SDR 0x440
#endif
#define PCIE0 DCRN_PCIE0_BASE
#define PCIE1 DCRN_PCIE1_BASE
#define PCIE2 DCRN_PCIE2_BASE
#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
#define DCRN_PEGPL_CFG(base) (base + 0x16)
/*
* System DCRs (SDRs)
*/
#define PESDR0_PLLLCT1 0x03a0
#define PESDR0_PLLLCT2 0x03a1
#define PESDR0_PLLLCT3 0x03a2
/* common regs, at least for 405EX and 440SPe */
#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02)
#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03)
#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04)
#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05)
#if defined(CONFIG_440SPE)
#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06)
#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07)
#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08)
#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09)
#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a)
#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b)
#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c)
#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d)
#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e)
#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f)
#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10)
#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11)
#define PESDR0_UTLSET1 0x0300
#define PESDR0_UTLSET2 0x0301
#define PESDR0_DLPSET 0x0302
#define PESDR0_LOOP 0x0303
#define PESDR0_RCSSET 0x0304
#define PESDR0_RCSSTS 0x0305
#define PESDR0_HSSL0SET1 0x0306
#define PESDR0_HSSL0SET2 0x0307
#define PESDR0_HSSL0STS 0x0308
#define PESDR0_HSSL1SET1 0x0309
#define PESDR0_HSSL1SET2 0x030a
#define PESDR0_HSSL1STS 0x030b
#define PESDR0_HSSL2SET1 0x030c
#define PESDR0_HSSL2SET2 0x030d
#define PESDR0_HSSL2STS 0x030e
#define PESDR0_HSSL3SET1 0x030f
#define PESDR0_HSSL3SET2 0x0310
#define PESDR0_HSSL3STS 0x0311
#define PESDR0_HSSL4SET1 0x0312
#define PESDR0_HSSL4SET2 0x0313
#define PESDR0_HSSL4STS 0x0314
#define PESDR0_HSSL5SET1 0x0315
#define PESDR0_HSSL5SET2 0x0316
#define PESDR0_HSSL5STS 0x0317
#define PESDR0_HSSL6SET1 0x0318
#define PESDR0_HSSL6SET2 0x0319
#define PESDR0_HSSL6STS 0x031a
#define PESDR0_HSSL7SET1 0x031b
#define PESDR0_HSSL7SET2 0x031c
#define PESDR0_HSSL7STS 0x031d
#define PESDR0_HSSCTLSET 0x031e
#define PESDR0_LANE_ABCD 0x031f
#define PESDR0_LANE_EFGH 0x0320
#define PESDR1_UTLSET1 0x0340
#define PESDR1_UTLSET2 0x0341
#define PESDR1_DLPSET 0x0342
#define PESDR1_LOOP 0x0343
#define PESDR1_RCSSET 0x0344
#define PESDR1_RCSSTS 0x0345
#define PESDR1_HSSL0SET1 0x0346
#define PESDR1_HSSL0SET2 0x0347
#define PESDR1_HSSL0STS 0x0348
#define PESDR1_HSSL1SET1 0x0349
#define PESDR1_HSSL1SET2 0x034a
#define PESDR1_HSSL1STS 0x034b
#define PESDR1_HSSL2SET1 0x034c
#define PESDR1_HSSL2SET2 0x034d
#define PESDR1_HSSL2STS 0x034e
#define PESDR1_HSSL3SET1 0x034f
#define PESDR1_HSSL3SET2 0x0350
#define PESDR1_HSSL3STS 0x0351
#define PESDR1_HSSCTLSET 0x0352
#define PESDR1_LANE_ABCD 0x0353
#define PESDR2_UTLSET1 0x0370
#define PESDR2_UTLSET2 0x0371
#define PESDR2_DLPSET 0x0372
#define PESDR2_LOOP 0x0373
#define PESDR2_RCSSET 0x0374
#define PESDR2_RCSSTS 0x0375
#define PESDR2_HSSL0SET1 0x0376
#define PESDR2_HSSL0SET2 0x0377
#define PESDR2_HSSL0STS 0x0378
#define PESDR2_HSSL1SET1 0x0379
#define PESDR2_HSSL1SET2 0x037a
#define PESDR2_HSSL1STS 0x037b
#define PESDR2_HSSL2SET1 0x037c
#define PESDR2_HSSL2SET2 0x037d
#define PESDR2_HSSL2STS 0x037e
#define PESDR2_HSSL3SET1 0x037f
#define PESDR2_HSSL3SET2 0x0380
#define PESDR2_HSSL3STS 0x0381
#define PESDR2_HSSCTLSET 0x0382
#define PESDR2_LANE_ABCD 0x0383
#elif defined(CONFIG_405EX)
#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06)
#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07)
#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08)
#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b)
#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c)
#define PESDR0_UTLSET1 0x0400
#define PESDR0_UTLSET2 0x0401
#define PESDR0_DLPSET 0x0402
#define PESDR0_LOOP 0x0403
#define PESDR0_RCSSET 0x0404
#define PESDR0_RCSSTS 0x0405
#define PESDR0_PHYSET1 0x0406
#define PESDR0_PHYSET2 0x0407
#define PESDR0_BIST 0x0408
#define PESDR0_LPB 0x040B
#define PESDR0_PHYSTA 0x040C
#define PESDR1_UTLSET1 0x0440
#define PESDR1_UTLSET2 0x0441
#define PESDR1_DLPSET 0x0442
#define PESDR1_LOOP 0x0443
#define PESDR1_RCSSET 0x0444
#define PESDR1_RCSSTS 0x0445
#define PESDR1_PHYSET1 0x0446
#define PESDR1_PHYSET2 0x0447
#define PESDR1_BIST 0x0448
#define PESDR1_LPB 0x044B
#define PESDR1_PHYSTA 0x044C
#endif
/*
* UTL register offsets
*/
#define PEUTL_PBCTL 0x00
#define PEUTL_PBBSZ 0x20
#define PEUTL_OPDBSZ 0x68
#define PEUTL_IPHBSZ 0x70
#define PEUTL_IPDBSZ 0x78
#define PEUTL_OUTTR 0x90
#define PEUTL_INTR 0x98
#define PEUTL_PCTL 0xa0
#define PEUTL_RCSTA 0xb0
#define PEUTL_RCIRQEN 0xb8
/*
* Config space register offsets
*/
#define PECFG_BAR0LMPA 0x210
#define PECFG_BAR0HMPA 0x214
#define PECFG_BAR1MPA 0x218
#define PECFG_BAR2LMPA 0x220
#define PECFG_BAR2HMPA 0x224
#define PECFG_PIMEN 0x33c
#define PECFG_PIM0LAL 0x340
#define PECFG_PIM0LAH 0x344
#define PECFG_PIM1LAL 0x348
#define PECFG_PIM1LAH 0x34c
#define PECFG_PIM01SAL 0x350
#define PECFG_PIM01SAH 0x354
#define PECFG_POM0LAL 0x380
#define PECFG_POM0LAH 0x384
#define SDR_READ(offset) ({\
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mfdcr(DCRN_SDR0_CFGDATA);})
#define SDR_WRITE(offset, data) ({\
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mtdcr(DCRN_SDR0_CFGDATA,data);})
#define GPL_DMER_MASK_DISA 0x02000000
#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
/*
* Prototypes
*/
int ppc4xx_init_pcie(void);
int ppc4xx_init_pcie_rootport(int port);
int ppc4xx_init_pcie_endport(int port);
void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
int pcie_hose_scan(struct pci_controller *hose, int bus);
/*
* Function to determine root port or endport from env variable.
*/
static inline int is_end_point(int port)
{
char s[10], *tk;
char *pcie_mode = getenv("pcie_mode");
if (pcie_mode == NULL)
return 0;
strcpy(s, pcie_mode);
tk = strtok(s, ":");
switch (port) {
case 0:
if (tk != NULL) {
if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
return 1;
else
return 0;
}
else
return 0;
case 1:
tk = strtok(NULL, ":");
if (tk != NULL) {
if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
return 1;
else
return 0;
}
else
return 0;
case 2:
tk = strtok(NULL, ":");
if (tk != NULL)
tk = strtok(NULL, ":");
if (tk != NULL) {
if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
return 1;
else
return 0;
}
else
return 0;
}
return 0;
}
static inline void mdelay(int n)
{
u32 ms = n;
while (ms--)
udelay(1000);
}
static inline u32 sdr_base(int port)
{
switch (port) {
default: /* to satisfy compiler */
case 0:
return PCIE0_SDR;
case 1:
return PCIE1_SDR;
#if CFG_PCIE_NR_PORTS > 2
case 2:
return PCIE2_SDR;
#endif
}
}
#endif /* __4XX_PCIE_H */

21
include/asm-ppc/cache.h
View File

@@ -8,15 +8,24 @@
#include <asm/processor.h>
/* bytes per L1 cache line */
#if !defined(CONFIG_8xx) || defined(CONFIG_8260)
#if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480))
#if defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_BYTES 128
#define L1_CACHE_SHIFT 7
#else
#define L1_CACHE_BYTES 32
#define L1_CACHE_SHIFT 5
#endif /* PPC64 */
#else
#define L1_CACHE_BYTES 16
#endif /* !8xx || 8260 */
#define L1_CACHE_SHIFT 4
#endif /* !(8xx || IOP480) */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
* For compatibility reasons support the CFG_CACHELINE_SIZE too
*/
#ifndef CFG_CACHELINE_SIZE
#define CFG_CACHELINE_SIZE L1_CACHE_BYTES
#endif
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8
@@ -35,6 +44,8 @@
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache(void);
extern void invalidate_dcache(void);
#ifdef CFG_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
#endif /* CFG_INIT_RAM_LOCK */

3
include/asm-ppc/global_data.h
View File

@@ -107,6 +107,9 @@ typedef struct global_data {
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif
#if defined(CONFIG_4xx)
u32 uart_clk;
#endif /* CONFIG_4xx */
#if defined(CFG_GT_6426x)
unsigned int mirror_hack[16];
#endif

35
include/asm-ppc/gpio.h
View File

@@ -21,6 +21,9 @@
* MA 02111-1307 USA
*/
#ifndef __ASM_PPC_GPIO_H
#define __ASM_PPC_GPIO_H
/* 4xx PPC's have 2 GPIO controllers */
#if defined(CONFIG_405EZ) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
@@ -30,6 +33,36 @@
#define GPIO_GROUP_MAX 1
#endif
/* Offsets */
#define GPIOx_OR 0x00 /* GPIO Output Register */
#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */
#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */
#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */
#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */
#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */
#define GPIOx_ODR 0x18 /* GPIO Open drain Register */
#define GPIOx_IR 0x1C /* GPIO Input Register */
#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */
#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */
#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */
#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */
#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */
#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */
#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */
#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */
#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */
#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */
#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */
#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */
#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */
#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */
#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */
#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */
#define GPIO0 0
#define GPIO1 1
#define GPIO_MAX 32
#define GPIO_ALT1_SEL 0x40000000
#define GPIO_ALT2_SEL 0x80000000
@@ -56,3 +89,5 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val);
int gpio_read_out_bit(int pin);
void gpio_set_chip_configuration(void);
#endif /* __ASM_PPC_GPIO_H */

45
include/asm-ppc/immap_85xx.h
View File

@@ -720,11 +720,10 @@ typedef struct ccsr_tsec {
} ccsr_tsec_t;
/*
* PIC Registers(0x2_6000-0x4_0000-0x8_0000)
* PIC Registers(0x4_0000-0x8_0000)
*/
typedef struct ccsr_pic {
char res0[106496]; /* 0x26000-0x40000 */
char res1[64];
char res1[64]; /* 0x40000 */
uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
char res2[12];
uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
@@ -1619,25 +1618,25 @@ typedef struct ccsr_gur {
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
typedef struct immap {
ccsr_local_ecm_t im_local_ecm;
ccsr_ddr_t im_ddr;
ccsr_i2c_t im_i2c;
ccsr_duart_t im_duart;
ccsr_lbc_t im_lbc;
ccsr_pcix_t im_pcix;
ccsr_pcix_t im_pcix2;
char reserved[90112];
ccsr_l2cache_t im_l2cache;
ccsr_dma_t im_dma;
ccsr_tsec_t im_tsec1;
ccsr_tsec_t im_tsec2;
ccsr_pic_t im_pic;
ccsr_cpm_t im_cpm;
ccsr_rio_t im_rio;
ccsr_gur_t im_gur;
} immap_t;
extern immap_t *immr;
#define CFG_MPC85xx_GUTS_OFFSET (0xE0000)
#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
#define CFG_MPC85xx_ECM_OFFSET (0x0000)
#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
#define CFG_MPC85xx_DDR_OFFSET (0x2000)
#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
#define CFG_MPC85xx_LBC_OFFSET (0x5000)
#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
#define CFG_MPC85xx_PCIX_OFFSET (0x8000)
#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
#define CFG_MPC85xx_PCIX2_OFFSET (0x9000)
#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
#define CFG_MPC85xx_L2_OFFSET (0x20000)
#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
#define CFG_MPC85xx_DMA_OFFSET (0x21000)
#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
#define CFG_MPC85xx_PIC_OFFSET (0x40000)
#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
#define CFG_MPC85xx_CPM_OFFSET (0x80000)
#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
#endif /*__IMMAP_85xx__*/

4
include/asm-ppc/immap_fsl_pci.h
View File

@@ -144,7 +144,9 @@ typedef struct ccsr_pci {
u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
char res23[456]; /* (- #x1000 #xe38) 456 */
char res23[200];
u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
char res24[252];
} ccsr_fsl_pci_t;
#endif /*__IMMAP_fsl_pci__*/

58
include/asm-ppc/io.h
View File

@@ -120,6 +120,37 @@ static inline void isync(void)
#define iobarrier_r() eieio()
#define iobarrier_w() eieio()
/*
* Non ordered and non-swapping "raw" accessors
*/
#define __iomem
#define PCI_FIX_ADDR(addr) (addr)
static inline unsigned char __raw_readb(const volatile void __iomem *addr)
{
return *(volatile unsigned char *)PCI_FIX_ADDR(addr);
}
static inline unsigned short __raw_readw(const volatile void __iomem *addr)
{
return *(volatile unsigned short *)PCI_FIX_ADDR(addr);
}
static inline unsigned int __raw_readl(const volatile void __iomem *addr)
{
return *(volatile unsigned int *)PCI_FIX_ADDR(addr);
}
static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
{
*(volatile unsigned char *)PCI_FIX_ADDR(addr) = v;
}
static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
{
*(volatile unsigned short *)PCI_FIX_ADDR(addr) = v;
}
static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
{
*(volatile unsigned int *)PCI_FIX_ADDR(addr) = v;
}
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*
@@ -127,7 +158,6 @@ static inline void isync(void)
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
#define __iomem
extern inline int in_8(const volatile unsigned char __iomem *addr)
{
int ret;
@@ -208,4 +238,30 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val)
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
}
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
* properties specified by "flags".
*/
typedef unsigned long phys_addr_t;
#define MAP_NOCACHE (0)
#define MAP_WRCOMBINE (0)
#define MAP_WRBACK (0)
#define MAP_WRTHROUGH (0)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
return (void *)paddr;
}
/*
* Take down a mapping set up by map_physmem().
*/
static inline void unmap_physmem(void *vaddr, unsigned long flags)
{
}
#endif

40
include/asm-ppc/iopin_85xx.h
View File

@@ -23,121 +23,121 @@ typedef struct {
extern __inline__ void iopin_set_high (iopin_t * iopin)
{
volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_low (iopin_t * iopin)
{
volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_high (iopin_t * iopin)
{
volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_low (iopin_t * iopin)
{
volatile uint *datp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdata;
volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_out (iopin_t * iopin)
{
volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_in (iopin_t * iopin)
{
volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_out (iopin_t * iopin)
{
volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_in (iopin_t * iopin)
{
volatile uint *dirp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.pdira;
volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_odr (iopin_t * iopin)
{
volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_act (iopin_t * iopin)
{
volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_odr (iopin_t * iopin)
{
volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_act (iopin_t * iopin)
{
volatile uint *odrp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.podra;
volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_ded (iopin_t * iopin)
{
volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_gen (iopin_t * iopin)
{
volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_ded (iopin_t * iopin)
{
volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_gen (iopin_t * iopin)
{
volatile uint *parp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.ppara;
volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
{
volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
{
volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
{
volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
{
volatile uint *sorp = &((immap_t *) CFG_IMMR)->im_cpm.im_cpm_iop.psora;
volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}

5
include/asm-ppc/mmu.h
View File

@@ -413,7 +413,9 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_TRGT_IF_PCI1 0x00000000
#define LAWAR_TRGT_IF_PCIX 0x00000000
#define LAWAR_TRGT_IF_PCI2 0x00100000
#define LAWAR_TRGT_IF_PEX 0x00200000
#define LAWAR_TRGT_IF_PCIE1 0x00200000
#define LAWAR_TRGT_IF_PCIE2 0x00100000
#define LAWAR_TRGT_IF_PCIE3 0x00300000
#define LAWAR_TRGT_IF_LBC 0x00400000
#define LAWAR_TRGT_IF_CCSR 0x00800000
#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
@@ -648,6 +650,7 @@ unsigned long mftlb3(unsigned long index);
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
void remove_tlb(u32 vaddr, u32 size);
void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_440 */

9
include/asm-ppc/processor.h
View File

@@ -91,6 +91,11 @@
/* Special Purpose Registers (SPRNs)*/
/* PPC440 Architecture is BOOK-E */
#ifdef CONFIG_440
#define CONFIG_BOOKE
#endif
#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
@@ -765,6 +770,10 @@
#define PVR_405EP_RA 0x51210950
#define PVR_405GPR_RB 0x50910951
#define PVR_405EZ_RA 0x41511460
#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */
#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */
#define PVR_405EX1_RA 0x12911477 /* 405EX rev A with Security */
#define PVR_405EX2_RA 0x12911475 /* 405EX rev A without Security */
#define PVR_440GP_RB 0x40120440
#define PVR_440GP_RC 0x40120481
#define PVR_440EP_RA 0x42221850

1
include/asm-ppc/u-boot.h
View File

@@ -84,6 +84,7 @@ typedef struct bd_info {
defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || \
defined(CONFIG_440)
unsigned char bi_s_version[4]; /* Version of this structure */
unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */

151
include/asm-sh/bitops.h Normal file
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@@ -0,0 +1,151 @@
#ifndef __ASM_SH_BITOPS_H
#define __ASM_SH_BITOPS_H
#ifdef __KERNEL__
#include <asm/irqflags.h>
/* For __swab32 */
#include <asm/byteorder.h>
static inline void set_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a |= mask;
local_irq_restore(flags);
}
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
static inline void clear_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a &= ~mask;
local_irq_restore(flags);
}
static inline void change_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a ^= mask;
local_irq_restore(flags);
}
static inline int test_and_set_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a |= mask;
local_irq_restore(flags);
return retval;
}
static inline int test_and_clear_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a &= ~mask;
local_irq_restore(flags);
return retval;
}
static inline int test_and_change_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a ^= mask;
local_irq_restore(flags);
return retval;
}
static inline unsigned long ffz(unsigned long word)
{
unsigned long result;
__asm__("1:\n\t"
"shlr %1\n\t"
"bt/s 1b\n\t"
" add #1, %0"
: "=r" (result), "=r" (word)
: "0" (~0L), "1" (word)
: "t");
return result;
}
/**
* ffs - find first bit in word.
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static inline int ffs (int x)
{
int r = 1;
if (!x)
return 0;
if (!(x & 0xffff)) {
x >>= 16;
r += 16;
}
if (!(x & 0xff)) {
x >>= 8;
r += 8;
}
if (!(x & 0xf)) {
x >>= 4;
r += 4;
}
if (!(x & 3)) {
x >>= 2;
r += 2;
}
if (!(x & 1)) {
x >>= 1;
r += 1;
}
return r;
}
#endif /* __KERNEL__ */
#endif /* __ASM_SH_BITOPS_H */

30
include/asm-sh/byteorder.h Normal file
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@@ -0,0 +1,30 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_SH_BYTEORDER_H_
#define __ASM_SH_BYTEORDER_H_
#include <config.h>
#include <asm/types.h>
#ifdef __LITTLE_ENDIAN__
#include <linux/byteorder/little_endian.h>
#else
#include <linux/byteorder/big_endian.h>
#endif
#endif

41
include/asm-sh/cpu_sh4.h Normal file
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@@ -0,0 +1,41 @@
/*
* (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_CPU_SH4_H_
#define _ASM_CPU_SH4_H_
/* cache control */
#define CCR_CACHE_STOP 0x00000808
#define CCR_CACHE_ENABLE 0x00000101
#define CCR_CACHE_ICI 0x00000800
#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
#define CACHE_OC_WAY_SHIFT 14
#define CACHE_OC_NUM_ENTRIES 512
#define CACHE_OC_ENTRY_SHIFT 5
#if defined (CONFIG_CPU_SH7750)
#include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
#include <asm/cpu_sh7722.h>
#else
#error "Unknown SH4 variant"
#endif
#endif /* _ASM_CPU_SH4_H_ */

1337
include/asm-sh/cpu_sh7722.h Normal file
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File diff suppressed because it is too large Load Diff

196
include/asm-sh/cpu_sh7750.h Normal file
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@@ -0,0 +1,196 @@
/*
* (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* SH7750/SH7750S/SH7750R/SH7751/SH7751R
* Internal I/O register
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ASM_CPU_SH7750_H_
#define _ASM_CPU_SH7750_H_
#ifdef CONFIG_CPU_TYPE_R
#define CACHE_OC_NUM_WAYS 2
#define CCR_CACHE_INIT 0x8000090d /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */
#else
#define CACHE_OC_NUM_WAYS 1
#define CCR_CACHE_INIT 0x0000090b
#endif
/* OCN */
#define PTEH 0xFF000000
#define PTEL 0xFF000004
#define TTB 0xFF000008
#define TEA 0xFF00000C
#define MMUCR 0xFF000010
#define BASRA 0xFF000014
#define BASRB 0xFF000018
#define CCR 0xFF00001C
#define TRA 0xFF000020
#define EXPEVT 0xFF000024
#define INTEVT 0xFF000028
#define PTEA 0xFF000034
#define QACR0 0xFF000038
#define QACR1 0xFF00003C
/* UBC */
#define BARA 0xFF200000
#define BAMRA 0xFF200004
#define BBRA 0xFF200008
#define BARB 0xFF20000C
#define BAMRB 0xFF200010
#define BBRB 0xFF200014
#define BDRB 0xFF200018
#define BDMRB 0xFF20001C
#define BRCR 0xFF200020
/* BSC */
#define BCR1 0xFF800000
#define BCR2 0xFF800004
#define BCR3 0xFF800050
#define BCR4 0xFE0A00F0
#define WCR1 0xFF800008
#define WCR2 0xFF80000C
#define WCR3 0xFF800010
#define MCR 0xFF800014
#define PCR 0xFF800018
#define RTCSR 0xFF80001C
#define RTCNT 0xFF800020
#define RTCOR 0xFF800024
#define RFCR 0xFF800028
#define PCTRA 0xFF80002C
#define PDTRA 0xFF800030
#define PCTRB 0xFF800040
#define PDTRB 0xFF800044
#define GPIOIC 0xFF800048
/* DMAC */
#define SAR0 0xFFA00000
#define DAR0 0xFFA00004
#define DMATCR0 0xFFA00008
#define CHCR0 0xFFA0000C
#define SAR1 0xFFA00010
#define DAR1 0xFFA00014
#define DMATCR1 0xFFA00018
#define CHCR1 0xFFA0001C
#define SAR2 0xFFA00020
#define DAR2 0xFFA00024
#define DMATCR2 0xFFA00028
#define CHCR2 0xFFA0002C
#define SAR3 0xFFA00030
#define DAR3 0xFFA00034
#define DMATCR3 0xFFA00038
#define CHCR3 0xFFA0003C
#define DMAOR 0xFFA00040
#define SAR4 0xFFA00050
#define DAR4 0xFFA00054
#define DMATCR4 0xFFA00058
/* CPG */
#define FRQCR 0xFFC00000
#define STBCR 0xFFC00004
#define WTCNT 0xFFC00008
#define WTCSR 0xFFC0000C
#define STBCR2 0xFFC00010
/* RTC */
#define R64CNT 0xFFC80000
#define RSECCNT 0xFFC80004
#define RMINCNT 0xFFC80008
#define RHRCNT 0xFFC8000C
#define RWKCNT 0xFFC80010
#define RDAYCNT 0xFFC80014
#define RMONCNT 0xFFC80018
#define RYRCNT 0xFFC8001C
#define RSECAR 0xFFC80020
#define RMINAR 0xFFC80024
#define RHRAR 0xFFC80028
#define RWKAR 0xFFC8002C
#define RDAYAR 0xFFC80030
#define RMONAR 0xFFC80034
#define RCR1 0xFFC80038
#define RCR2 0xFFC8003C
#define RCR3 0xFFC80050
#define RYRAR 0xFFC80054
/* ICR */
#define ICR 0xFFD00000
#define IPRA 0xFFD00004
#define IPRB 0xFFD00008
#define IPRC 0xFFD0000C
#define IPRD 0xFFD00010
#define INTPRI 0xFE080000
#define INTREQ 0xFE080020
#define INTMSK 0xFE080040
#define INTMSKCL 0xFE080060
/* CPG */
#define CLKSTP 0xFE0A0000
#define CLKSTPCLR 0xFE0A0008
/* TMU */
#define TSTR2 0xFE100004
#define TCOR3 0xFE100008
#define TCNT3 0xFE10000C
#define TCR3 0xFE100010
#define TCOR4 0xFE100014
#define TCNT4 0xFE100018
#define TCR4 0xFE10001C
#define TOCR 0xFFD80000
#define TSTR0 0xFFD80004
#define TCOR0 0xFFD80008
#define TCNT0 0xFFD8000C
#define TCR0 0xFFD80010
#define TCOR1 0xFFD80014
#define TCNT1 0xFFD80018
#define TCR1 0xFFD8001C
#define TCOR2 0xFFD80020
#define TCNT2 0xFFD80024
#define TCR2 0xFFD80028
#define TCPR2 0xFFD8002C
#define TSTR TSTR0
/* SCI */
#define SCSMR1 0xFFE00000
#define SCBRR1 0xFFE00004
#define SCSCR1 0xFFE00008
#define SCTDR1 0xFFE0000C
#define SCSSR1 0xFFE00010
#define SCRDR1 0xFFE00014
#define SCSCMR1 0xFFE00018
#define SCSPTR1 0xFFE0001C
#define SCF0_BASE SCSMR1
/* SCIF */
#define SCSMR2 0xFFE80000
#define SCBRR2 0xFFE80004
#define SCSCR2 0xFFE80008
#define SCFTDR2 0xFFE8000C
#define SCFSR2 0xFFE80010
#define SCFRDR2 0xFFE80014
#define SCFCR2 0xFFE80018
#define SCFDR2 0xFFE8001C
#define SCSPTR2 0xFFE80020
#define SCLSR2 0xFFE80024
#define SCIF1_BASE SCSMR2
/* H-UDI */
#define SDIR 0xFFF00000
#define SDDR 0xFFF00008
#define SDINT 0xFFF00014
#endif /* _ASM_CPU_SH7750_H_ */

156
include/asm-sh/errno.h Normal file
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@@ -0,0 +1,156 @@
/*
* U-boot - errno.h Error number defines
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _BLACKFIN_ERRNO_H
#define _BLACKFIN_ERRNO_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Arg list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
#define EDEADLOCK EDEADLK
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
#endif

50
include/asm-sh/global_data.h Normal file
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@@ -0,0 +1,50 @@
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_SH_GLOBALDATA_H_
#define __ASM_SH_GLOBALDATA_H_
typedef struct global_data
{
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
unsigned long ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid */
void **jt; /* Standalone app jump table */
}gd_t;
#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
#define GD_FLG_SILENT 0x00004 /* Silent mode */
#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13")
#endif /* __ASM_SH_GLOBALDATA_H_ */

231
include/asm-sh/io.h Normal file
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@@ -0,0 +1,231 @@
/*
* linux/include/asm-sh/io.h
*
* Copyright (C) 1996-2000 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Modifications:
* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
* constant addresses and variable addresses.
* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
* specific IO header files.
* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
* 04-Apr-1999 PJB Added check_signature.
* 12-Dec-1999 RMK More cleanups
* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
*/
#ifndef __ASM_SH_IO_H
#define __ASM_SH_IO_H
#ifdef __KERNEL__
#include <linux/types.h>
#include <asm/byteorder.h>
/*
* Generic virtual read/write. Note that we don't support half-word
* read/writes. We define __arch_*[bl] here, and leave __arch_*w
* to the architecture specific code.
*/
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
extern void __raw_readsl(unsigned int addr, void *data, int longlen);
#define __raw_writeb(v,a) __arch_putb(v,a)
#define __raw_writew(v,a) __arch_putw(v,a)
#define __raw_writel(v,a) __arch_putl(v,a)
#define __raw_readb(a) __arch_getb(a)
#define __raw_readw(a) __arch_getw(a)
#define __raw_readl(a) __arch_getl(a)
/*
* The compiler seems to be incapable of optimising constants
* properly. Spell it out to the compiler in some cases.
* These are only valid for small values of "off" (< 1<<12)
*/
#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off)
#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off)
#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off)
#define __raw_base_readb(base,off) __arch_base_getb(base,off)
#define __raw_base_readw(base,off) __arch_base_getw(base,off)
#define __raw_base_readl(base,off) __arch_base_getl(base,off)
/*
* Now, pick up the machine-defined IO definitions
*/
#if 0 /* XXX###XXX */
#include <asm/arch/io.h>
#endif /* XXX###XXX */
/*
* IO port access primitives
* -------------------------
*
* The SH doesn't have special IO access instructions; all IO is memory
* mapped. Note that these are defined to perform little endian accesses
* only. Their primary purpose is to access PCI and ISA peripherals.
*
* The machine specific io.h include defines __io to translate an "IO"
* address to a memory address.
*
* Note that we prevent GCC re-ordering or caching values in expressions
* by introducing sequence points into the in*() definitions. Note that
* __raw_* do not guarantee this behaviour.
*
* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
*/
#define outb(v,p) __raw_writeb(v, p)
#define outw(v,p) __raw_writew(cpu_to_le16(v),p)
#define outl(v,p) __raw_writel(cpu_to_le32(v),p)
#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; })
#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; })
#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; })
#define outsb(p,d,l) __raw_writesb(p,d,l)
#define outsw(p,d,l) __raw_writesw(p,d,l)
#define outsl(p,d,l) __raw_writesl(p,d,l)
#define insb(p,d,l) __raw_readsb(p,d,l)
#define insw(p,d,l) __raw_readsw(p,d,l)
#define insl(p,d,l) __raw_readsl(p,d,l)
#define outb_p(val,port) outb((val),(port))
#define outw_p(val,port) outw((val),(port))
#define outl_p(val,port) outl((val),(port))
#define inb_p(port) inb((port))
#define inw_p(port) inw((port))
#define inl_p(port) inl((port))
#define outsb_p(port,from,len) outsb(port,from,len)
#define outsw_p(port,from,len) outsw(port,from,len)
#define outsl_p(port,from,len) outsl(port,from,len)
#define insb_p(port,to,len) insb(port,to,len)
#define insw_p(port,to,len) insw(port,to,len)
#define insl_p(port,to,len) insl(port,to,len)
/*
* ioremap and friends.
*
* ioremap takes a PCI memory address, as specified in
* linux/Documentation/IO-mapping.txt. If you want a
* physical address, use __ioremap instead.
*/
extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
extern void __iounmap(void *addr);
/*
* Generic ioremap support.
*
* Define:
* iomem_valid_addr(off,size)
* iomem_to_phys(off)
*/
#ifdef iomem_valid_addr
#define __arch_ioremap(off,sz,nocache) \
({ \
unsigned long _off = (off), _size = (sz); \
void *_ret = (void *)0; \
if (iomem_valid_addr(_off, _size)) \
_ret = __ioremap(iomem_to_phys(_off),_size,0); \
_ret; \
})
#define __arch_iounmap __iounmap
#endif
#define ioremap(off,sz) __arch_ioremap((off),(sz),0)
#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1)
#define iounmap(_addr) __arch_iounmap(_addr)
/*
* DMA-consistent mapping functions. These allocate/free a region of
* uncached, unwrite-buffered mapped memory space for use with DMA
* devices. This is the "generic" version. The PCI specific version
* is in pci.h
*/
extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
extern void consistent_sync(void *vaddr, size_t size, int rw);
/*
* String version of IO memory access ops:
*/
extern void _memcpy_fromio(void *, unsigned long, size_t);
extern void _memcpy_toio(unsigned long, const void *, size_t);
extern void _memset_io(unsigned long, int, size_t);
/*
* If this architecture has PCI memory IO, then define the read/write
* macros. These should only be used with the cookie passed from
* ioremap.
*/
#ifdef __mem_pci
#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
#define eth_io_copy_and_sum(s,c,l,b) \
eth_copy_and_sum((s),__mem_pci(c),(l),(b))
static inline int
check_signature(unsigned long io_addr, const unsigned char *signature,
int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
#elif !defined(readb)
#define readb(addr) __raw_readb(addr)
#define readw(addr) __raw_readw(addr)
#define readl(addr) __raw_readl(addr)
#define writeb(v,addr) __raw_writeb(v, addr)
#define writew(v,addr) __raw_writew(v, addr)
#define writel(v,addr) __raw_writel(v, addr)
#define check_signature(io,sig,len) (0)
#endif /* __mem_pci */
static inline void sync(void)
{
}
#endif /* __KERNEL__ */
#endif /* __ASM_SH_IO_H */

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#ifndef __ASM_SH_IRQFLAGS_H
#define __ASM_SH_IRQFLAGS_H
static inline void raw_local_irq_enable(void)
{
unsigned long __dummy0, __dummy1;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"and %1, %0\n\t"
#ifdef CONFIG_CPU_HAS_SR_RB
"stc r6_bank, %1\n\t"
"or %1, %0\n\t"
#endif
"ldc %0, sr\n\t"
: "=&r" (__dummy0), "=r" (__dummy1)
: "1" (~0x000000f0)
: "memory"
);
}
static inline void raw_local_irq_disable(void)
{
unsigned long flags;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"or #0xf0, %0\n\t"
"ldc %0, sr\n\t"
: "=&z" (flags)
: /* no inputs */
: "memory"
);
}
static inline void set_bl_bit(void)
{
unsigned long __dummy0, __dummy1;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"or %2, %0\n\t"
"and %3, %0\n\t"
"ldc %0, sr\n\t"
: "=&r" (__dummy0), "=r" (__dummy1)
: "r" (0x10000000), "r" (0xffffff0f)
: "memory"
);
}
static inline void clear_bl_bit(void)
{
unsigned long __dummy0, __dummy1;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"and %2, %0\n\t"
"ldc %0, sr\n\t"
: "=&r" (__dummy0), "=r" (__dummy1)
: "1" (~0x10000000)
: "memory"
);
}
static inline unsigned long __raw_local_save_flags(void)
{
unsigned long flags;
__asm__ __volatile__ (
"stc sr, %0\n\t"
"and #0xf0, %0\n\t"
: "=&z" (flags)
: /* no inputs */
: "memory"
);
return flags;
}
#define raw_local_save_flags(flags) \
do { (flags) = __raw_local_save_flags(); } while (0)
static inline int raw_irqs_disabled_flags(unsigned long flags)
{
return (flags != 0);
}
static inline int raw_irqs_disabled(void)
{
unsigned long flags = __raw_local_save_flags();
return raw_irqs_disabled_flags(flags);
}
static inline unsigned long __raw_local_irq_save(void)
{
unsigned long flags, __dummy;
__asm__ __volatile__ (
"stc sr, %1\n\t"
"mov %1, %0\n\t"
"or #0xf0, %0\n\t"
"ldc %0, sr\n\t"
"mov %1, %0\n\t"
"and #0xf0, %0\n\t"
: "=&z" (flags), "=&r" (__dummy)
: /* no inputs */
: "memory"
);
return flags;
}
#define raw_local_irq_save(flags) \
do { (flags) = __raw_local_irq_save(); } while (0)
#define local_irq_save raw_local_irq_save
static inline void raw_local_irq_restore(unsigned long flags)
{
if ((flags & 0xf0) != 0xf0)
raw_local_irq_enable();
}
#define local_irq_restore raw_local_irq_restore
#endif /* __ASM_SH_IRQFLAGS_H */

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#ifndef __ASM_SH_POSIX_TYPES_H
#define __ASM_SH_POSIX_TYPES_H
/*
* This file is generally used by user-level software, so you need to
* be a little careful about namespace pollution etc. Also, we cannot
* assume GCC is being used.
*/
typedef unsigned short __kernel_dev_t;
typedef unsigned long __kernel_ino_t;
typedef unsigned short __kernel_mode_t;
typedef unsigned short __kernel_nlink_t;
typedef long __kernel_off_t;
typedef int __kernel_pid_t;
typedef unsigned short __kernel_ipc_pid_t;
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
typedef int __kernel_timer_t;
typedef int __kernel_clockid_t;
typedef int __kernel_daddr_t;
typedef char * __kernel_caddr_t;
typedef unsigned short __kernel_uid16_t;
typedef unsigned short __kernel_gid16_t;
typedef unsigned int __kernel_uid32_t;
typedef unsigned int __kernel_gid32_t;
typedef unsigned short __kernel_old_uid_t;
typedef unsigned short __kernel_old_gid_t;
typedef unsigned short __kernel_old_dev_t;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
typedef struct {
#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
int __val[2];
#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
#undef __FD_SET
static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
{
unsigned long __tmp = __fd / __NFDBITS;
unsigned long __rem = __fd % __NFDBITS;
__fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
}
#undef __FD_CLR
static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
{
unsigned long __tmp = __fd / __NFDBITS;
unsigned long __rem = __fd % __NFDBITS;
__fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
}
#undef __FD_ISSET
static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
{
unsigned long __tmp = __fd / __NFDBITS;
unsigned long __rem = __fd % __NFDBITS;
return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
}
/*
* This will unroll the loop for the normal constant case (8 ints,
* for a 256-bit fd_set)
*/
#undef __FD_ZERO
static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
{
unsigned long *__tmp = __p->fds_bits;
int __i;
if (__builtin_constant_p(__FDSET_LONGS)) {
switch (__FDSET_LONGS) {
case 16:
__tmp[ 0] = 0; __tmp[ 1] = 0;
__tmp[ 2] = 0; __tmp[ 3] = 0;
__tmp[ 4] = 0; __tmp[ 5] = 0;
__tmp[ 6] = 0; __tmp[ 7] = 0;
__tmp[ 8] = 0; __tmp[ 9] = 0;
__tmp[10] = 0; __tmp[11] = 0;
__tmp[12] = 0; __tmp[13] = 0;
__tmp[14] = 0; __tmp[15] = 0;
return;
case 8:
__tmp[ 0] = 0; __tmp[ 1] = 0;
__tmp[ 2] = 0; __tmp[ 3] = 0;
__tmp[ 4] = 0; __tmp[ 5] = 0;
__tmp[ 6] = 0; __tmp[ 7] = 0;
return;
case 4:
__tmp[ 0] = 0; __tmp[ 1] = 0;
__tmp[ 2] = 0; __tmp[ 3] = 0;
return;
}
}
__i = __FDSET_LONGS;
while (__i) {
__i--;
*__tmp = 0;
__tmp++;
}
}
#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
#endif /* __ASM_SH_POSIX_TYPES_H */

8
include/asm-sh/processor.h Normal file
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#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
#if defined CONFIG_SH3
# include <asm/cpu_sh3.h>
#elif defined (CONFIG_SH4)
# include <asm/cpu_sh4.h>
#endif
#endif

112
include/asm-sh/ptrace.h Normal file
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#ifndef __ASM_SH_PTRACE_H
#define __ASM_SH_PTRACE_H
/*
* Copyright (C) 1999, 2000 Niibe Yutaka
* from linux kernel code.
*/
/*
* GCC defines register number like this:
* -----------------------------
* 0 - 15 are integer registers
* 17 - 22 are control/special registers
* 24 - 39 fp registers
* 40 - 47 xd registers
* 48 - fpscr register
* -----------------------------
*
* We follows above, except:
* 16 --- program counter (PC)
* 22 --- syscall #
* 23 --- floating point communication register
*/
#define REG_REG0 0
#define REG_REG15 15
#define REG_PC 16
#define REG_PR 17
#define REG_SR 18
#define REG_GBR 19
#define REG_MACH 20
#define REG_MACL 21
#define REG_SYSCALL 22
#define REG_FPREG0 23
#define REG_FPREG15 38
#define REG_XFREG0 39
#define REG_XFREG15 54
#define REG_FPSCR 55
#define REG_FPUL 56
/* options set using PTRACE_SETOPTIONS */
#define PTRACE_O_TRACESYSGOOD 0x00000001
/*
* This struct defines the way the registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_regs {
unsigned long regs[16];
unsigned long pc;
unsigned long pr;
unsigned long sr;
unsigned long gbr;
unsigned long mach;
unsigned long macl;
long tra;
};
/*
* This struct defines the way the DSP registers are stored on the
* kernel stack during a system call or other kernel entry.
*/
struct pt_dspregs {
unsigned long a1;
unsigned long a0g;
unsigned long a1g;
unsigned long m0;
unsigned long m1;
unsigned long a0;
unsigned long x0;
unsigned long x1;
unsigned long y0;
unsigned long y1;
unsigned long dsr;
unsigned long rs;
unsigned long re;
unsigned long mod;
};
#define PTRACE_GETDSPREGS 55
#define PTRACE_SETDSPREGS 56
#ifdef __KERNEL__
#define user_mode(regs) (((regs)->sr & 0x40000000)==0)
#define instruction_pointer(regs) ((regs)->pc)
extern void show_regs(struct pt_regs *);
#ifdef CONFIG_SH_DSP
#define task_pt_regs(task) \
((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
- sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1)
#else
#define task_pt_regs(task) \
((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \
- sizeof(unsigned long)) - 1)
#endif
static inline unsigned long profile_pc(struct pt_regs *regs)
{
unsigned long pc = instruction_pointer(regs);
if (pc >= 0xa0000000UL && pc < 0xc0000000UL)
pc -= 0x20000000;
return pc;
}
#endif
#endif /* __ASM_SH_PTRACE_H */

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#ifndef __ASM_SH_STRING_H
#define __ASM_SH_STRING_H
/*
* Copyright (C) 1999 Niibe Yutaka
* But consider these trivial functions to be public domain.
*
* from linux kernel code.
*/
#ifdef __KERNEL__ /* only set these up for kernel code */
#define __HAVE_ARCH_STRCPY
static inline char *strcpy(char *__dest, const char *__src)
{
register char *__xdest = __dest;
unsigned long __dummy;
__asm__ __volatile__("1:\n\t"
"mov.b @%1+, %2\n\t"
"mov.b %2, @%0\n\t"
"cmp/eq #0, %2\n\t"
"bf/s 1b\n\t"
" add #1, %0\n\t"
: "=r" (__dest), "=r" (__src), "=&z" (__dummy)
: "0" (__dest), "1" (__src)
: "memory", "t");
return __xdest;
}
#define __HAVE_ARCH_STRNCPY
static inline char *strncpy(char *__dest, const char *__src, size_t __n)
{
register char *__xdest = __dest;
unsigned long __dummy;
if (__n == 0)
return __xdest;
__asm__ __volatile__(
"1:\n"
"mov.b @%1+, %2\n\t"
"mov.b %2, @%0\n\t"
"cmp/eq #0, %2\n\t"
"bt/s 2f\n\t"
" cmp/eq %5,%1\n\t"
"bf/s 1b\n\t"
" add #1, %0\n"
"2:"
: "=r" (__dest), "=r" (__src), "=&z" (__dummy)
: "0" (__dest), "1" (__src), "r" (__src+__n)
: "memory", "t");
return __xdest;
}
#define __HAVE_ARCH_STRCMP
static inline int strcmp(const char *__cs, const char *__ct)
{
register int __res;
unsigned long __dummy;
__asm__ __volatile__(
"mov.b @%1+, %3\n"
"1:\n\t"
"mov.b @%0+, %2\n\t"
"cmp/eq #0, %3\n\t"
"bt 2f\n\t"
"cmp/eq %2, %3\n\t"
"bt/s 1b\n\t"
" mov.b @%1+, %3\n\t"
"add #-2, %1\n\t"
"mov.b @%1, %3\n\t"
"sub %3, %2\n"
"2:"
: "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
: "0" (__cs), "1" (__ct)
: "t");
return __res;
}
#define __HAVE_ARCH_STRNCMP
static inline int strncmp(const char *__cs, const char *__ct, size_t __n)
{
register int __res;
unsigned long __dummy;
if (__n == 0)
return 0;
__asm__ __volatile__(
"mov.b @%1+, %3\n"
"1:\n\t"
"mov.b @%0+, %2\n\t"
"cmp/eq %6, %0\n\t"
"bt/s 2f\n\t"
" cmp/eq #0, %3\n\t"
"bt/s 3f\n\t"
" cmp/eq %3, %2\n\t"
"bt/s 1b\n\t"
" mov.b @%1+, %3\n\t"
"add #-2, %1\n\t"
"mov.b @%1, %3\n"
"2:\n\t"
"sub %3, %2\n"
"3:"
:"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy)
: "0" (__cs), "1" (__ct), "r" (__cs+__n)
: "t");
return __res;
}
#undef __HAVE_ARCH_MEMSET
extern void *memset(void *__s, int __c, size_t __count);
#undef __HAVE_ARCH_MEMCPY
extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
#undef __HAVE_ARCH_MEMMOVE
extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
#undef __HAVE_ARCH_MEMCHR
extern void *memchr(const void *__s, int __c, size_t __n);
#undef __HAVE_ARCH_STRLEN
extern size_t strlen(const char *);
/* arch/sh/lib/strcasecmp.c */
extern int strcasecmp(const char *, const char *);
#else /* KERNEL */
/*
* let user libraries deal with these,
* IMHO the kernel has no place defining these functions for user apps
*/
#define __HAVE_ARCH_STRCPY 1
#define __HAVE_ARCH_STRNCPY 1
#define __HAVE_ARCH_STRCAT 1
#define __HAVE_ARCH_STRNCAT 1
#define __HAVE_ARCH_STRCMP 1
#define __HAVE_ARCH_STRNCMP 1
#define __HAVE_ARCH_STRNICMP 1
#define __HAVE_ARCH_STRCHR 1
#define __HAVE_ARCH_STRRCHR 1
#define __HAVE_ARCH_STRSTR 1
#define __HAVE_ARCH_STRLEN 1
#define __HAVE_ARCH_STRNLEN 1
#define __HAVE_ARCH_MEMSET 1
#define __HAVE_ARCH_MEMCPY 1
#define __HAVE_ARCH_MEMMOVE 1
#define __HAVE_ARCH_MEMSCAN 1
#define __HAVE_ARCH_MEMCMP 1
#define __HAVE_ARCH_MEMCHR 1
#define __HAVE_ARCH_STRTOK 1
#endif /* KERNEL */
#endif /* __ASM_SH_STRING_H */

275
include/asm-sh/system.h Normal file
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#ifndef __ASM_SH_SYSTEM_H
#define __ASM_SH_SYSTEM_H
/*
* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
* Copyright (C) 2002 Paul Mundt
*
* from linux kernel code.
*/
#include <linux/irqflags.h>
#include <asm/types.h>
/*
* switch_to() should switch tasks to task nr n, first
*/
#define switch_to(prev, next, last) do { \
struct task_struct *__last; \
register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \
register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \
register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
__asm__ __volatile__ (".balign 4\n\t" \
"stc.l gbr, @-r15\n\t" \
"sts.l pr, @-r15\n\t" \
"mov.l r8, @-r15\n\t" \
"mov.l r9, @-r15\n\t" \
"mov.l r10, @-r15\n\t" \
"mov.l r11, @-r15\n\t" \
"mov.l r12, @-r15\n\t" \
"mov.l r13, @-r15\n\t" \
"mov.l r14, @-r15\n\t" \
"mov.l r15, @r1 ! save SP\n\t" \
"mov.l @r6, r15 ! change to new stack\n\t" \
"mova 1f, %0\n\t" \
"mov.l %0, @r2 ! save PC\n\t" \
"mov.l 2f, %0\n\t" \
"jmp @%0 ! call __switch_to\n\t" \
" lds r7, pr ! with return to new PC\n\t" \
".balign 4\n" \
"2:\n\t" \
".long __switch_to\n" \
"1:\n\t" \
"mov.l @r15+, r14\n\t" \
"mov.l @r15+, r13\n\t" \
"mov.l @r15+, r12\n\t" \
"mov.l @r15+, r11\n\t" \
"mov.l @r15+, r10\n\t" \
"mov.l @r15+, r9\n\t" \
"mov.l @r15+, r8\n\t" \
"lds.l @r15+, pr\n\t" \
"ldc.l @r15+, gbr\n\t" \
: "=z" (__last) \
: "r" (__ts1), "r" (__ts2), "r" (__ts4), \
"r" (__ts5), "r" (__ts6), "r" (__ts7) \
: "r3", "t"); \
last = __last; \
} while (0)
/*
* On SMP systems, when the scheduler does migration-cost autodetection,
* it needs a way to flush as much of the CPU's caches as possible.
*
* TODO: fill this in!
*/
static inline void sched_cacheflush(void)
{
}
#ifdef CONFIG_CPU_SH4A
#define __icbi() \
{ \
unsigned long __addr; \
__addr = 0xa8000000; \
__asm__ __volatile__( \
"icbi %0\n\t" \
: /* no output */ \
: "m" (__m(__addr))); \
}
#endif
static inline unsigned long tas(volatile int *m)
{
unsigned long retval;
__asm__ __volatile__ ("tas.b @%1\n\t"
"movt %0"
: "=r" (retval): "r" (m): "t", "memory");
return retval;
}
/*
* A brief note on ctrl_barrier(), the control register write barrier.
*
* Legacy SH cores typically require a sequence of 8 nops after
* modification of a control register in order for the changes to take
* effect. On newer cores (like the sh4a and sh5) this is accomplished
* with icbi.
*
* Also note that on sh4a in the icbi case we can forego a synco for the
* write barrier, as it's not necessary for control registers.
*
* Historically we have only done this type of barrier for the MMUCR, but
* it's also necessary for the CCR, so we make it generic here instead.
*/
#ifdef CONFIG_CPU_SH4A
#define mb() __asm__ __volatile__ ("synco": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("synco": : :"memory")
#define ctrl_barrier() __icbi()
#define read_barrier_depends() do { } while(0)
#else
#define mb() __asm__ __volatile__ ("": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("": : :"memory")
#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
#define read_barrier_depends() do { } while(0)
#endif
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
#define smp_wmb() wmb()
#define smp_read_barrier_depends() read_barrier_depends()
#else
#define smp_mb() barrier()
#define smp_rmb() barrier()
#define smp_wmb() barrier()
#define smp_read_barrier_depends() do { } while(0)
#endif
#define set_mb(var, value) do { xchg(&var, value); } while (0)
/*
* Jump to P2 area.
* When handling TLB or caches, we need to do it from P2 area.
*/
#define jump_to_P2() \
do { \
unsigned long __dummy; \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"or %1, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy) \
: "r" (0x20000000)); \
} while (0)
/*
* Back to P1 area.
*/
#define back_to_P1() \
do { \
unsigned long __dummy; \
ctrl_barrier(); \
__asm__ __volatile__( \
"mov.l 1f, %0\n\t" \
"jmp @%0\n\t" \
" nop\n\t" \
".balign 4\n" \
"1: .long 2f\n" \
"2:" \
: "=&r" (__dummy)); \
} while (0)
static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
{
unsigned long flags, retval;
local_irq_save(flags);
retval = *m;
*m = val;
local_irq_restore(flags);
return retval;
}
static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
{
unsigned long flags, retval;
local_irq_save(flags);
retval = *m;
*m = val & 0xff;
local_irq_restore(flags);
return retval;
}
extern void __xchg_called_with_bad_pointer(void);
#define __xchg(ptr, x, size) \
({ \
unsigned long __xchg__res; \
volatile void *__xchg_ptr = (ptr); \
switch (size) { \
case 4: \
__xchg__res = xchg_u32(__xchg_ptr, x); \
break; \
case 1: \
__xchg__res = xchg_u8(__xchg_ptr, x); \
break; \
default: \
__xchg_called_with_bad_pointer(); \
__xchg__res = x; \
break; \
} \
\
__xchg__res; \
})
#define xchg(ptr,x) \
((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
unsigned long new)
{
__u32 retval;
unsigned long flags;
local_irq_save(flags);
retval = *m;
if (retval == old)
*m = new;
local_irq_restore(flags); /* implies memory barrier */
return retval;
}
/* This function doesn't exist, so you'll get a linker error
* if something tries to do an invalid cmpxchg(). */
extern void __cmpxchg_called_with_bad_pointer(void);
#define __HAVE_ARCH_CMPXCHG 1
static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
unsigned long new, int size)
{
switch (size) {
case 4:
return __cmpxchg_u32(ptr, old, new);
}
__cmpxchg_called_with_bad_pointer();
return old;
}
#define cmpxchg(ptr,o,n) \
({ \
__typeof__(*(ptr)) _o_ = (o); \
__typeof__(*(ptr)) _n_ = (n); \
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
(unsigned long)_n_, sizeof(*(ptr))); \
})
extern void *set_exception_table_vec(unsigned int vec, void *handler);
static inline void *set_exception_table_evt(unsigned int evt, void *handler)
{
return set_exception_table_vec(evt >> 5, handler);
}
/* XXX
* disable hlt during certain critical i/o operations
*/
#define HAVE_DISABLE_HLT
void disable_hlt(void);
void enable_hlt(void);
#define arch_align_stack(x) (x)
#endif

59
include/asm-sh/types.h Normal file
View File

@@ -0,0 +1,59 @@
#ifndef __ASM_SH_TYPES_H
#define __ASM_SH_TYPES_H
#ifndef __ASSEMBLY__
typedef unsigned short umode_t;
/*
* __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
* header files exported to user space
*/
typedef __signed__ char __s8;
typedef unsigned char __u8;
typedef __signed__ short __s16;
typedef unsigned short __u16;
typedef __signed__ int __s32;
typedef unsigned int __u32;
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
typedef __signed__ long long __s64;
typedef unsigned long long __u64;
#endif
#endif /* __ASSEMBLY__ */
/*
* These aren't exported outside the kernel to avoid name space clashes
*/
#ifdef __KERNEL__
#define BITS_PER_LONG 32
#ifndef __ASSEMBLY__
typedef __signed__ char s8;
typedef unsigned char u8;
typedef __signed__ short s16;
typedef unsigned short u16;
typedef __signed__ int s32;
typedef unsigned int u32;
typedef __signed__ long long s64;
typedef unsigned long long u64;
/* Dma addresses are 32-bits wide. */
typedef u32 dma_addr_t;
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_SH_TYPES_H */

42
include/asm-sh/u-boot.h Normal file
View File

@@ -0,0 +1,42 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************
* NOTE: This header file defines an interface to U-Boot. Including
* this (unmodified) header file in another file is considered normal
* use of U-Boot, and does *not* fall under the heading of "derived
* work".
********************************************************************
*/
#ifndef __ASM_SH_U_BOOT_H_
#define __ASM_SH_U_BOOT_H_
typedef struct bd_info {
unsigned long bi_memstart; /* start of DRAM memory */
unsigned long bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
unsigned long bi_baudrate; /* Console Baudrate */
unsigned long bi_boot_params; /* where this board expects params */
} bd_t;
#endif

20
include/bcd.h Normal file
View File

@@ -0,0 +1,20 @@
/* Permission is hereby granted to copy, modify and redistribute this code
* in terms of the GNU Library General Public License, Version 2 or later,
* at your option.
*/
/* macros to translate to/from binary and binary-coded decimal (frequently
* found in RTC chips).
*/
#ifndef _BCD_H
#define _BCD_H
#define BCD2BIN(val) (((val) & 0x0f) + ((val)>>4)*10)
#define BIN2BCD(val) ((((val)/10)<<4) + (val)%10)
/* backwards compat */
#define BCD_TO_BIN(val) ((val)=BCD2BIN(val))
#define BIN_TO_BCD(val) ((val)=BIN2BCD(val))
#endif /* _BCD_H */

20
include/common.h
View File

@@ -129,20 +129,21 @@ typedef void (interrupt_handler_t)(void *);
/*
* enable common handling for all TQM8xxL/M boards:
* - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards
* - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
* - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
* and for the TQM885D board
*/
#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \
defined(CONFIG_TQM885D)
defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
# ifndef CONFIG_TQM8xxM
# define CONFIG_TQM8xxM
# endif
#endif
#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \
defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \
defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM)
defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \
defined(CONFIG_TQM885D)
# ifndef CONFIG_TQM8xxL
# define CONFIG_TQM8xxL
# endif
@@ -258,7 +259,7 @@ void pciinfo (int, int);
int pci_pre_init (struct pci_controller * );
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_440)
#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX))
# if defined(CFG_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif
@@ -266,7 +267,7 @@ void pciinfo (int, int);
void pci_master_init (struct pci_controller *);
# endif
int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE)
#if defined(CONFIG_440SPE) || defined(CONFIG_405EX)
void pcie_setup_hoses(int busno);
#endif
#endif
@@ -497,6 +498,7 @@ ulong get_bus_freq (ulong);
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
ulong get_ddr_freq (ulong);
#endif
#if defined(CONFIG_MPC86xx)
typedef MPC86xx_SYS_INFO sys_info_t;
@@ -505,15 +507,13 @@ void get_sys_info ( sys_info_t * );
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
typedef PPC440_SYS_INFO sys_info_t;
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
int ppc440spe_revB(void);
# endif
# else
typedef PPC405_SYS_INFO sys_info_t;
# endif
typedef PPC4xx_SYS_INFO sys_info_t;
int ppc440spe_revB(void);
void get_sys_info ( sys_info_t * );
#endif

9
include/configs/ADCIOP.h
View File

@@ -191,15 +191,6 @@
#define CFG_ETH_DEV_FN 0x0000
#define CFG_ETH_IOBASE 0x0fff0000
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

8
include/configs/AP1000.h
View File

@@ -193,14 +193,6 @@
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:

10
include/configs/AR405.h
View File

@@ -213,16 +213,6 @@
#define CFG_ENV_ADDR_REDUND 0xFFFA0000
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

10
include/configs/ASH405.h
View File

@@ -258,16 +258,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

9
include/configs/CANBT.h
View File

@@ -181,15 +181,6 @@
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

10
include/configs/CMS700.h
View File

@@ -272,16 +272,6 @@
#define CFG_EEPROM_WREN 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/

10
include/configs/CPCI2DP.h
View File

@@ -223,16 +223,6 @@
#define CFG_EEPROM_WREN 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

9
include/configs/CPCI405.h
View File

@@ -266,15 +266,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

10
include/configs/CPCI4052.h
View File

@@ -317,16 +317,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

10
include/configs/CPCI405AB.h
View File

@@ -288,16 +288,6 @@
#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

10
include/configs/CPCI405DT.h
View File

@@ -319,16 +319,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

296
include/configs/CPCI440.h
View File

@@ -1,296 +0,0 @@
/*
* (C) Copyright 2002
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* board/config_CPCI440.h - configuration for esd CPCI-440 board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_CPCI440 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
#if 1
#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
#else
#define CFG_MONITOR_BASE 0x01fc0000 /* start of monitor */
#endif
#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK /* (1843200 * 6) / * Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
/*-----------------------------------------------------------------------
* NVRAM/RTC
*
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
* The DS1743 code assumes this condition (i.e. -- it assumes the base
* address for the RTC registers is:
*
* CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
*
*----------------------------------------------------------------------*/
#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#if 1 /* test-only */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#undef CFG_FLASH_BASE
#define CFG_FLASH_BASE 0xFF800000 /* test-only...*/
#else /* test-only */
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#endif
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if 0 /* test-only */
#define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */
#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
#else
#if 0 /* test-only */
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET 0x010 /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
#else
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#endif
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#endif
#undef CONFIG_BOOTARGS
#undef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_BAUDRATE 9600
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#undef CONFIG_WATCHDOG /* watchdog disabled */
#undef CONFIG_SPD_EEPROM /* don't use SPD EEPROM for setup */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#if 0 /* test-only */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#endif
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#if 0
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
#endif
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
/*-----------------------------------------------------------------------
* Definitions for Serial Presence Detect EEPROM address
* (to get SDRAM settings)
*/
#define SPD_EEPROM_ADDRESS 0x50
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

9
include/configs/CPCIISER4.h
View File

@@ -205,15 +205,6 @@
#define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
/* total size of a CAT24WC08 is 1024 bytes */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

6
include/configs/CRAYL1.h
View File

@@ -192,12 +192,6 @@
#define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
/* END ENVIRONNEMENT FLASH */
/*-----------------------------------------------------------------------
* Cache Configuration. Only used to ..?? clear it, I guess..
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
/*
* Init Memory Controller:
*

9
include/configs/DASA_SIM.h
View File

@@ -182,15 +182,6 @@
#define CFG_PCI9054_DEV_FN 0x0800
#define CFG_PCI9054_IOBASE 0x0eff0000
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

10
include/configs/DP405.h
View File

@@ -241,16 +241,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/

9
include/configs/DU405.h
View File

@@ -232,15 +232,6 @@
#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
/* total size of a CAT24WC08 is 1024 bytes */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

8
include/configs/ERIC.h
View File

@@ -323,14 +323,6 @@
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:

4
include/configs/EXBITGEN.h
View File

@@ -205,10 +205,6 @@
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/* Cache configuration */
#define CFG_DCACHE_SIZE 8192
#define CFG_CACHELINE_SIZE 32
/*
* Internal Definitions
*

10
include/configs/G2000.h
View File

@@ -330,16 +330,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/

10
include/configs/HH405.h
View File

@@ -362,16 +362,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/

12
include/configs/HMI10.h
View File

@@ -224,11 +224,15 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */

10
include/configs/HUB405.h
View File

@@ -257,16 +257,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

9
include/configs/JSE.h
View File

@@ -279,15 +279,6 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

8
include/configs/KAREF.h
View File

@@ -281,14 +281,6 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#endif
/*
* Internal Definitions

8
include/configs/METROBOX.h
View File

@@ -346,14 +346,6 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
#endif
/*
* Internal Definitions

9
include/configs/MIP405.h
View File

@@ -257,15 +257,6 @@
#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)"
*/
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* Logbuffer Configuration
*/

8
include/configs/ML2.h
View File

@@ -201,14 +201,6 @@
#define CFG_ENV_ADDR \
(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:

12
include/configs/MPC8540ADS.h
View File

@@ -298,13 +298,9 @@
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,8540@0"
#define OF_SOC "soc8540@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500"
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
#define CFG_64BIT_VSPRINTF 1
#define CFG_64BIT_STRTOUL 1
@@ -424,6 +420,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -441,6 +438,7 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */

13
include/configs/MPC8541CDS.h
View File

@@ -309,14 +309,9 @@ extern unsigned long get_clock_freq(void);
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,8541@0"
#define OF_SOC "soc8541@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
#define OF_PCI "pci@e0008000"
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -422,6 +417,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -434,6 +430,7 @@ extern unsigned long get_clock_freq(void);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)

119
include/configs/MPC8544DS.h
View File

@@ -40,6 +40,7 @@
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -251,13 +252,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,8544@0"
#define OF_SOC "soc8544@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500"
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
@@ -410,6 +407,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -426,6 +424,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
@@ -475,10 +474,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.251
@@ -488,8 +483,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_BOOTFILE 8544ds/uImage.uboot
#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
@@ -499,65 +494,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_BAUDRATE 115200
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
#define PCIE_ENV \
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
"pcieerr=md ${a}020 1; md ${a}e00 e;" \
"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1;" \
"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
"pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \
"pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \
"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
"pci w $b.0 130 ffffffff\0" \
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
"pcie1regs=setenv a e000a; run pciereg\0" \
"pcie2regs=setenv a e0009; run pciereg\0" \
"pcie3regs=setenv a e000b; run pciereg\0" \
"pcie1cfg=setenv b 3; run pciecfg\0" \
"pcie2cfg=setenv b 5; run pciecfg\0" \
"pcie3cfg=setenv b 0; run pciecfg\0" \
"pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
"pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
"pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
"pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
"pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
"pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
#else
#define PCIE_ENV ""
#endif
#if defined(CONFIG_PCI1)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
"echo e;md ${a}e00 9\0" \
"pci1regs=setenv a e0008; run pcireg\0" \
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1\0" \
"pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
"pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
"pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
#else
#define PCI_ENV ""
#endif
#if defined(CONFIG_TSEC_ENET)
#define ENET_ENV \
"enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
"md ${a}098 2\0" \
"enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
"enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
"enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
"echo mib;md ${a}680 31\0" \
"enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
"enet1regs=setenv a e0024; run enetreg\0" \
"enet3regs=setenv a e0026; run enetreg\0"
#else
#define ENET_ENV ""
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
@@ -570,29 +506,9 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8544ds/ramdisk.uboot\0" \
"dtbaddr=c00000\0" \
"dtbfile=8544ds/mpc8544ds.dtb\0" \
"bdev=sda3\0" \
"eoi=mw e00400b0 0\0" \
"iack=md e00400a0 1\0" \
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
"ddrregs=setenv a e0002; run ddrreg\0" \
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
"guregs=setenv a e00e0; run gureg\0" \
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
"ecmregs=setenv a e0001; run ecmreg\0" \
"lawregs=md e0000c08 4b\0" \
"lbcregs=md e0005000 36\0" \
"dma0regs=md e0021100 12\0" \
"dma1regs=md e0021180 12\0" \
"dma2regs=md e0021200 12\0" \
"dma3regs=md e0021280 12\0" \
PCIE_ENV \
PCI_ENV \
ENET_ENV
"fdtaddr=c00000\0" \
"fdtfile=8544ds/mpc8544ds.dtb\0" \
"bdev=sda3\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
@@ -600,23 +516,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $dtbaddr $dtbfile;" \
"bootm $loadaddr - $dtbaddr"
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $dtbaddr $dtbfile;" \
"bootm $loadaddr $ramdiskaddr $dtbaddr"
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $dtbaddr $dtbfile;" \
"bootm $loadaddr - $dtbaddr"
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#endif /* __CONFIG_H */

103
include/configs/MPC8548CDS.h
View File

@@ -42,6 +42,7 @@
#undef CONFIG_RIO
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
@@ -333,14 +334,9 @@ extern unsigned long get_clock_freq(void);
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,8548@0"
#define OF_SOC "soc8548@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
#define OF_PCI "pci@e0008000"
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -483,6 +479,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -495,6 +492,7 @@ extern unsigned long get_clock_freq(void);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
@@ -568,72 +566,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_BAUDRATE 115200
#if defined(CONFIG_PCIE1)
#define PCIE_ENV \
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
"pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
"pci d $b.0 130 1\0" \
"pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
"pcie1regs=setenv a e000a; run pciereg\0" \
"pcie1cfg=setenv b 3; run pciecfg\0" \
"pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
"pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
#else
#define PCIE_ENV ""
#endif
#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
"echo e;md ${a}e00 9\0" \
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1\0" \
"pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
#else
#define PCI_ENV ""
#endif
#if defined(CONFIG_PCI1)
#define PCI_ENV1 \
"pci1regs=setenv a e0008; run pcireg\0" \
"pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
"pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
#else
#define PCI_ENV1 ""
#endif
#if defined(CONFIG_PCI2)
#define PCI_ENV2 \
"pci2regs=setenv a e0009; run pcireg\0" \
"pci2err=setenv a e0009; setenv b 123; run pcierr\0" \
"pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
#else
#define PCI_ENV2 ""
#endif
#if defined(CONFIG_TSEC_ENET)
#define ENET_ENV \
"enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
"md ${a}098 2\0" \
"enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
"enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
"enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
"echo mib;md ${a}680 31\0" \
"enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
"enet1regs=setenv a e0024; run enetreg\0" \
"enet2regs=setenv a e0025; run enetreg\0" \
"enet3regs=setenv a e0026; run enetreg\0" \
"enet4regs=setenv a e0027; run enetreg\0"
#else
#define ENET_ENV ""
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
@@ -647,28 +579,7 @@ extern unsigned long get_clock_freq(void);
"ramdiskaddr=2000000\0" \
"ramdiskfile=ramdisk.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=mpc8548cds.dtb\0" \
"eoi=mw e00400b0 0\0" \
"iack=md e00400a0 1\0" \
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
"ddrregs=setenv a e0002; run ddrreg\0" \
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
"guregs=setenv a e00e0; run gureg\0" \
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
"ecmregs=setenv a e0001; run ecmreg\0" \
"lawregs=md e0000c08 4b\0" \
"lbcregs=md e0005000 36\0" \
"dma0regs=md e0021100 12\0" \
"dma1regs=md e0021180 12\0" \
"dma2regs=md e0021200 12\0" \
"dma3regs=md e0021280 12\0" \
PCIE_ENV \
PCI_ENV \
PCI_ENV1 \
PCI_ENV2 \
ENET_ENV
"fdtfile=mpc8548cds.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \

13
include/configs/MPC8555CDS.h
View File

@@ -309,14 +309,9 @@ extern unsigned long get_clock_freq(void);
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,8555@0"
#define OF_SOC "soc8555@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
#define OF_PCI "pci@e0008000"
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -422,6 +417,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -434,6 +430,7 @@ extern unsigned long get_clock_freq(void);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)

14
include/configs/MPC8560ADS.h
View File

@@ -289,13 +289,9 @@
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,8560@0"
#define OF_SOC "soc8560@e0000000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8560@e0000000/serial@4500"
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -450,6 +446,7 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -471,6 +468,7 @@
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x1000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
@@ -525,6 +523,8 @@
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253

39
include/configs/MPC8568MDS.h
View File

@@ -33,7 +33,11 @@
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
#define CONFIG_PCI
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI1 1 /* PCI controller */
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
@@ -87,6 +91,9 @@ extern unsigned long get_clock_freq(void);
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
/*
* DDR Setup
*/
@@ -290,14 +297,9 @@ extern unsigned long get_clock_freq(void);
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,8568@0"
#define OF_SOC "soc8568@e0000000"
#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4500"
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* I2C
@@ -325,12 +327,12 @@ extern unsigned long get_clock_freq(void);
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
#define CFG_PEX_MEM_BASE 0xa0000000
#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
#define CFG_PEX_MEM_SIZE 0x10000000 /* 256M */
#define CFG_PEX_IO_BASE 0x00000000
#define CFG_PEX_IO_PHYS 0xe2800000
#define CFG_PEX_IO_SIZE 0x00800000 /* 8M */
#define CFG_PCIE1_MEM_BASE 0xa0000000
#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCIE1_IO_BASE 0x00000000
#define CFG_PCIE1_IO_PHYS 0xe2800000
#define CFG_PCIE1_IO_SIZE 0x00800000 /* 8M */
#define CFG_SRIO_MEM_BASE 0xc0000000
@@ -383,6 +385,11 @@ extern unsigned long get_clock_freq(void);
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x80000000
#endif /* CONFIG_PCI */
#ifndef CONFIG_NET_MULTI
@@ -440,6 +447,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@@ -452,6 +460,7 @@ extern unsigned long get_clock_freq(void);
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)

9
include/configs/OCRTC.h
View File

@@ -222,15 +222,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

9
include/configs/ORSG.h
View File

@@ -220,15 +220,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

9
include/configs/PCI405.h
View File

@@ -251,15 +251,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

9
include/configs/PIP405.h
View File

@@ -231,15 +231,6 @@
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*/

16
include/configs/PLU405.h
View File

@@ -288,6 +288,7 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
#define CFG_EEPROM_WREN 1
/* CAT24WC08/16... */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
@@ -299,16 +300,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
@@ -389,15 +380,16 @@
* GPIO0[28-29] - UART1 data signal input/output
* GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
*/
#define CFG_GPIO0_OSRH 0x40000550
#define CFG_GPIO0_OSRH 0x00000550
#define CFG_GPIO0_OSRL 0x00000110
#define CFG_GPIO0_ISR1H 0x00000000
#define CFG_GPIO0_ISR1L 0x15555445
#define CFG_GPIO0_TSRH 0x00000000
#define CFG_GPIO0_TSRL 0x00000000
#define CFG_GPIO0_TCR 0xF7FE0014
#define CFG_GPIO0_TCR 0x77FE0014
#define CFG_DUART_RST (0x80000000 >> 14)
#define CFG_EEPROM_WP (0x80000000 >> 0)
/*
* Internal Definitions

10
include/configs/PMC405.h
View File

@@ -269,16 +269,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/

522
include/configs/PMC440.h Normal file
View File

@@ -0,0 +1,522 @@
/*
* (C) Copyright 2007
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
* Based on the sequoia configuration file.
*
* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* PMC440.h - configuration for esd PMC440 boards
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333400
#define CONFIG_4xx_DCACHE /* enable dcache */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_BOARD_TYPES 1 /* support board types */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
#define CONFIG_PRAM 0 /* use pram variable to overwrite */
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
#define CFG_PCI_MEMSIZE 0x80000000 /* 2GB! */
/* Don't change either of these */
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CFG_USB2D0_BASE 0xe0000100
#define CFG_USB_DEVICE 0xe0000000
#define CFG_USB_HOST 0xe0000400
#define CFG_FPGA_BASE0 0xef000000 /* 32 bit */
#define CFG_FPGA_BASE1 0xef100000 /* 16 bit */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_UART1_CONSOLE /* console on front panel */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
#else
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
#endif
/*-----------------------------------------------------------------------
* RTC
*----------------------------------------------------------------------*/
#define CONFIG_RTC_RX8025
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif
#ifdef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
#endif
/*
* IPL (Initial Program Loader, integrated inside CPU)
* Will load first 4k from NAND (SPL) into cache and execute it from there.
*
* SPL (Secondary Program Loader)
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
* controller and the NAND controller so that the special U-Boot image can be
* loaded from NAND to SDRAM.
*
* NUB (NAND U-Boot)
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
*
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
* set up. While still running from cache, I experienced problems accessing
* the NAND controller. sr - 2006-08-25
*/
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
/*
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
*/
#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
#define CFG_NAND_ECCSIZE 256
#define CFG_NAND_ECCBYTES 3
#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
#define CFG_NAND_OOBSIZE 16
#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
#ifdef CFG_ENV_IS_IN_NAND
/*
* For NAND booting the environment is embedded in the U-Boot image. Please take
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
*/
#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM (256) /* 256MB */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
#endif
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CONFIG_I2C_CMD_TREE 1
#define CONFIG_I2C_MULTI_BUS 1
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR 0x54
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 5
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CFG_EEPROM_WREN 1
#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
/*
* standard dtt sensor configuration - bottom bit will determine local or
* remote sensor of the TMP401
*/
#define CONFIG_DTT_SENSORS { 0, 1 }
/*
* The PMC440 uses a TI TMP401 temperature sensor. This part
* is basically compatible to the ADM1021 that is supported
* by U-Boot.
*
* - i2c addr 0x4c
* - conversion rate 0x02 = 0.25 conversions/second
* - ALERT ouput disabled
* - local temp sensor enabled, min set to 0 deg, max set to 70 deg
* - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
*/
#define CONFIG_DTT_ADM1021
#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
#define CONFIG_PREBOOT /* enable preboot variable */
#undef CONFIG_BOOTARGS
/* Setup some board specific values for the default environment variables */
#define CONFIG_HOSTNAME pmc440
#define CFG_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
#define CFG_ROOTPATH "rootpath=/opt/eldk_410/ppc_4xx\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
CFG_BOOTFILE \
CFG_ROOTPATH \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
"load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
"cp.b 200000 FFFA0000 60000\0" \
""
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 1
#define CONFIG_RESET_PHY_R 1
/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CFG_OHCI_BE_CONTROLLER
#define CFG_USB_OHCI_BOARD_INIT 1
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
#define CFG_USB_OHCI_SLOT_NAME "ppc440"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#include <config_cmd_default.h>
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SDRAM
/* POST support */
/* ethernet POST sometimes freezes the CPU.
* So disable it for now until issue is solved
*/
#if 0
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_UART | \
CFG_POST_I2C | \
CFG_POST_CACHE | \
CFG_POST_FPU | \
CFG_POST_ETHER | \
CFG_POST_SPR)
#else
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_UART | \
CFG_POST_I2C | \
CFG_POST_CACHE | \
CFG_POST_FPU | \
CFG_POST_SPR)
#endif
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
/* esd expects pram at end of physical memory.
* So no logbuffer at the moment.
*/
#if 0
#define CONFIG_LOGBUFFER
#endif
#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_SUPPORT_VFAT
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
#undef CONFIG_AUTOBOOT_DELAY_STR
#define CONFIG_AUTOBOOT_STOP_STR " "
/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
/* PCI identification */
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CFG_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
#define CFG_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
#define CFG_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
#define CFG_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FPGA stuff
*----------------------------------------------------------------------*/
#define CONFIG_FPGA
#define CONFIG_FPGA_XILINX
#define CONFIG_FPGA_SPARTAN2
#define CONFIG_FPGA_SPARTAN3
#define CONFIG_FPGA_COUNT 2
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
/*
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
*/
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_NAND_CS 2 /* NAND chip connected to CSx */
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03017200
#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
/* Memory Bank 2 (NAND-FLASH) initialization */
#define CFG_EBC_PB2AP 0x018003c0
#define CFG_EBC_PB2CR (CFG_NAND_ADDR | 0x1c000)
#else
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
/* Memory Bank 2 (NOR-FLASH) initialization */
#define CFG_EBC_PB2AP 0x03017200
#define CFG_EBC_PB2CR (CFG_FLASH_BASE | 0xda000)
/* Memory Bank 0 (NAND-FLASH) initialization */
#define CFG_EBC_PB0AP 0x018003c0
#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
#endif
/* Memory Bank 4 (FPGA / 32Bit) initialization */
#define CFG_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
#define CFG_EBC_PB4CR (CFG_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */
/* Memory Bank 5 (FPGA / 16Bit) initialization */
#define CFG_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
#define CFG_EBC_PB5CR (CFG_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */
/*-----------------------------------------------------------------------
* NAND FLASH
*----------------------------------------------------------------------*/
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#endif /* __CONFIG_H */

10
include/configs/PPChameleonEVB.h
View File

@@ -454,16 +454,6 @@
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
/* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Init Memory Controller:
*

3
include/configs/TB5200.h
View File

@@ -335,7 +335,7 @@
#else
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#endif /* CONFIG_TQM5200_B */
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
#define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
@@ -392,6 +392,7 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else

12
include/configs/TQM823L.h
View File

@@ -192,11 +192,15 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */

14
include/configs/TQM823M.h
View File

@@ -188,15 +188,19 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */

12
include/configs/TQM850L.h
View File

@@ -179,11 +179,15 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */

14
include/configs/TQM850M.h
View File

@@ -177,15 +177,19 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */

12
include/configs/TQM855L.h
View File

@@ -183,11 +183,15 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */

14
include/configs/TQM855M.h
View File

@@ -217,15 +217,19 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */

12
include/configs/TQM860L.h
View File

@@ -186,11 +186,15 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */

20
include/configs/TQM860M.h
View File

@@ -189,11 +189,14 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
@@ -368,7 +371,7 @@
*/
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM 0x00000A00
@@ -444,7 +447,10 @@
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 10 column SDRAM */
#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
* Internal Definitions

13
include/configs/TQM862L.h
View File

@@ -186,14 +186,17 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_USE_BUFFER_WRITE 1
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */

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