ARM: Fix for wrong patch version applied for Lyrtech SFF-SDR board (ARM926EJS)
ARM: Fix for incorrect version of patch applied when adding support for the Lyrtech SFF-SDR board. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> Signed-off-by: Philip Balister, OpenSDR <philip@opensdr.com>
This commit is contained in:
Hugo Villeneuve
committed by
Wolfgang Denk
Wolfgang Denk
parent
47042b363e
commit
2b1fa9d383
@@ -1,6 +1,9 @@
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/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
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* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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@@ -21,30 +24,24 @@
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#define __CONFIG_H
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#include <asm/sizes.h>
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/*=======*/
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/* Board */
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/*=======*/
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#define SFFSDR
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#define CFG_NAND_LARGEPAGE
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#define CFG_USE_NAND
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/*===================*/
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#define CFG_USE_DSPLINK /* This is to prevent U-Boot from
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* powering ON the DSP. */
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/* SoC Configuration */
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/*===================*/
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */
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#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */
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#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */
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#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */
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#define CFG_HZ 1000
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/*==================================================*/
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/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
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/*==================================================*/
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/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
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#define CFG_I2C_EEPROM_ADDR_LEN 2
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#define CFG_I2C_EEPROM_ADDR 0x50
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#define CFG_EEPROM_PAGE_WRITE_BITS 5
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
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/*=============*/
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/* Memory Info */
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/*=============*/
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#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
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#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */
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#define CFG_MEMTEST_START 0x80000000 /* memtest start address */
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@@ -54,9 +51,7 @@
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#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
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#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
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#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
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/*====================*/
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/* Serial Driver info */
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/*====================*/
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */
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@@ -65,16 +60,12 @@
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*===================*/
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/* I2C Configuration */
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/*===================*/
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#define CONFIG_HARD_I2C
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#define CONFIG_DRIVER_DAVINCI_I2C
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#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
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#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
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/*==================================*/
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/* Network & Ethernet Configuration */
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/*==================================*/
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_MII
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#define CONFIG_BOOTP_DEFAULT
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@@ -83,9 +74,7 @@
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/*=====================*/
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/* Flash & Environment */
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/*=====================*/
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#undef CFG_ENV_IS_IN_FLASH
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#define CFG_NO_FLASH
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#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
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@@ -98,28 +87,19 @@
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#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define NAND_MAX_CHIPS 1
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#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
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/*=====================*/
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/* Board related stuff */
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/*=====================*/
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/*==========================================*/
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/* I2C switch definitions for PCA9543 chip */
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/* on Lyrtech SFF SDR board. */
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/* This chip has a single register. */
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/*==========================================*/
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/* I2C switch definitions for PCA9543 chip */
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#define CFG_I2C_PCA9543_ADDR 0x70
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#define CFG_I2C_PCA9543_ADDR_LEN 0
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#define CFG_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
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#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
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/*==============================*/
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/* U-Boot general configuration */
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/*==============================*/
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#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
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#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
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#define CONFIG_MISC_INIT_R
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#undef CONFIG_BOOTDELAY
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#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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/* Print buffer size */
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#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
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#define CFG_PBSIZE \
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(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print buffer size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel
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@@ -133,25 +113,20 @@
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#define CFG_LONGHELP
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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/*
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* Define this to load an Integrity kernel.
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*
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#define CONFIG_CMD_ELF
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*/
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/*===================*/
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/* Linux Information */
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/*===================*/
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#define LINUX_BOOT_PARAM_ADDR 0x80000100
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_BOOTARGS \
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"mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
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#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
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/*=================*/
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#define CONFIG_BOOTARGS \
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"mem=56M " \
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"console=ttyS0,115200n8 " \
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"root=/dev/nfs rw noinitrd ip=dhcp " \
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"nfsroot=${serverip}:/nfsroot/sffsdr " \
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"eth0=${ethaddr}"
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#define CONFIG_BOOTCOMMAND \
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"nand read 87A00000 100000 300000;" \
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"bootelf 87A00000"
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/* U-Boot commands */
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/*=================*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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@@ -167,9 +142,7 @@
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#undef CONFIG_CMD_SETGETDCR
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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/*=======================*/
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/* KGDB support (if any) */
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/*=======================*/
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
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