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Merge branch 'wd'

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This commit is contained in:
Jon Loeliger
2006-08-09 13:36:54 -05:00
parent 870cbeaa45 6587f7e1e9
commit 281f69ede2
248 changed files with 24221 additions and 6667 deletions
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10
include/405_mal.h
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@@ -92,11 +92,21 @@
#define MAL_ESR_PBEI 0x00000001
/* ^^ ^^ */
/* Mal IER */
#ifdef CONFIG_440SPE
#define MAL_IER_PT 0x00000080
#define MAL_IER_PRE 0x00000040
#define MAL_IER_PWE 0x00000020
#define MAL_IER_DE 0x00000010
#define MAL_IER_OTE 0x00000004
#define MAL_IER_OE 0x00000002
#define MAL_IER_PE 0x00000001
#else
#define MAL_IER_DE 0x00000010
#define MAL_IER_NE 0x00000008
#define MAL_IER_TE 0x00000004
#define MAL_IER_OPBE 0x00000002
#define MAL_IER_PLBE 0x00000001
#endif
/* MAL Channel Active Set and Reset Registers */
#define MAL_TXRX_CASR (0x80000000)

82
include/asm-m68k/immap_5282.h
View File

@@ -13,7 +13,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -25,39 +25,61 @@
#ifndef __IMMAP_5282__
#define __IMMAP_5282__
struct sys_ctrl {
uint ipsbar;
char res1[4];
uint rambar;
char res2[4];
uchar crsr;
uchar cwcr;
uchar lpicr;
uchar cwsr;
uint dmareqc;
char res3[4];
uint mpark;
/* TODO: finish these */
};
/* Fast ethernet controller registers
*/
typedef struct fec {
uint fec_ecntrl; /* ethernet control register */
uint fec_ievent; /* interrupt event register */
uint fec_imask; /* interrupt mask register */
uint fec_ivec; /* interrupt level and vector status */
uint fec_r_des_active; /* Rx ring updated flag */
uint fec_x_des_active; /* Tx ring updated flag */
uint res3[10]; /* reserved */
uint fec_mii_data; /* MII data register */
uint fec_mii_speed; /* MII speed control register */
uint res4[17]; /* reserved */
uint fec_r_bound; /* end of RAM (read-only) */
uint fec_r_fstart; /* Rx FIFO start address */
uint res5[6]; /* reserved */
uint fec_x_fstart; /* Tx FIFO start address */
uint res7[21]; /* reserved */
uint fec_r_cntrl; /* Rx control register */
uint fec_r_hash; /* Rx hash register */
uint res8[14]; /* reserved */
uint fec_x_cntrl; /* Tx control register */
uint res9[0x9e]; /* reserved */
uint fec_addr_low; /* lower 32 bits of station address */
uint fec_addr_high; /* upper 16 bits of station address */
uint fec_hash_table_high; /* upper 32-bits of hash table */
uint fec_hash_table_low; /* lower 32-bits of hash table */
uint fec_r_des_start; /* beginning of Rx descriptor ring */
uint fec_x_des_start; /* beginning of Tx descriptor ring */
uint fec_r_buff_size; /* Rx buffer size */
uint res2[9]; /* reserved */
uchar fec_fifo[960]; /* fifo RAM */
uint res1; /* reserved 1000*/
uint fec_ievent; /* interrupt event register 1004*/ /* EIR */
uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */
uint res2; /* reserved 100c*/
uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */
uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */
uint res3[3]; /* reserved 1018*/
uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */
uint res4[6]; /* reserved 1028*/
uint fec_mii_data; /* MII data register 1040*/ /* MDATA */
uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */
/*1044*/
uint res5[7]; /* reserved 1048*/
uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */
uint res6[7]; /* reserved 1068*/
uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */
uint res7[15]; /* reserved 1088*/
uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */
uint res8[7]; /* reserved 10C8*/
uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */
uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */
uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */
uint res9[10]; /* reserved 10F0*/
uint fec_ihash_table_high; /* upper 32-bits of individual hash */ /* IAUR */
uint fec_ihash_table_low; /* lower 32-bits of individual hash */ /* IALR */
uint fec_ghash_table_high; /* upper 32-bits of group hash */ /* GAUR */
uint fec_ghash_table_low; /* lower 32-bits of group hash */ /* GALR */
uint res10[7]; /* reserved 1128*/
uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */
uint res11; /* reserved 1148*/
uint fec_r_bound; /* FIFO Receive Bound Register = end of */ /* FRBR */
uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = */ /* FRSR */
uint res12[11]; /* reserved 1154*/
uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*/ /* ERDSR */
uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*/ /* ETDSR */
uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */
} fec_t;
#endif /* __IMMAP_5282__ */

525
include/asm-m68k/m5282.h
View File

@@ -1,9 +1,6 @@
/*
* mcf5282.h -- Definitions for Motorola Coldfire 5282
*
* Based on mcf5282sim.h of uCLinux distribution:
* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -34,27 +31,515 @@
#define INT_RAM_SIZE 65536
/* General Purpose I/O Module GPIO */
/*
* Define the 5282 SIM register set addresses.
*/
#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */
#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
#define MCFINTC_IRLR 0x18 /* */
#define MCFINTC_IACKL 0x19 /* */
#define MCFINTC_ICR0 0x40 /* Base ICR register */
#define MCFGPIO_PORTA (*(vu_char *) (CFG_MBAR+0x100000))
#define MCFGPIO_PORTB (*(vu_char *) (CFG_MBAR+0x100001))
#define MCFGPIO_PORTC (*(vu_char *) (CFG_MBAR+0x100002))
#define MCFGPIO_PORTD (*(vu_char *) (CFG_MBAR+0x100003))
#define MCFGPIO_PORTE (*(vu_char *) (CFG_MBAR+0x100004))
#define MCFGPIO_PORTF (*(vu_char *) (CFG_MBAR+0x100005))
#define MCFGPIO_PORTG (*(vu_char *) (CFG_MBAR+0x100006))
#define MCFGPIO_PORTH (*(vu_char *) (CFG_MBAR+0x100007))
#define MCFGPIO_PORTJ (*(vu_char *) (CFG_MBAR+0x100008))
#define MCFGPIO_PORTDD (*(vu_char *) (CFG_MBAR+0x100009))
#define MCFGPIO_PORTEH (*(vu_char *) (CFG_MBAR+0x10000A))
#define MCFGPIO_PORTEL (*(vu_char *) (CFG_MBAR+0x10000B))
#define MCFGPIO_PORTAS (*(vu_char *) (CFG_MBAR+0x10000C))
#define MCFGPIO_PORTQS (*(vu_char *) (CFG_MBAR+0x10000D))
#define MCFGPIO_PORTSD (*(vu_char *) (CFG_MBAR+0x10000E))
#define MCFGPIO_PORTTC (*(vu_char *) (CFG_MBAR+0x10000F))
#define MCFGPIO_PORTTD (*(vu_char *) (CFG_MBAR+0x100010))
#define MCFGPIO_PORTUA (*(vu_char *) (CFG_MBAR+0x100011))
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */
#define MCFGPIO_DDRA (*(vu_char *) (CFG_MBAR+0x100014))
#define MCFGPIO_DDRB (*(vu_char *) (CFG_MBAR+0x100015))
#define MCFGPIO_DDRC (*(vu_char *) (CFG_MBAR+0x100016))
#define MCFGPIO_DDRD (*(vu_char *) (CFG_MBAR+0x100017))
#define MCFGPIO_DDRE (*(vu_char *) (CFG_MBAR+0x100018))
#define MCFGPIO_DDRF (*(vu_char *) (CFG_MBAR+0x100019))
#define MCFGPIO_DDRG (*(vu_char *) (CFG_MBAR+0x10001A))
#define MCFGPIO_DDRH (*(vu_char *) (CFG_MBAR+0x10001B))
#define MCFGPIO_DDRJ (*(vu_char *) (CFG_MBAR+0x10001C))
#define MCFGPIO_DDRDD (*(vu_char *) (CFG_MBAR+0x10001D))
#define MCFGPIO_DDREH (*(vu_char *) (CFG_MBAR+0x10001E))
#define MCFGPIO_DDREL (*(vu_char *) (CFG_MBAR+0x10001F))
#define MCFGPIO_DDRAS (*(vu_char *) (CFG_MBAR+0x100020))
#define MCFGPIO_DDRQS (*(vu_char *) (CFG_MBAR+0x100021))
#define MCFGPIO_DDRSD (*(vu_char *) (CFG_MBAR+0x100022))
#define MCFGPIO_DDRTC (*(vu_char *) (CFG_MBAR+0x100023))
#define MCFGPIO_DDRTD (*(vu_char *) (CFG_MBAR+0x100024))
#define MCFGPIO_DDRUA (*(vu_char *) (CFG_MBAR+0x100025))
#define MCF5282_GPIO_PUAPAR 0x10005C
#define MCFGPIO_PORTAP (*(vu_char *) (CFG_MBAR+0x100028))
#define MCFGPIO_PORTBP (*(vu_char *) (CFG_MBAR+0x100029))
#define MCFGPIO_PORTCP (*(vu_char *) (CFG_MBAR+0x10002A))
#define MCFGPIO_PORTDP (*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_PORTEP (*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_PORTFP (*(vu_char *) (CFG_MBAR+0x10002D))
#define MCFGPIO_PORTGP (*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_PORTHP (*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_PORTJP (*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_PORTELP (*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_PORTASP (*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_MBAR+0x100039))
#define MCFGPIO_SETA (*(vu_char *) (CFG_MBAR+0x100028))
#define MCFGPIO_SETB (*(vu_char *) (CFG_MBAR+0x100029))
#define MCFGPIO_SETC (*(vu_char *) (CFG_MBAR+0x10002A))
#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B))
#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C))
#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D))
#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
/* Bit level definitions and macros */
#define MCFGPIO_PORT7 (0x80)
#define MCFGPIO_PORT6 (0x40)
#define MCFGPIO_PORT5 (0x20)
#define MCFGPIO_PORT4 (0x10)
#define MCFGPIO_PORT3 (0x08)
#define MCFGPIO_PORT2 (0x04)
#define MCFGPIO_PORT1 (0x02)
#define MCFGPIO_PORT0 (0x01)
#define MCFGPIO_PORT(x) (0x01<<x)
#define MCFGPIO_DDR7 (0x80)
#define MCFGPIO_DDR6 (0x40)
#define MCFGPIO_DDR5 (0x20)
#define MCFGPIO_DDR4 (0x10)
#define MCFGPIO_DDR3 (0x08)
#define MCFGPIO_DDR2 (0x04)
#define MCFGPIO_DDR1 (0x02)
#define MCFGPIO_DDR0 (0x01)
#define MCFGPIO_DDR(x) (0x01<<x)
#define MCFGPIO_Px7 (0x80)
#define MCFGPIO_Px6 (0x40)
#define MCFGPIO_Px5 (0x20)
#define MCFGPIO_Px4 (0x10)
#define MCFGPIO_Px3 (0x08)
#define MCFGPIO_Px2 (0x04)
#define MCFGPIO_Px1 (0x02)
#define MCFGPIO_Px0 (0x01)
#define MCFGPIO_Px(x) (0x01<<x)
#define MCFGPIO_PBCDPAR_PBPA (0x80)
#define MCFGPIO_PBCDPAR_PCDPA (0x40)
#define MCFGPIO_PEPAR_PEPA7 (0x4000)
#define MCFGPIO_PEPAR_PEPA6 (0x1000)
#define MCFGPIO_PEPAR_PEPA5 (0x0400)
#define MCFGPIO_PEPAR_PEPA4 (0x0100)
#define MCFGPIO_PEPAR_PEPA3 (0x0040)
#define MCFGPIO_PEPAR_PEPA2 (0x0010)
#define MCFGPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PEPAR_PEPA0(x) (((x)&0x3))
#define MCFGPIO_PFPAR_PFPA7 (0x80)
#define MCFGPIO_PFPAR_PFPA6 (0x40)
#define MCFGPIO_PFPAR_PFPA5 (0x20)
#define MCFGPIO_PJPAR_PJPA7 (0x80)
#define MCFGPIO_PJPAR_PJPA6 (0x40)
#define MCFGPIO_PJPAR_PJPA5 (0x20)
#define MCFGPIO_PJPAR_PJPA4 (0x10)
#define MCFGPIO_PJPAR_PJPA3 (0x08)
#define MCFGPIO_PJPAR_PJPA2 (0x04)
#define MCFGPIO_PJPAR_PJPA1 (0x02)
#define MCFGPIO_PJPAR_PJPA0 (0x01)
#define MCFGPIO_PJPAR_PJPA(x) (0x01<<x)
#define MCFGPIO_PSDPAR_PSDPA (0x80)
#define MCFGPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10)
#define MCFGPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8)
#define MCFGPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6)
#define MCFGPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4)
#define MCFGPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PASPAR_PASPA0(x) (((x)&0x3))
#define MCFGPIO_PEHLPAR_PEHPA (0x80)
#define MCFGPIO_PEHLPAR_PELPA (0x40)
#define MCFGPIO_PQSPAR_PQSPA6 (0x40)
#define MCFGPIO_PQSPAR_PQSPA5 (0x20)
#define MCFGPIO_PQSPAR_PQSPA4 (0x10)
#define MCFGPIO_PQSPAR_PQSPA3 (0x08)
#define MCFGPIO_PQSPAR_PQSPA2 (0x04)
#define MCFGPIO_PQSPAR_PQSPA1 (0x02)
#define MCFGPIO_PQSPAR_PQSPA0 (0x01)
#define MCFGPIO_PQSPAR_PQSPA(x) (0x01<<x)
#define MCFGPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6)
#define MCFGPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4)
#define MCFGPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PTCPAR_PTCPA0(x) (((x)&0x3))
#define MCFGPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6)
#define MCFGPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4)
#define MCFGPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2)
#define MCFGPIO_PTDPAR_PTDPA0(x) (((x)&0x3))
#define MCFGPIO_PUAPAR_PUAPA3 (0x08)
#define MCFGPIO_PUAPAR_PUAPA2 (0x04)
#define MCFGPIO_PUAPAR_PUAPA1 (0x02)
#define MCFGPIO_PUAPAR_PUAPA0 (0x01)
/* System Conrol Module SCM */
#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010))
#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011))
#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012))
#define MCFSCM_CWSR (*(vu_char *) (CFG_MBAR+0x00000013))
#define MCFSCM_MPARK (*(vu_long *) (CFG_MBAR+0x0000001C))
#define MCFSCM_MPR (*(vu_char *) (CFG_MBAR+0x00000020))
#define MCFSCM_PACR0 (*(vu_char *) (CFG_MBAR+0x00000024))
#define MCFSCM_PACR1 (*(vu_char *) (CFG_MBAR+0x00000025))
#define MCFSCM_PACR2 (*(vu_char *) (CFG_MBAR+0x00000026))
#define MCFSCM_PACR3 (*(vu_char *) (CFG_MBAR+0x00000027))
#define MCFSCM_PACR4 (*(vu_char *) (CFG_MBAR+0x00000028))
#define MCFSCM_PACR5 (*(vu_char *) (CFG_MBAR+0x0000002A))
#define MCFSCM_PACR6 (*(vu_char *) (CFG_MBAR+0x0000002B))
#define MCFSCM_PACR7 (*(vu_char *) (CFG_MBAR+0x0000002C))
#define MCFSCM_PACR8 (*(vu_char *) (CFG_MBAR+0x0000002E))
#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030))
#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031))
#define MCFSCM_CRSR_EXT (0x80)
#define MCFSCM_CRSR_CWDR (0x20)
#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
#define MCFSCM_RAMBAR_BDE (0x00000200)
/* Reset Controller Module RCM */
#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000))
#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001))
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
#define MCFRESET_RCR_LVDF (0x10)
#define MCFRESET_RCR_LVDIE (0x08)
#define MCFRESET_RCR_LVDRE (0x04)
#define MCFRESET_RCR_LVDE (0x01)
#define MCFRESET_RSR_LVD (0x40)
#define MCFRESET_RSR_SOFT (0x20)
#define MCFRESET_RSR_WDR (0x10)
#define MCFRESET_RSR_POR (0x08)
#define MCFRESET_RSR_EXT (0x04)
#define MCFRESET_RSR_LOC (0x02)
#define MCFRESET_RSR_LOL (0x01)
#define MCFRESET_RSR_ALL (0x7F)
#define MCFRESET_RCR_SOFTRST (0x80)
#define MCFRESET_RCR_FRCRSTOUT (0x40)
/* Chip Configuration Module CCM */
#define MCFCCM_CCR (*(vu_short *)(CFG_MBAR+0x00110004))
#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008))
#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
/* Bit level definitions and macros */
#define MCFCCM_CCR_LOAD (0x8000)
#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
#define MCFCCM_CCR_SZEN (0x0040)
#define MCFCCM_CCR_PSTEN (0x0020)
#define MCFCCM_CCR_BME (0x0008)
#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
#define MCFCCM_CIR_PIN_MASK (0xFF00)
#define MCFCCM_CIR_PRN_MASK (0x00FF)
/* Clock Module */
#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
#define MCFCLOCK_SYNSR_LOCK 0x08
#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040))
#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048))
#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_MBAR+0x0000004c))
#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_MBAR+0x00000050))
#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_MBAR+0x00000054))
#define MCFSDRAMC_DCR_NAM (0x2000)
#define MCFSDRAMC_DCR_COC (0x1000)
#define MCFSDRAMC_DCR_IS (0x0800)
#define MCFSDRAMC_DCR_RTIM_3 (0x0000)
#define MCFSDRAMC_DCR_RTIM_6 (0x0200)
#define MCFSDRAMC_DCR_RTIM_9 (0x0400)
#define MCFSDRAMC_DCR_RC(x) ((x)&0x01FF)
#define MCFSDRAMC_DACR_BASE(x) ((x)&0xFFFC0000)
#define MCFSDRAMC_DACR_RE (0x00008000)
#define MCFSDRAMC_DACR_CASL(x) (((x)&0x03)<<12)
#define MCFSDRAMC_DACR_CBM(x) (((x)&0x07)<<8)
#define MCFSDRAMC_DACR_PS_32 (0x00000000)
#define MCFSDRAMC_DACR_PS_16 (0x00000020)
#define MCFSDRAMC_DACR_PS_8 (0x00000010)
#define MCFSDRAMC_DACR_IP (0x00000008)
#define MCFSDRAMC_DACR_IMRS (0x00000040)
#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000)
#define MCFSDRAMC_DMR_WP (0x00000100)
#define MCFSDRAMC_DMR_CI (0x00000040)
#define MCFSDRAMC_DMR_AM (0x00000020)
#define MCFSDRAMC_DMR_SC (0x00000010)
#define MCFSDRAMC_DMR_SD (0x00000008)
#define MCFSDRAMC_DMR_UC (0x00000004)
#define MCFSDRAMC_DMR_UD (0x00000002)
#define MCFSDRAMC_DMR_V (0x00000001)
#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
/* Chip SELECT Module CSM */
#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080))
#define MCFCSM_CSMR0 (*(vu_long *) (CFG_MBAR+0x00000084))
#define MCFCSM_CSCR0 (*(vu_short *)(CFG_MBAR+0x0000008a))
#define MCFCSM_CSAR1 (*(vu_short *)(CFG_MBAR+0x0000008C))
#define MCFCSM_CSMR1 (*(vu_long *) (CFG_MBAR+0x00000090))
#define MCFCSM_CSCR1 (*(vu_short *)(CFG_MBAR+0x00000096))
#define MCFCSM_CSAR2 (*(vu_short *)(CFG_MBAR+0x00000098))
#define MCFCSM_CSMR2 (*(vu_long *) (CFG_MBAR+0x0000009C))
#define MCFCSM_CSCR2 (*(vu_short *)(CFG_MBAR+0x000000A2))
#define MCFCSM_CSAR3 (*(vu_short *)(CFG_MBAR+0x000000A4))
#define MCFCSM_CSMR3 (*(vu_long *) (CFG_MBAR+0x000000A8))
#define MCFCSM_CSCR3 (*(vu_short *)(CFG_MBAR+0x000000AE))
#define MCFCSM_CSMR_BAM(x) ((x) & 0xFFFF0000)
#define MCFCSM_CSMR_WP (1<<8)
#define MCFCSM_CSMR_V (0x01)
#define MCFCSM_CSCR_WS(x) ((x & 0x0F)<<10)
#define MCFCSM_CSCR_AA (0x0100)
#define MCFCSM_CSCR_PS_32 (0x0000)
#define MCFCSM_CSCR_PS_8 (0x0040)
#define MCFCSM_CSCR_PS_16 (0x0080)
/*********************************************************************
*
* General Purpose Timer (GPT) Module
*
*********************************************************************/
#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000))
#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1A0001))
#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1A0002))
#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1A0003))
#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_MBAR+0x1A0004))
#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1A0006))
#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_MBAR+0x1A0008))
#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1A0009))
#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1A000B))
#define MCFGPTA_GPTIE (*(vu_char *)(CFG_MBAR+0x1A000C))
#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1A000D))
#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1A000E))
#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1A000F))
#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_MBAR+0x1A0010))
#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_MBAR+0x1A0012))
#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_MBAR+0x1A0014))
#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_MBAR+0x1A0016))
#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1A0018))
#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1A0019))
#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1A001A))
#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D))
#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E))
#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000))
#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001))
#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002))
#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1B0003))
#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_MBAR+0x1B0004))
#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1B0006))
#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_MBAR+0x1B0008))
#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1B0009))
#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1B000B))
#define MCFGPTB_GPTIE (*(vu_char *)(CFG_MBAR+0x1B000C))
#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1B000D))
#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1B000E))
#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1B000F))
#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_MBAR+0x1B0010))
#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_MBAR+0x1B0012))
#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_MBAR+0x1B0014))
#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_MBAR+0x1B0016))
#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1B0018))
#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1B0019))
#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1B001A))
#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_MBAR+0x1B001D))
#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_MBAR+0x1B001E))
/* Bit level definitions and macros */
#define MCFGPT_GPTIOS_IOS3 (0x08)
#define MCFGPT_GPTIOS_IOS2 (0x04)
#define MCFGPT_GPTIOS_IOS1 (0x02)
#define MCFGPT_GPTIOS_IOS0 (0x01)
#define MCFGPT_GPTCFORC_FOC3 (0x08)
#define MCFGPT_GPTCFORC_FOC2 (0x04)
#define MCFGPT_GPTCFORC_FOC1 (0x02)
#define MCFGPT_GPTCFORC_FOC0 (0x01)
#define MCFGPT_GPTOC3M_OC3M3 (0x08)
#define MCFGPT_GPTOC3M_OC3M2 (0x04)
#define MCFGPT_GPTOC3M_OC3M1 (0x02)
#define MCFGPT_GPTOC3M_OC3M0 (0x01)
#define MCFGPT_GPTOC3M_OC3D(x) (((x)&0x04))
#define MCFGPT_GPTSCR1_GPTEN (0x80)
#define MCFGPT_GPTSCR1_TFFCA (0x10)
#define MCFGPT_GPTTOV3 (0x08)
#define MCFGPT_GPTTOV2 (0x04)
#define MCFGPT_GPTTOV1 (0x02)
#define MCFGPT_GPTTOV0 (0x01)
#define MCFGPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6)
#define MCFGPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4)
#define MCFGPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2)
#define MCFGPT_GPTCTL_OMOL0(x) (((x)&0x03))
#define MCFGPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6)
#define MCFGPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4)
#define MCFGPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2)
#define MCFGPT_GPTCTL2_EDG0(x) (((x)&0x03))
#define MCFGPT_GPTIE_C3I (0x08)
#define MCFGPT_GPTIE_C2I (0x04)
#define MCFGPT_GPTIE_C1I (0x02)
#define MCFGPT_GPTIE_C0I (0x01)
#define MCFGPT_GPTSCR2_TOI (0x80)
#define MCFGPT_GPTSCR2_PUPT (0x20)
#define MCFGPT_GPTSCR2_RDPT (0x10)
#define MCFGPT_GPTSCR2_TCRE (0x08)
#define MCFGPT_GPTSCR2_PR(x) (((x)&0x07))
#define MCFGPT_GPTFLG1_C3F (0x08)
#define MCFGPT_GPTFLG1_C2F (0x04)
#define MCFGPT_GPTFLG1_C1F (0x02)
#define MCFGPT_GPTFLG1_C0F (0x01)
#define MCFGPT_GPTFLG2_TOF (0x80)
#define MCFGPT_GPTFLG2_C3F (0x08)
#define MCFGPT_GPTFLG2_C2F (0x04)
#define MCFGPT_GPTFLG2_C1F (0x02)
#define MCFGPT_GPTFLG2_C0F (0x01)
#define MCFGPT_GPTPACTL_PAE (0x40)
#define MCFGPT_GPTPACTL_PAMOD (0x20)
#define MCFGPT_GPTPACTL_PEDGE (0x10)
#define MCFGPT_GPTPACTL_CLK_PACLK (0x04)
#define MCFGPT_GPTPACTL_CLK_PACLK256 (0x08)
#define MCFGPT_GPTPACTL_CLK_PACLK65536 (0x0C)
#define MCFGPT_GPTPACTL_CLK(x) (((x)&0x03)<<2)
#define MCFGPT_GPTPACTL_PAOVI (0x02)
#define MCFGPT_GPTPACTL_PAI (0x01)
#define MCFGPT_GPTPAFLG_PAOVF (0x02)
#define MCFGPT_GPTPAFLG_PAIF (0x01)
#define MCFGPT_GPTPORT_PORTT3 (0x08)
#define MCFGPT_GPTPORT_PORTT2 (0x04)
#define MCFGPT_GPTPORT_PORTT1 (0x02)
#define MCFGPT_GPTPORT_PORTT0 (0x01)
#define MCFGPT_GPTDDR_DDRT3 (0x08)
#define MCFGPT_GPTDDR_DDRT2 (0x04)
#define MCFGPT_GPTDDR_DDRT1 (0x02)
#define MCFGPT_GPTDDR_DDRT0 (0x01)
/* Coldfire Flash Module CFM */
#define MCFCFM_MCR (*(vu_short *)(CFG_MBAR+0x1D0000))
#define MCFCFM_MCR_LOCK (0x0400)
#define MCFCFM_MCR_PVIE (0x0200)
#define MCFCFM_MCR_AEIE (0x0100)
#define MCFCFM_MCR_CBEIE (0x0080)
#define MCFCFM_MCR_CCIE (0x0040)
#define MCFCFM_MCR_KEYACC (0x0020)
#define MCFCFM_CLKD (*(vu_char *)(CFG_MBAR+0x1D0002))
#define MCFCFM_SEC (*(vu_long*) (CFG_MBAR+0x1D0008))
#define MCFCFM_SEC_KEYEN (0x80000000)
#define MCFCFM_SEC_SECSTAT (0x40000000)
#define MCFCFM_PROT (*(vu_long*) (CFG_MBAR+0x1D0010))
#define MCFCFM_SACC (*(vu_long*) (CFG_MBAR+0x1D0014))
#define MCFCFM_DACC (*(vu_long*) (CFG_MBAR+0x1D0018))
#define MCFCFM_USTAT (*(vu_char*) (CFG_MBAR+0x1D0020))
#define MCFCFM_USTAT_CBEIF 0x80
#define MCFCFM_USTAT_CCIF 0x40
#define MCFCFM_USTAT_PVIOL 0x20
#define MCFCFM_USTAT_ACCERR 0x10
#define MCFCFM_USTAT_BLANK 0x04
#define MCFCFM_CMD (*(vu_char*) (CFG_MBAR+0x1D0024))
#define MCFCFM_CMD_ERSVER 0x05
#define MCFCFM_CMD_PGERSVER 0x06
#define MCFCFM_CMD_PGM 0x20
#define MCFCFM_CMD_PGERS 0x40
#define MCFCFM_CMD_MASERS 0x41
/****************************************************************************/
#endif /* m5282_h */

5
include/asm-mips/au1x00.h
View File

@@ -119,6 +119,11 @@ static __inline__ int au_ffs(int x)
return __ilog2(x & -x) + 1;
}
#define gpio_set(Value) outl(Value, SYS_OUTPUTSET)
#define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR)
#define gpio_read() inl(SYS_PINSTATERD)
#define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR)
#endif /* !ASSEMBLY */
#ifdef CONFIG_PM

7
include/asm-nios2/io.h
View File

@@ -39,12 +39,13 @@ extern unsigned inl (unsigned port);
#define readl(addr)\
({unsigned long val;\
asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
#define writeb(addr,val)\
asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val))
asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val))
#define writew(addr,val)\
asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val))
asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val))
#define writel(addr,val)\
asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val))
asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val))
#define inb(addr) readb(addr)
#define inw(addr) readw(addr)

41
include/asm-ppc/mmu.h
View File

@@ -483,4 +483,45 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
#ifdef CONFIG_440SPE
/*----------------------------------------------------------------------------+
| Following instructions are not available in Book E mode of the GNU assembler.
+----------------------------------------------------------------------------*/
#define DCCCI(ra,rb) .long 0x7c000000|\
(ra<<16)|(rb<<11)|(454<<1)
#define ICCCI(ra,rb) .long 0x7c000000|\
(ra<<16)|(rb<<11)|(966<<1)
#define DCREAD(rt,ra,rb) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
#define ICREAD(ra,rb) .long 0x7c000000|\
(ra<<16)|(rb<<11)|(998<<1)
#define TLBSX(rt,ra,rb) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
#define TLBWE(rs,ra,ws) .long 0x7c000000|\
(rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
#define TLBRE(rt,ra,ws) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
(rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
#define MSYNC .long 0x7c000000|\
(598<<1)
#define MBAR_INST .long 0x7c000000|\
(854<<1)
/*----------------------------------------------------------------------------+
| Following instruction is not available in PPC405 mode of the GNU assembler.
+----------------------------------------------------------------------------*/
#define TLBRE(rt,ra,ws) .long 0x7c000000|\
(rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
#endif
#endif /* _PPC_MMU_H_ */

2
include/asm-ppc/processor.h
View File

@@ -745,6 +745,8 @@
#define PVR_405EP_RB 0x51210950
#define PVR_440SP_RA 0x53221850
#define PVR_440SP_RB 0x53221891
#define PVR_440SPe_RA 0x53421890
#define PVR_440SPe_RB 0x53421891
#define PVR_601 0x00010000
#define PVR_602 0x00050000
#define PVR_603 0x00030000

1948
include/bmp_logo.h
View File

File diff suppressed because it is too large Load Diff

9
include/common.h
View File

@@ -120,12 +120,13 @@ typedef void (interrupt_handler_t)(void *);
/*
* enable common handling for all TQM8xxL/M boards:
* - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
* - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards
* - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
*/
#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \
defined(CONFIG_TQM885D)
# ifndef CONFIG_TQM8xxM
# define CONFIG_TQM8xxM
# endif
@@ -470,6 +471,10 @@ void get_sys_info ( sys_info_t * );
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
typedef PPC440_SYS_INFO sys_info_t;
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
# endif
# else
typedef PPC405_SYS_INFO sys_info_t;
# endif

12
include/commproc.h
View File

@@ -1405,15 +1405,16 @@ typedef struct scc_enet {
#endif /* CONFIG_SXNI855T */
/*** MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI *******************/
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \
defined(CONFIG_VIRTLAB2)|| \
defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \
defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
@@ -1438,6 +1439,11 @@ typedef struct scc_enet {
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
#define FEC_ENET
# endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/

24
include/configs/CPU87.h
View File

@@ -455,7 +455,7 @@
#define CFG_MIN_AM_MASK 0xC0000000
/*
* we use the same values for 32 MB and 128 MB SDRAM
* we use the same values for 32 MB, 128 MB and 256 MB SDRAM
* refresh rate = 7.68 uS (100 MHz Bus Clock)
*/
@@ -510,6 +510,24 @@
PSDMR_WRC_1C |\
PSDMR_CL_2)
/* SDRAM initialization values for 10-column chips
*/
#define CFG_OR2_10COL (CFG_MIN_AM_MASK |\
ORxS_BPD_4 |\
ORxS_ROWST_PBI1_A4 |\
ORxS_NUMR_13)
#define CFG_PSDMR_10COL (PSDMR_PBI |\
PSDMR_SDAM_A17_IS_A5 |\
PSDMR_BSMA_A13_A15 |\
PSDMR_SDA10_PBI1_A6 |\
PSDMR_RFRC_7_CLK |\
PSDMR_PRETOACT_2W |\
PSDMR_ACTTORW_2W |\
PSDMR_LDOTOPRE_1C |\
PSDMR_WRC_1C |\
PSDMR_CL_2)
/*
* Init Memory Controller:
*
@@ -588,9 +606,9 @@
BRx_MS_SDRAM_P |\
BRx_V)
#define CFG_OR2_PRELIM CFG_OR2_9COL
#define CFG_OR2_PRELIM CFG_OR2_8COL
#define CFG_PSDMR CFG_PSDMR_9COL
#define CFG_PSDMR CFG_PSDMR_8COL
#endif /* CFG_RAMBOOT */
/* Bank 3 - Dual Ported SRAM

223
include/configs/EB+MCF-EV123.h Normal file
View File

@@ -0,0 +1,223 @@
/*
* Configuation settings for the BuS EB+MCF-EV123 boards.
*
* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _CONFIG_EB_MCF_EV123_H_
#define _CONFIG_EB_MCF_EV123_H_
#define CONFIG_EB_MCF_EV123
#undef DEBUG
#undef CFG_HALT_BEFOR_RAM_JUMP
#undef ET_DEBUG
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5282 /* define processor type */
#define CONFIG_MISC_INIT_R
#define FEC_ENET
#define CONFIG_ETHADDR 00:CF:52:82:EB:01
#define CONFIG_BAUDRATE 9600
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
#define CONFIG_BOOTCOMMAND "printenv"
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CFG_ENV_ADDR 0xF003C000 /* End of 256K */
#define CFG_ENV_SECT_SIZE 0x4000
#define CFG_ENV_IS_IN_FLASH 1
/*
#define CFG_ENV_IS_EMBEDDED 1
#define CFG_ENV_ADDR_REDUND 0xF0018000
#define CFG_ENV_SECT_SIZE_REDUND 0x4000
*/
#else
#define CFG_ENV_ADDR 0xFFE04000
#define CFG_ENV_SECT_SIZE 0x2000
#define CFG_ENV_IS_IN_FLASH 1
#endif
/*#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB))
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5
#define CFG_PROMPT "\nEV123 U-Boot> "
#define CFG_LONGHELP /* undef to save memory */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x20000
#define CFG_MEMTEST_START 0x100000
#define CFG_MEMTEST_END 0x400000
/*#define CFG_DRAM_TEST 1 */
#undef CFG_DRAM_TEST
/* Clock and PLL Configuration */
#define CFG_HZ 10000000
#define CFG_CLK 58982400 /* 9,8304MHz * 6 */
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
#define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */
#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CFG_MBAR 0x40000000
#define CFG_DISCOVER_PHY
/* #define CFG_ENET_BD_BASE 0x380000 */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR 0x20000000
#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE1 0x00000000
#define CFG_SDRAM_SIZE1 16 /* SDRAM size in MB */
/*
#define CFG_SDRAM_BASE0 CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024
#define CFG_SDRAM_SIZE0 16 */ /* SDRAM size in MB */
#define CFG_SDRAM_BASE CFG_SDRAM_BASE1
#define CFG_SDRAM_SIZE CFG_SDRAM_SIZE1
#define CFG_FLASH_BASE 0xFFE00000
#define CFG_INT_FLASH_BASE 0xF0000000
/* If M5282 port is fully implemented the monitor base will be behind
* the vector table. */
#if (TEXT_BASE != CFG_INT_FLASH_BASE)
#define CFG_MONITOR_BASE (TEXT_BASE + 0x400)
#else
#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
#endif
#define CFG_MONITOR_LEN 0x20000
#define CFG_MALLOC_LEN (256 << 10)
#define CFG_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_SECT 35
#define CFG_MAX_FLASH_BANKS 2
#define CFG_FLASH_ERASE_TOUT 10000000
#define CFG_FLASH_PROTECTION
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CFG_CS0_BASE CFG_FLASH_BASE
#define CFG_CS0_SIZE 2*1024*1024
#define CFG_CS0_WIDTH 16
#define CFG_CS0_RO 0
#define CFG_CS0_WS 6
#define CFG_CS3_BASE 0xE0000000
#define CFG_CS3_SIZE 1*1024*1024
#define CFG_CS3_WIDTH 16
#define CFG_CS3_RO 0
#define CFG_CS3_WS 6
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CFG_PACNT 0x0000000 /* Port A D[31:24] */
#define CFG_PADDR 0x0000000
#define CFG_PADAT 0x0000000
#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
#define CFG_PBDDR 0x0000000
#define CFG_PBDAT 0x0000000
#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
#define CFG_PCDDR 0x0000000
#define CFG_PCDAT 0x0000000
#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
#define CFG_PCDDR 0x0000000
#define CFG_PCDAT 0x0000000
#define CFG_PEHLPAR 0xC0
#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
#define CFG_DDRUA 0x05
#define CFG_PJPAR 0xFF;
/*-----------------------------------------------------------------------
* CCM configuration
*/
#define CFG_CCM_SIZ 0
/*---------------------------------------------------------------------*/
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/

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/*
* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*------------------------------------------------------------------------
* BOARD/CPU
*----------------------------------------------------------------------*/
#define CONFIG_EP1C20 1 /* EP1C20 board */
#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
* CACHE -- the following will support II/s and II/f. The II/s does not
* have dcache, so the cache instructions will behave as NOPs.
*----------------------------------------------------------------------*/
#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */
#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */
#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
/*------------------------------------------------------------------------
* MEMORY BASE ADDRESSES
*----------------------------------------------------------------------*/
#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */
#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
/*------------------------------------------------------------------------
* MEMORY ORGANIZATION
* -Monitor at top.
* -The heap is placed below the monitor.
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
* FLASH (AM29LV065D)
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
/*------------------------------------------------------------------------
* ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
* CFG_RESET_ADDR, since we assume the monitor is stored at the
* reset address, no? This will keep the environment in user region
* of flash. NOTE: the monitor length must be multiple of sector size
* (which is common practice).
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN)
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */
#endif
#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
/*------------------------------------------------------------------------
* EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
* epcs device access is enabled. The base address is the epcs
* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
* The register base is currently at offset 0x600 from the memory base.
*----------------------------------------------------------------------*/
#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
/*------------------------------------------------------------------------
* DEBUG
*----------------------------------------------------------------------*/
#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
/*------------------------------------------------------------------------
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
* registers, we can slow it down to 10 msec using TMRCNT. If the default
* period is acceptable, TMRCNT can be left undefined.
*----------------------------------------------------------------------*/
#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
* must implement its own led routines -- leds are, after all,
* board-specific, no?
*----------------------------------------------------------------------*/
#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
#define CONFIG_STATUS_LED /* Enable status driver */
#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
#define STATUS_LED_STATE 1 /* Blinking */
#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */
/*------------------------------------------------------------------------
* ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
* and really doesn't need any additional clutter. So I choose the lazy
* way out to avoid changes there -- define the base address to ensure
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
/*------------------------------------------------------------------------
* COMMANDS
*----------------------------------------------------------------------*/
#define CONFIG_COMMANDS (CFG_CMD_BDI | \
CFG_CMD_DHCP | \
CFG_CMD_ECHO | \
CFG_CMD_ENV | \
CFG_CMD_FLASH | \
CFG_CMD_IMI | \
CFG_CMD_IRQ | \
CFG_CMD_LOADS | \
CFG_CMD_LOADB | \
CFG_CMD_MEMORY | \
CFG_CMD_MISC | \
CFG_CMD_NET | \
CFG_CMD_PING | \
CFG_CMD_RUN | \
CFG_CMD_SAVES )
#include <cmd_confdefs.h>
/*------------------------------------------------------------------------
* MISC
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* Provide extended help*/
#define CFG_PROMPT "==> " /* Command prompt */
#define CFG_CBSIZE 256 /* Console I/O buf size */
#define CFG_MAXARGS 16 /* Max command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */
#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */
#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*------------------------------------------------------------------------
* BOARD/CPU
*----------------------------------------------------------------------*/
#define CONFIG_EP1S10 1 /* EP1S10 board */
#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */
/*------------------------------------------------------------------------
* CACHE -- the following will support II/s and II/f. The II/s does not
* have dcache, so the cache instructions will behave as NOPs.
*----------------------------------------------------------------------*/
#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */
#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */
#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
/*------------------------------------------------------------------------
* MEMORY BASE ADDRESSES
*----------------------------------------------------------------------*/
#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */
#define CFG_SRAM_SIZE 0x00100000 /* 1 MB */
/*------------------------------------------------------------------------
* MEMORY ORGANIZATION
* -Monitor at top.
* -The heap is placed below the monitor.
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) /* 256k heap */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
* FLASH (AM29LV065D)
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
/*------------------------------------------------------------------------
* ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
* CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
* of flash memory. This will keep the environment in user region
* of flash. NOTE: the monitor length must be multiple of sector size
* (which is common practice).
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */
#endif
#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
/*------------------------------------------------------------------------
* EPCS Device -- None for stratix.
*----------------------------------------------------------------------*/
#undef CFG_NIOS_EPCSBASE
/*------------------------------------------------------------------------
* DEBUG
*----------------------------------------------------------------------*/
#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
/*------------------------------------------------------------------------
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
* registers, we can slow it down to 10 msec using TMRCNT. If the default
* period is acceptable, TMRCNT can be left undefined.
*----------------------------------------------------------------------*/
#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
* must implement its own led routines -- since leds are board-specific.
*----------------------------------------------------------------------*/
#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
#define CONFIG_STATUS_LED /* Enable status driver */
#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
#define STATUS_LED_STATE 1 /* Blinking */
#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */
/*------------------------------------------------------------------------
* ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
* and really doesn't need any additional clutter. So I choose the lazy
* way out to avoid changes there -- define the base address to ensure
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
/*------------------------------------------------------------------------
* COMMANDS
*----------------------------------------------------------------------*/
#define CONFIG_COMMANDS (CFG_CMD_BDI | \
CFG_CMD_DHCP | \
CFG_CMD_ECHO | \
CFG_CMD_ENV | \
CFG_CMD_FLASH | \
CFG_CMD_IMI | \
CFG_CMD_IRQ | \
CFG_CMD_LOADS | \
CFG_CMD_LOADB | \
CFG_CMD_MEMORY | \
CFG_CMD_MISC | \
CFG_CMD_NET | \
CFG_CMD_PING | \
CFG_CMD_RUN | \
CFG_CMD_SAVES )
#include <cmd_confdefs.h>
/*------------------------------------------------------------------------
* MISC
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* Provide extended help*/
#define CFG_PROMPT "==> " /* Command prompt */
#define CFG_CBSIZE 256 /* Console I/O buf size */
#define CFG_MAXARGS 16 /* Max command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */
#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */
#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif /* __CONFIG_H */

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/*
* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*------------------------------------------------------------------------
* BOARD/CPU
*----------------------------------------------------------------------*/
#define CONFIG_EP1S40 1 /* EP1S40 board */
#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */
/*------------------------------------------------------------------------
* CACHE -- the following will support II/s and II/f. The II/s does not
* have dcache, so the cache instructions will behave as NOPs.
*----------------------------------------------------------------------*/
#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */
#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */
#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
/*------------------------------------------------------------------------
* MEMORY BASE ADDRESSES
*----------------------------------------------------------------------*/
#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */
#define CFG_SRAM_SIZE 0x00100000 /* 1 MB */
/*------------------------------------------------------------------------
* MEMORY ORGANIZATION
* -Monitor at top.
* -The heap is placed below the monitor.
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) /* 256k heap */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
* FLASH (AM29LV065D)
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
/*------------------------------------------------------------------------
* ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above
* CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom
* of flash memory. This will keep the environment in user region
* of flash. NOTE: the monitor length must be multiple of sector size
* (which is common practice).
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */
#endif
#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
/*------------------------------------------------------------------------
* EPCS Device -- None for stratix.
*----------------------------------------------------------------------*/
#undef CFG_NIOS_EPCSBASE
/*------------------------------------------------------------------------
* DEBUG
*----------------------------------------------------------------------*/
#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
/*------------------------------------------------------------------------
* TIMEBASE --
*
* The high res timer defaults to 1 msec. Since it includes the period
* registers, we can slow it down to 10 msec using TMRCNT. If the default
* period is acceptable, TMRCNT can be left undefined.
*----------------------------------------------------------------------*/
#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1))
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
* must implement its own led routines -- since leds are board-specific.
*----------------------------------------------------------------------*/
#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
#define CONFIG_STATUS_LED /* Enable status driver */
#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
#define STATUS_LED_STATE 1 /* Blinking */
#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */
/*------------------------------------------------------------------------
* ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
* and really doesn't need any additional clutter. So I choose the lazy
* way out to avoid changes there -- define the base address to ensure
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
/*------------------------------------------------------------------------
* COMMANDS
*----------------------------------------------------------------------*/
#define CONFIG_COMMANDS (CFG_CMD_BDI | \
CFG_CMD_DHCP | \
CFG_CMD_ECHO | \
CFG_CMD_ENV | \
CFG_CMD_FLASH | \
CFG_CMD_IMI | \
CFG_CMD_IRQ | \
CFG_CMD_LOADS | \
CFG_CMD_LOADB | \
CFG_CMD_MEMORY | \
CFG_CMD_MISC | \
CFG_CMD_NET | \
CFG_CMD_PING | \
CFG_CMD_RUN | \
CFG_CMD_SAVES )
#include <cmd_confdefs.h>
/*------------------------------------------------------------------------
* MISC
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* Provide extended help*/
#define CFG_PROMPT "==> " /* Command prompt */
#define CFG_CBSIZE 256 /* Console I/O buf size */
#define CFG_MAXARGS 16 /* Max command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */
#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */
#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */
#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif /* __CONFIG_H */

20
include/configs/PK1C20.h
View File

@@ -32,7 +32,7 @@
#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */
#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
@@ -51,7 +51,7 @@
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
#define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */
#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */
#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
/*------------------------------------------------------------------------
@@ -61,7 +61,7 @@
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
@@ -95,9 +95,9 @@
* CONSOLE
*----------------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */
#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */
#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */
#endif
#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
@@ -110,9 +110,9 @@
* EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
* epcs device access is enabled. The base address is the epcs
* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
* The register base is currently at offset 0x400 from the memory base.
* The register base is currently at offset 0x600 from the memory base.
*----------------------------------------------------------------------*/
#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */
#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
/*------------------------------------------------------------------------
* DEBUG
@@ -126,7 +126,7 @@
* registers, we can slow it down to 10 msec using TMRCNT. If the default
* period is acceptable, TMRCNT can be left undefined.
*----------------------------------------------------------------------*/
#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */
#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
@@ -137,7 +137,7 @@
* must implement its own led routines -- leds are, after all,
* board-specific, no?
*----------------------------------------------------------------------*/
#define CFG_LEDPIO_ADDR 0x00920840 /* LED PIO base addr */
#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
#define CONFIG_STATUS_LED /* Enable status driver */
#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
@@ -150,7 +150,7 @@
* way out to avoid changes there -- define the base address to ensure
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
#define CONFIG_SMC91111_BASE 0x80910300 /* Base addr (bypass) */
#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */

507
include/configs/TB5200.h Normal file
View File

@@ -0,0 +1,507 @@
/*
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2006
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#define CONFIG_TB5200 1 /* ... on a TB5200 base board */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */
#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/*
* Video console
*/
#if 1
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#define CONFIG_VIDEO_SM501_32BPP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CFG_CONSOLE_IS_IN_ENV
#endif
#ifdef CONFIG_VIDEO
#define ADD_BMP_CMD CFG_CMD_BMP
#else
#define ADD_BMP_CMD 0
#endif
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
/* USB */
#define CONFIG_USB_OHCI
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_I2C)
#ifdef CONFIG_POST
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#else
#define CFG_CMD_POST_DIAG 0
#endif
/* IDE */
#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
/*
* Supported commands
*/
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
ADD_BMP_CMD | \
ADD_IDE_CMD | \
ADD_PCI_CMD | \
ADD_USB_CMD | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_ECHO | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_JFFS2 | \
CFG_CMD_MII | \
CFG_CMD_NFS | \
CFG_CMD_PING | \
CFG_CMD_POST_DIAG | \
CFG_CMD_REGINFO | \
CFG_CMD_SNTP | \
CFG_CMD_BSP)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_TIMESTAMP /* display image timestamps */
#if (TEXT_BASE == 0xFC000000) /* Boot low */
# define CFG_LOWBOOT 1
#endif
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#if defined(CONFIG_TQM5200_B)
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
"update=protect off FC000000 FC07FFFF;" \
"erase FC000000 FC07FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC07FFFF\0" \
""
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"load=tftp 200000 $(u-boot)\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0" \
""
#endif /* CONFIG_TQM5200_B */
#define CONFIG_BOOTCOMMAND "run net_nfs"
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#endif
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_MODULE 2 /* Select I2C module #2 */
/*
* I2C clock frequency
*
* Please notice, that the resulting clock frequency could differ from the
* configured value. This is because the I2C clock is derived from system
* clock over a frequency divider with only a few divider values. U-boot
* calculates the best approximation for CFG_I2C_SPEED. However the calculated
* approximation allways lies below the configured value, never above.
*/
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F
/*
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
* also). For other EEPROMs configuration should be verified. On Mini-FAP the
* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
* same configuration could be used.
*/
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
/* List of I2C addresses to be verified by POST */
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
CFG_I2C_RTC_ADDR, \
CFG_I2C_SLAVE }
/*
* Flash configuration
*/
#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CFG_FLASH_USE_BUFFER_WRITE 1
#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
#else /* CFG_LOWBOOT */
#if defined(CONFIG_TQM5200_B)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000)
#else
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
#endif /* CONFIG_TQM5200_B */
#endif /* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
/* Dynamic MTD partition support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM5200-0"
#if defined(CONFIG_TQM5200_B)
#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
"1280k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
"16m(big-fs)," \
"8m(misc)"
#else
#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
"1408k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
"16m(big-fs)," \
"8m(misc)"
#endif /* CONFIG_TQM5200_B */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000
#if defined(CONFIG_TQM5200_B)
#define CFG_ENV_SECT_SIZE 0x40000
#else
#define CFG_ENV_SECT_SIZE 0x20000
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#endif /* CONFIG_TQM5200_B */
/*
* Memory map
*/
#define CFG_MBAR 0xF0000000
#define CFG_SDRAM_BASE 0x00000000
#define CFG_DEFAULT_MBAR 0x80000000
/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
#endif
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1
#endif
#if defined(CONFIG_TQM5200_B)
#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
#else
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#endif /* CONFIG_TQM5200_B */
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
/*
* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
*/
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 0x00
/*
* GPIO configuration
*
* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
* Bit 0 (mask: 0x80000000): 1
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
* Use for REV200 STK52XX boards. Do not use with REV100 modules
* (because, there I2C1 is used as I2C bus)
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
* 000 -> All PSC2 pins are GIOPs
* 001 -> CAN1/2 on PSC2 pins
* Use for REV100 STK52xx boards
* use PSC3: Bits 20:23 (mask: 0x00000300):
* 0001 -> USB2
* 0000 -> GPIO
* use PSC6:
* on STK52xx:
* use as UART. Pins PSC6_0 to PSC6_3 are used.
* Bits 9:11 (mask: 0x00700000):
* 101 -> PSC6 : Extended POST test is not available
* on MINI-FAP and TQM5200_IB:
* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
* 000 -> PSC6 could not be used as UART, CODEC or IrDA
* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
* tests.
*/
#define CFG_GPS_PORT_CONFIG 0x81500114
/*
* RTC configuration
*/
#define CONFIG_RTC_M41T11 1
#define CFG_I2C_RTC_ADDR 0x68
#define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
year */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
* Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
* which is normally part of the default commands (CFV_CMD_DFL)
*/
#define CONFIG_LOOPW
/*
* Various low-level settings
*/
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE
#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
#endif
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
#define CONFIG_LAST_STAGE_INIT
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
#define CFG_CS2_START 0xE5000000
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#define CFG_CS2_CFG 0x0004D930
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
#define CFG_RESET_ADDRESS 0xff000000
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------
*/
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_USB_CONFIG 0x00001000
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CFG_ATA_STRIDE 4
#endif /* __CONFIG_H */

197
include/configs/TQM5200.h
View File

@@ -2,7 +2,7 @@
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2005
* (C) Copyright 2004-2006
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
@@ -32,28 +32,30 @@
* (easy to change)
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#ifndef CONFIG_CAM5200 /* On a Cameron board or ... */
#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
#endif
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifdef CONFIG_STK52XX
@@ -83,7 +85,7 @@
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_NET_MULTI 1
#define CONFIG_EEPRO100
#define CONFIG_EEPRO100 1
#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
#define CONFIG_NS8382X 1
#endif /* CONFIG_STK52XX */
@@ -97,7 +99,7 @@
/*
* Video console
*/
#if 1
#ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SM501
#define CONFIG_VIDEO_SM501_32BPP
@@ -130,10 +132,12 @@
#define ADD_USB_CMD 0
#endif
#ifndef CONFIG_CAM5200
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_I2C)
#endif
#ifdef CONFIG_POST
#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
@@ -177,8 +181,8 @@
#define CONFIG_TIMESTAMP /* display image timestamps */
#if (TEXT_BASE == 0xFC000000) /* Boot low */
# define CFG_LOWBOOT 1
#if (TEXT_BASE != 0xFFF00000)
# define CFG_LOWBOOT 1 /* Boot low */
#endif
/*
@@ -187,20 +191,42 @@
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#if defined (CONFIG_TQM5200_AA)
# define CONFIG_U_BOOT_SUFFIX "-AA\0"
#elif defined (CONFIG_TQM5200_AB)
# define CONFIG_U_BOOT_SUFFIX "-AB\0"
#elif defined (CONFIG_TQM5200_AC)
# define CONFIG_U_BOOT_SUFFIX "-AC\0"
#ifdef CONFIG_STK52XX
# if defined(CONFIG_TQM5200_B)
# if defined(CFG_LOWBOOT)
# define ENV_UPDT \
"update=protect off FC000000 FC07FFFF;" \
"erase FC000000 FC07FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC07FFFF\0"
# else /* highboot */
# define ENV_UPDT \
"update=protect off FFF00000 FFF7FFFF;" \
"erase FFF00000 FFF7FFFF;" \
"cp.b 200000 FFF00000 ${filesize};" \
"protect on FFF00000 FFF7FFFF\0"
# endif /* CFG_LOWBOOT */
# else /* !CONFIG_TQM5200_B */
# define ENV_UPDT \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0"
# endif /* CONFIG_TQM5200_B */
#elif defined (CONFIG_CAM5200)
# define ENV_UPDT \
"update=protect off FC000000 FC03FFFF;" \
"erase FC000000 FC03FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC03FFFF\0"
#else
# define CONFIG_U_BOOT_SUFFIX "\0"
#endif
# error "Unknown Carrier Board"
#endif /* CONFIG_STK52XX */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
@@ -211,18 +237,18 @@
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_self=run ramargs addip;" \
"addcons=setenv bootargs ${bootargs} " \
"console=ttyS0,${baudrate}\0" \
"flash_self=run ramargs addip addcons;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip;" \
"flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
"bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0" \
ENV_UPDT \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
@@ -284,13 +310,6 @@
#endif
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
CFG_I2C_SLAVE }
#elif defined (CONFIG_TQM5200_AC)
#define I2C_ADDR_LIST { CFG_I2C_SLAVE }
#endif
#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
@@ -301,45 +320,80 @@
/*
* Flash configuration
*/
#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
#define CFG_FLASH_BASE 0xFC000000
/* use CFI flash driver if no module variant is spezified */
/* use CFI flash driver */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
#define CFG_FLASH_USE_BUFFER_WRITE 1
#if defined (CONFIG_CAM5200)
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
#elif defined(CONFIG_TQM5200_B)
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000)
#else
# define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
#endif
#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
#else /* CFG_LOWBOOT */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
#endif /* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
/* Dynamic MTD partition support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=TQM5200-0"
#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
#ifdef CONFIG_STK52XX
# if defined(CONFIG_TQM5200_B)
# if defined(CFG_LOWBOOT)
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \
"1536k(kernel)," \
"3584k(small-fs)," \
"2m(initrd)," \
"8m(misc)," \
"16m(big-fs)"
# else /* highboot */
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:2560k(kernel)," \
"3584k(small-fs)," \
"2m(initrd)," \
"8m(misc)," \
"15m(big-fs)," \
"1m(firmware)"
# endif /* CFG_LOWBOOT */
# else /* !CONFIG_TQM5200_B */
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
"1408k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
"16m(big-fs)," \
"8m(misc)"
"8m(misc)," \
"16m(big-fs)"
# endif /* CONFIG_TQM5200_B */
#elif defined (CONFIG_CAM5200)
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
"1792k(kernel)," \
"3584k(small-fs)," \
"2m(initrd)," \
"8m(misc)," \
"16m(big-fs)"
#else
# error "Unknown Carrier Board"
#endif /* CONFIG_STK52XX */
/*
* Environment settings
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000
#define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
#if defined(CONFIG_TQM5200_B)
#define CFG_ENV_SECT_SIZE 0x40000
#else
#define CFG_ENV_SECT_SIZE 0x20000
#endif /* CONFIG_TQM5200_B */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Memory map
@@ -367,8 +421,15 @@
# define CFG_RAMBOOT 1
#endif
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
#if defined (CONFIG_CAM5200)
# define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#elif defined(CONFIG_TQM5200_B)
# define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
#else
# define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
#endif
#define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
@@ -429,6 +490,8 @@
#if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
# define CONFIG_RTC_M41T11 1
# define CFG_I2C_RTC_ADDR 0x68
# define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
year */
#else
# define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
#endif
@@ -438,6 +501,10 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#define CFG_PROMPT_HUSH_PS2 "> "
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
@@ -484,37 +551,25 @@
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
/* automatic configuration of chip selects */
#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
#ifdef CONFIG_TQM5200_AB
#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
#else /* CONFIG_CS_AUTOCONF */
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#endif
#define CFG_CS2_CFG 0x0004D930
#endif
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */

11
include/configs/TQM85xx.h
View File

@@ -158,7 +158,7 @@
#undef CONFIG_CONS_NONE /* define if console on something else */
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
#else
#else /* ! TQM8560 */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
@@ -170,6 +170,15 @@
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* PS/2 Keyboard */
#if !defined(CONFIG_TQM8560)
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
#define CONFIG_BOARD_EARLY_INIT_R 1
#endif /* !CONFIG_TQM8560 */
#endif /* CONFIG_TQM8560 */
#define CONFIG_BAUDRATE 115200

492
include/configs/TQM885D.h Normal file
View File

@@ -0,0 +1,492 @@
/*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2006
* Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */
/* (it will be used if there is no */
/* 'cpuclk' variable with valid value) */
#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */
/* (function measure_gclk() */
/* will be called) */
#ifdef CFG_MEASURE_CPUCLK
#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
#endif
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"flash_nfs=run nfsargs addip;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"rootpath=/opt/eldk/ppc_8xx\0" \
"bootfile=/tftpboot/TQM866M/uImage\0" \
"kernel_addr=40080000\0" \
"ramdisk_addr=40180000\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
#define CFG_I2C_SLAVE 0xFE
#ifdef CONFIG_SOFT_I2C
/*
* Software (bit-bang) I2C driver configuration
*/
#define PB_SCL 0x00000020 /* PB 26 */
#define PB_SDA 0x00000010 /* PB 27 */
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
else immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
#endif /* CONFIG_SOFT_I2C */
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
# define CONFIG_RTC_DS1337 1
# define CFG_I2C_RTC_ADDR 0x68
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
#define CONFIG_TIMESTAMP /* but print image timestmps */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IDE | \
CFG_CMD_MII | \
CFG_CMD_NFS | \
CFG_CMD_PING )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if 0
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
#endif
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
#define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
#define CFG_ALT_MEMTEST /* alternate, more extensive
memory test.*/
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
* which is normally part of the default commands (CFV_CMD_DFL)
*/
#define CONFIG_LOOPW
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xFFF00000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#ifndef CONFIG_CAN_DRIVER
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#else /* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif /* CONFIG_CAN_DRIVER */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
/*-----------------------------------------------------------------------
* PCMCIA stuff
*-----------------------------------------------------------------------
*
*/
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
/*-----------------------------------------------------------------------
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET 0x0100
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
#define CFG_DER 0
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
/* used to re-map FLASH both when starting from SRAM or FLASH:
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/*
* FLASH timing: Default value of OR0 after reset
*/
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
OR_SCY_6_CLK | OR_TRLX)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
#define CFG_OR1_REMAP CFG_OR0_REMAP
#define CFG_OR1_PRELIM CFG_OR0_PRELIM
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
/*
* BR2/3 and OR2/3 (SDRAM)
*
*/
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CFG_OR_TIMING_SDRAM 0x00000A00
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#ifndef CONFIG_CAN_DRIVER
#define CFG_OR3_PRELIM CFG_OR2_PRELIM
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
BR_PS_8 | BR_MS_UPMB | BR_V )
#endif /* CONFIG_CAN_DRIVER */
/*
* 4096 Rows from SDRAM example configuration
* 1000 factor s -> ms
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
*/
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
/*
* Memory Periodic Timer Prescaler
* Periodic timer for refresh, start with refresh rate for 40 MHz clock
* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
*/
#define CFG_MAMR_PTA 39
/*
* For 16 MBit, refresh rates could be 31.3 us
* (= 64 ms / 2K = 125 / quad bursts).
* For a simpler initialization, 15.6 us is used instead.
*
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
*/
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 10 column SDRAM */
#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Network configuration
*/
#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
#define CONFIG_FEC_ENET /* enable ethernet on FEC */
#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
#if (CONFIG_COMMANDS & CFG_CMD_MII)
#define CFG_DISCOVER_PHY
#endif
#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
switching to another netwok (if the
tried network is unreachable) */
#define CONFIG_ETHPRIME "SCC ETHERNET"
#endif /* __CONFIG_H */

5
include/configs/aev.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2003-2005
* (C) Copyright 2003-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2005
@@ -370,10 +370,7 @@
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
/* automatic configuration of chip selects */
#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used

16
include/configs/bamboo.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2005
* (C) Copyright 2005-2006
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -49,7 +49,7 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
@@ -257,8 +257,8 @@
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
"cp.b 100000 fff80000 80000;" \
"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
"cp.b 100000 fffa0000 60000;" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
@@ -358,6 +358,14 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING
#ifdef CONFIG_CMDLINE_EDITING
#undef CONFIG_AUTO_COMPLETE
#else
#define CONFIG_AUTO_COMPLETE
#endif
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------

11
include/configs/cmc_pu2.h
View File

@@ -108,7 +108,7 @@
/* still about 20 kB free with this defined */
#define CFG_LONGHELP
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTDELAY 1
#ifdef CONFIG_HARD_I2C
#define CONFIG_COMMANDS \
@@ -206,15 +206,6 @@ struct bd_info_ext {
#error CONFIG_USE_IRQ not supported
#endif
#define CFG_DEVICE_NULLDEV 1 /* enble null device */
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
#define CONFIG_AUTOBOOT_STOP_STR "R" /* default password */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_EXTRA_ENV_SETTINGS \
"net_nfs=tftp ${loadaddr} ${bootfile};run nfsargs addip addcons " \
"addmtd;bootm\0" \

195
include/configs/gth2.h Normal file
View File

@@ -0,0 +1,195 @@
/*
* (C) Copyright 2005
* Thomas.Lange@corelatus.se
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file contains the configuration parameters for the gth2 board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
#define CONFIG_GTH2 1
#define CONFIG_AU1X00 1 /* alchemy series cpu */
#define CONFIG_AU1000 1
#define CONFIG_MISC_INIT_R 1
#define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
#define CONFIG_BAUDRATE 115200
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 115200 }
/* Only interrupt boot if space is pressed */
/* If a long serial cable is connected but */
/* other end is dead, garbage will be read */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n"
#define CONFIG_AUTOBOOT_DELAY_STR "d"
#define CONFIG_AUTOBOOT_STOP_STR " "
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
#define CONFIG_BOOTARGS "panic=1"
#define CONFIG_EXTRA_ENV_SETTINGS \
"addmisc=setenv bootargs $(bootargs) " \
"ethaddr=$(ethaddr) \0" \
"netboot=bootp;run addmisc;bootm\0" \
""
/* Boot from Compact flash partition 2 as default */
#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \
CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT ))
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args*/
#define CFG_MALLOC_LEN 128*1024
#define CFG_BOOTPARAMS_LEN 128*1024
#define CFG_MHZ 500
#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
#define CFG_LOAD_ADDR 0x81000000 /* default load address */
#define CFG_MEMTEST_START 0x80100000
#define CFG_MEMTEST_END 0x83000000
#define CONFIG_HW_WATCHDOG 1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (192 << 10)
#define CFG_INIT_SP_OFFSET 0x400000
/* We boot from this flash, selected with dip switch */
#define CFG_FLASH_BASE PHYS_FLASH
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_NOWHERE 1
/* Address and size of Primary Environment Sector */
#define CFG_ENV_ADDR 0xB0030000
#define CFG_ENV_SIZE 0x10000
#define CONFIG_FLASH_16BIT
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_NET_MULTI
#define CONFIG_MEMSIZE_IN_BYTES
/*---ATA PCMCIA ------------------------------------*/
#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
#define CFG_PCMCIA_MEM_ADDR 0x20000000
#define CFG_PCMCIA_IO_BASE 0x28000000
#define CFG_PCMCIA_ATTR_BASE 0x30000000
#define CONFIG_PCMCIA_SLOT_A
#define CONFIG_ATAPI 1
#define CONFIG_MAC_PARTITION 1
/* We run CF in "true ide" mode or a harddrive via pcmcia */
#define CONFIG_IDE_PCMCIA 1
/* We only support one slot for now */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CFG_ATA_IDE0_OFFSET 0
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE
/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET 0
/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET 0
/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET 0x0200
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384
#define CFG_ICACHE_SIZE 16384
#define CFG_CACHELINE_SIZE 32
#define GPIO_CACONFIG (1<<0)
#define GPIO_DPACONFIG (1<<6)
#define GPIO_ERESET (1<<11)
#define GPIO_EEDQ (1<<17)
#define GPIO_WDI (1<<18)
#define GPIO_RJ1LY (1<<22)
#define GPIO_RJ1LG (1<<23)
#define GPIO_LEDCLK (1<<29)
#define GPIO_LEDD (1<<30)
#define GPIO_CPU_LED (1<<31)
#endif /* __CONFIG_H */

262
include/configs/kvme080.h Normal file
View File

@@ -0,0 +1,262 @@
/*
* (C) Copyright 2005
* Sangmoon Kim, dogoil@etinsys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_KVME080 1
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5
#define CONFIG_IPADDR 192.168.0.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 " \
"root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
"ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
"kvme080:eth0:none " \
"mtdparts=phys_mapped_flash:12m(root),-(kernel)"
#define CONFIG_BOOTCOMMAND \
"tftp 800000 kvme080/uImage; " \
"bootm 800000"
#define CONFIG_LOADADDR 800000
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_LOADS_ECHO 1
#undef CFG_LOADS_BAUD_CHANGE
#undef CONFIG_WATCHDOG
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_RTC_DS164x
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_CACHE | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_JFFS2 | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_SDRAM | \
CFG_CMD_SNTP)
#define CONFIG_NETCONSOLE
#include <cmd_confdefs.h>
#define CFG_LONGHELP
#define CFG_PROMPT "=> "
#define CFG_CBSIZE 256
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS 16
#define CFG_BARGSIZE CFG_CBSIZE
#define CFG_MEMTEST_START 0x00400000
#define CFG_MEMTEST_END 0x07C00000
#define CFG_LOAD_ADDR 0x00100000
#define CFG_HZ 1000
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_INIT_RAM_ADDR 0x40000000
#define CFG_INIT_RAM_END 0x1000
#define CFG_GBL_DATA_SIZE 128
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x7C000000
#define CFG_EUMB_ADDR 0xFC000000
#define CFG_NVRAM_BASE_ADDR 0xFF000000
#define CFG_NS16550_COM1 0xFF080000
#define CFG_NS16550_COM2 0xFF080010
#define CFG_NS16550_COM3 0xFF080020
#define CFG_NS16550_COM4 0xFF080030
#define CFG_RESET_ADDRESS 0xFFF00100
#define CFG_MAX_RAM_SIZE 0x20000000
#define CFG_FLASH_SIZE (16 * 1024 * 1024)
#define CFG_NVRAM_SIZE 0x7FFF8
#define CONFIG_VERY_BIG_RAM
#define CFG_MONITOR_LEN 0x00040000
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_LEN (512 << 10)
#define CFG_BOOTMAPSZ (8 << 20)
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_USE_BUFFER_WRITE
#define CFG_FLASH_PROTECTION
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_PROTECT_CLEAR
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 256
#define CFG_FLASH_ERASE_TOUT 120000
#define CFG_FLASH_WRITE_TOUT 500
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS 1
#define CFG_ENV_IS_IN_NVRAM 1
#define CONFIG_ENV_OVERWRITE 1
#define CFG_NVRAM_ACCESS_ROUTINE
#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
#define CFG_ENV_SIZE 0x400
#define CFG_ENV_OFFSET 0
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK 14745600
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100
#define CONFIG_EEPRO100_SROM_WRITE
#define CFG_RX_ETH_BUFFER 8
#define CONFIG_HARD_I2C 1
#define CFG_I2C_SPEED 400000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_SYS_CLK_FREQ 33333333
#define CFG_CACHELINE_SIZE 32
#if CONFIG_COMMANDS & CFG_CMD_KGDB
# define CFG_CACHELINE_SHIFT 5
#endif
#define CFG_DLL_EXTEND 0x00
#define CFG_PCI_HOLD_DEL 0x20
#define CFG_ROMNAL 15
#define CFG_ROMFAL 31
#define CFG_REFINT 430
#define CFG_DBUS_SIZE2 1
#define CFG_BSTOPRE 121
#define CFG_REFREC 8
#define CFG_RDLAT 4
#define CFG_PRETOACT 3
#define CFG_ACTTOPRE 5
#define CFG_ACTORW 3
#define CFG_SDMODE_CAS_LAT 3
#define CFG_SDMODE_WRAP 0
#define CFG_REGISTERD_TYPE_BUFFER 1
#define CFG_EXTROM 1
#define CFG_REGDIMM 0
#define CFG_BANK0_START 0x00000000
#define CFG_BANK0_END (0x4000000 - 1)
#define CFG_BANK0_ENABLE 1
#define CFG_BANK1_START 0x04000000
#define CFG_BANK1_END (0x8000000 - 1)
#define CFG_BANK1_ENABLE 1
#define CFG_BANK2_START 0x3ff00000
#define CFG_BANK2_END 0x3fffffff
#define CFG_BANK2_ENABLE 0
#define CFG_BANK3_START 0x3ff00000
#define CFG_BANK3_END 0x3fffffff
#define CFG_BANK3_ENABLE 0
#define CFG_BANK4_START 0x00000000
#define CFG_BANK4_END 0x00000000
#define CFG_BANK4_ENABLE 0
#define CFG_BANK5_START 0x00000000
#define CFG_BANK5_END 0x00000000
#define CFG_BANK5_ENABLE 0
#define CFG_BANK6_START 0x00000000
#define CFG_BANK6_END 0x00000000
#define CFG_BANK6_ENABLE 0
#define CFG_BANK7_START 0x00000000
#define CFG_BANK7_END 0x00000000
#define CFG_BANK7_ENABLE 0
#define CFG_BANK_ENABLE 0x03
#define CFG_ODCR 0x75
#define CFG_PGMAX 0x32
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U
#define CFG_DBAT1L CFG_IBAT1L
#define CFG_DBAT1U CFG_IBAT1U
#define CFG_DBAT2L CFG_IBAT2L
#define CFG_DBAT2U CFG_IBAT2U
#define CFG_DBAT3L CFG_IBAT3L
#define CFG_DBAT3U CFG_IBAT3U
#define BOOTFLAG_COLD 0x01
#define BOOTFLAG_WARM 0x02
#endif /* __CONFIG_H */

62
include/configs/mcc200.h
View File

@@ -47,8 +47,22 @@
/*
* Serial console configuration
*
* To select console on the one of 8 external UARTs,
* define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
* or as 5, 6, 7, or 8 for the second Quad UART.
*
* CONFIG_PSC_CONSOLE must be undefined in this case.
*/
/* #define CONFIG_QUART_CONSOLE 1 */ /* console is on UART1 of QUART1 */
/*
* To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
* and undefine CONFIG_QUART_CONSOLE.
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
#error "Select only one console device!"
#endif
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
@@ -256,11 +270,59 @@
#define CFG_CS2_SIZE 0x00001000
#define CFG_CS2_CFG 0x1d300
/* Second Quad UART @0x80010000 */
#define CFG_CS1_START 0x80010000
#define CFG_CS1_SIZE 0x00001000
#define CFG_CS1_CFG 0x1d300
/*
* Select one of quarts as a default
* console. If undefined - PSC console
* wil be default
*/
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333333
#define CFG_RESET_ADDRESS 0xff000000
/*
* QUART Expanders support
*/
#if defined(CONFIG_QUART_CONSOLE)
/*
* We'll use NS16550 chip routines,
*/
#define CFG_NS16550 1
#define CFG_NS16550_SERIAL 1
#define CONFIG_CONS_INDEX 1
/*
* To achieve necessary offset on SC16C554
* A0-A2 (register select) pins with NS16550
* functions (in struct NS16550), REG_SIZE
* should be 4, because A0-A2 pins are connected
* to DA2-DA4 address bus lines.
*/
#define CFG_NS16550_REG_SIZE 4
/*
* LocalPlus Bus already inited in cpu_init_f(),
* so can work with QUART's chip selects.
* One of four SC16C554 UARTs is selected with
* A3-A4 (DA5-DA6) lines.
*/
#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5)
#define CFG_NS16550_COM1 (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
#define CFG_NS16550_COM1 (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
#elif
#error "Wrong QUART expander number."
#endif
/*
* SC16C554 chip's external crystal oscillator frequency
* is 7.3728 MHz
*/
#define CFG_NS16550_CLK 7372800
#endif /* CONFIG_QUART_CONSOLE */
/*-----------------------------------------------------------------------
* USB stuff
*-----------------------------------------------------------------------

8
include/configs/pcs440ep.h
View File

@@ -116,18 +116,17 @@
*----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#undef CONFIG_DDR_ECC /* don't use ECC */
#define SPD_EEPROM_ADDRESS {0x50, 0x51}
#define SPD_EEPROM_ADDRESS {0x50}
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR (0xa4>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
@@ -211,6 +210,7 @@
CFG_CMD_ASKENV | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \

419
include/configs/ppmc7xx.h Normal file
View File

@@ -0,0 +1,419 @@
/*
* ppmc7xx.h
* ---------
*
* Wind River PPMC 7xx/74xx board configuration file.
*
* By Richard Danter (richard.danter@windriver.com)
* Copyright (C) 2005 Wind River Systems
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_PPMC7XX
/*===================================================================
*
* User configurable settings - Modify to your preference
*
*===================================================================
*/
/*
* Debug
*
* DEBUG - Define this is you want extra debug info
* GTREGREAD - Required to build with debug
* do_bdinfo - Required to build with debug
*/
#undef DEBUG
#define GTREGREAD(x) 0xFFFFFFFF
#define do_bdinfo(a,b,c,d)
/*
* CPU type
*
* CONFIG_7xx - We have a 750 or 755 CPU
* CONFIG_74xx - We have a 7400 CPU
* CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
* CONFIG_BUS_CLK - System bus clock in Hz
*/
#define CONFIG_7xx
#undef CONFIG_74xx
#undef CONFIG_ALTIVEC
#define CONFIG_BUS_CLK 66000000
/*
* Monitor configuration
*
* CONFIG_COMMANDS - List of command sets to include in shell
*
* The following command sets have been tested and known to work:
*
* CFG_CMD_CACHE - Cache control commands
* CFG_CMD_MEMORY - Memory display, change and test commands
* CFG_CMD_FLASH - Erase and program flash
* CFG_CMD_ENV - Environment commands
* CFG_CMD_RUN - Run commands stored in env vars
* CFG_CMD_ELF - Load ELF files
* CFG_CMD_NET - Networking/file download commands
* CFG_CMD_PING - ICMP Echo Request command
* CFG_CMD_PCI - PCI Bus scanning command
*/
#define CONFIG_COMMANDS ( (CFG_CMD_DFL & ~(CFG_CMD_KGDB)) | \
CFG_CMD_FLASH | \
CFG_CMD_ENV | \
CFG_CMD_RUN | \
CFG_CMD_ELF | \
CFG_CMD_NET | \
CFG_CMD_PING | \
CFG_CMD_PCI)
/*
* Serial configuration
*
* CONFIG_CONS_INDEX - Serial console port number (COM1)
* CONFIG_BAUDRATE - Serial speed
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 9600
/*
* PCI config
*
* CONFIG_PCI - Enable PCI bus
* CONFIG_PCI_PNP - Enable Plug & Play support
* CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
*/
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#undef CONFIG_PCI_SCAN_SHOW
/*
* Network config
*
* CONFIG_NET_MULTI - Support for multiple network interfaces
* CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
* CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
*/
#define CONFIG_NET_MULTI
#define CONFIG_EEPRO100
#define CONFIG_EEPRO100_SROM_WRITE
/*
* Enable extra init functions
*
* CONFIG_MISC_INIT_F - Call pre-relocation init functions
* CONFIG_MISC_INIT_R - Call post relocation init functions
*/
#undef CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R
/*
* Boot config
*
* CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
* CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
*/
#define CONFIG_BOOTCOMMAND \
"bootp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
"bootm"
#define CONFIG_BOOTDELAY 5
/*===================================================================
*
* Board configuration settings - You should not need to modify these
*
*===================================================================
*/
#include <cmd_confdefs.h>
/*
* Memory map
*
* This board runs in a standard CHRP (Map-B) configuration.
*
* Type Start End Size Width Chip Sel
* ----------- ----------- ----------- ------- ------- --------
* SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
* User LED's 0x78000000 RCS3
* UART 0x7C000000 RCS2
* Mailbox 0xFF000000 RCS1
* Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
*
* Flash sectors are laid out as follows.
*
* Sector Start End Size Comments
* ------- ----------- ----------- ------- -----------
* 0 0xFFC00000 0xFFC3FFFF 256KB
* 1 0xFFC40000 0xFFC7FFFF 256KB
* 2 0xFFC80000 0xFFCBFFFF 256KB
* 3 0xFFCC0000 0xFFCFFFFF 256KB
* 4 0xFFD00000 0xFFD3FFFF 256KB
* 5 0xFFD40000 0xFFD7FFFF 256KB
* 6 0xFFD80000 0xFFDBFFFF 256KB
* 7 0xFFDC0000 0xFFDFFFFF 256KB
* 8 0xFFE00000 0xFFE3FFFF 256KB
* 9 0xFFE40000 0xFFE7FFFF 256KB
* 10 0xFFE80000 0xFFEBFFFF 256KB
* 11 0xFFEC0000 0xFFEFFFFF 256KB
* 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
* 13 0xFFF40000 0xFFF7FFFF 256KB
* 14 0xFFF80000 0xFFFBFFFF 256KB
* 15 0xFFFC0000 0xFFFDFFFF 128KB
* 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
* 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
* 18 0xFFFF0000 0xFFFFFFFF 64KB
*/
/*
* SDRAM config - see memory map details above.
*
* CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
* CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_SIZE 0x04000000
/*
* Flash config - see memory map details above.
*
* CFG_FLASH_BASE - Start address of flash memory
* CFG_FLASH_SIZE - Total size of contiguous flash mem
* CFG_FLASH_ERASE_TOUT - Erase timeout in ms
* CFG_FLASH_WRITE_TOUT - Write timeout in ms
* CFG_MAX_FLASH_BANKS - Number of banks of flash on board
* CFG_MAX_FLASH_SECT - Number of sectors in a bank
*/
#define CFG_FLASH_BASE 0xFFC00000
#define CFG_FLASH_SIZE 0x00400000
#define CFG_FLASH_ERASE_TOUT 250000
#define CFG_FLASH_WRITE_TOUT 5000
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 19
/*
* Monitor config - see memory map details above
*
* CFG_MONITOR_BASE - Base address of monitor code
* CFG_MALLOC_LEN - Size of malloc pool (128KB)
*/
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_LEN 0x20000
/*
* Command shell settings
*
* CFG_BARGSIZE - Boot Argument buffer size
* CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
* CFG_CBSIZE - Console Buffer (input) size
* CFG_LOAD_ADDR - Default load address
* CFG_LONGHELP - Provide more detailed help
* CFG_MAXARGS - Number of args accepted by monitor commands
* CFG_MEMTEST_START - Start address of test to run on RAM
* CFG_MEMTEST_END - End address of RAM test
* CFG_PBSIZE - Print Buffer (output) size
* CFG_PROMPT - Prompt string
*/
#define CFG_BARGSIZE 1024
#define CFG_BOOTMAPSZ 0x800000
#define CFG_CBSIZE 1024
#define CFG_LOAD_ADDR 0x100000
#define CFG_LONGHELP
#define CFG_MAXARGS 16
#define CFG_MEMTEST_START 0x00040000
#define CFG_MEMTEST_END 0x00040100
#define CFG_PBSIZE 1024
#define CFG_PROMPT "=> "
/*
* Environment config - see memory map details above
*
* CFG_ENV_IS_IN_FLASH - The env variables are stored in flash
* CFG_ENV_ADDR - Address of the sector containing env vars
* CFG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
* CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
*/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR 0xFFFE0000
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR_REDUND 0xFFFE8000
#define CFG_ENV_SIZE_REDUND 0x1000
#define CFG_ENV_SECT_SIZE 0x8000
/*
* Initial RAM config
*
* Since the main system RAM is initialised very early, we place the INIT_RAM
* in the main system RAM just above the exception vectors. The contents are
* copied to top of RAM by the init code.
*
* CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
* CFG_INIT_RAM_END - Size of Init RAM
* CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
* CFG_GBL_DATA_OFFSET - Start of global data, top of stack
*/
#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
#define CFG_INIT_RAM_END 0x4000
#define CFG_GBL_DATA_SIZE 128
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*
* Initial BAT config
*
* BAT0 - System SDRAM
* BAT1 - LED's and Serial Port
* BAT2 - PCI Memory
* BAT3 - PCI I/O including Flash Memory
*/
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CFG_DBAT0L CFG_IBAT0L
#define CFG_DBAT0U CFG_IBAT0U
#define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
/*
* Cache config
*
* CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
* CFG_L2 - L2 cache enabled if defined
* L2_INIT - L2 cache init flags
* L2_ENABLE - L2 cache enable flags
*/
#define CFG_CACHELINE_SIZE 32
#undef CFG_L2
#define L2_INIT 0
#define L2_ENABLE 0
/*
* Clocks config
*
* CFG_BUS_HZ - Bus clock frequency in Hz
* CFG_BUS_CLK - As above (?)
* CFG_HZ - Decrementer freq in Hz
*/
#define CFG_BUS_HZ CONFIG_BUS_CLK
#define CFG_BUS_CLK CONFIG_BUS_CLK
#define CFG_HZ 1000
/*
* Serial port config
*
* CFG_BAUDRATE_TABLE - List of valid baud rates
* CFG_NS16550 - Include the NS16550 driver
* CFG_NS16550_SERIAL - Include the serial (wrapper) driver
* CFG_NS16550_CLK - Frequency of reference clock
* CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
* CFG_NS16550_COM1 - Base address of 1st serial port
*/
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_CLK 3686400
#define CFG_NS16550_REG_SIZE -8
#define CFG_NS16550_COM1 0x7C000000
/*
* PCI Config - Address Map B (CHRP)
*/
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x40000000
#define CFG_PCI_MEM_BUS 0x80000000
#define CFG_PCI_MEM_PHYS 0x80000000
#define CFG_PCI_MEM_SIZE 0x7D000000
#define CFG_ISA_MEM_BUS 0x00000000
#define CFG_ISA_MEM_PHYS 0xFD000000
#define CFG_ISA_MEM_SIZE 0x01000000
#define CFG_PCI_IO_BUS 0x00800000
#define CFG_PCI_IO_PHYS 0xFE800000
#define CFG_PCI_IO_SIZE 0x00400000
#define CFG_ISA_IO_BUS 0x00000000
#define CFG_ISA_IO_PHYS 0xFE000000
#define CFG_ISA_IO_SIZE 0x00800000
#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
#define CFG_ISA_IO CFG_ISA_IO_PHYS
#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
/*
* Extra init functions
*
* CFG_BOARD_ASM_INIT - Call assembly init code
*/
#define CFG_BOARD_ASM_INIT
/*
* Boot flags
*
* BOOTFLAG_COLD - Indicates a power-on boot
* BOOTFLAG_WARM - Indicates a software reset
*/
#define BOOTFLAG_COLD 0x01
#define BOOTFLAG_WARM 0x02
#endif /* __CONFIG_H */

239
include/configs/sbc2410x.h Normal file
View File

@@ -0,0 +1,239 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
* Gary Jennejohn <gj@denx.de>
* David Mueller <d.mueller@elsoft.ch>
*
* Modified for the friendly-arm SBC-2410X by
* (C) Copyright 2005
* JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
*
* Configuation settings for the friendly-arm SBC-2410X board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* If we are developing, we might want to start armboot from ram
* so we MUST NOT initialize critical regs like mem-timing ...
*/
#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
#define USE_920T_MMU 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
*/
#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
#define CS8900_BASE 0x19000300
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
/************************************************************
* RTC
************************************************************/
#define CONFIG_RTC_S3C24X0 1
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
/***********************************************************
* Command definition
***********************************************************/
#define CONFIG_COMMANDS \
(CONFIG_CMD_DFL | \
CFG_CMD_CACHE | \
/*CFG_CMD_NAND |*/ \
/*CFG_CMD_EEPROM |*/ \
/*CFG_CMD_I2C |*/ \
/*CFG_CMD_USB |*/ \
CFG_CMD_REGINFO | \
CFG_CMD_DATE | \
CFG_CMD_PING | \
CFG_CMD_DHCP | \
CFG_CMD_ELF)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.69
#define CONFIG_SERVERIP 192.168.0.1
/*#define CONFIG_BOOTFILE "elinos-lart" */
#define CONFIG_BOOTCOMMAND "dhcp; bootm"
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x33000000 /* default load address */
/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
/* it to wrap 100 times (total 1562500) to get 1 sec. */
#define CFG_HZ 1562500
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CFG_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#ifdef CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif
#ifdef CONFIG_AMD_LV400
#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
#endif
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* NAND flash settings
*/
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define NAND_WAIT_READY(nand) NF_WaitRB()
#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
#define WRITE_NAND(d, adr) NF_Write(d)
#define READ_NAND(adr) NF_Read()
/* the following functions are NOP's because S3C24X0 handles this in hardware */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_TAG
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#ifdef CONFIG_CMDLINE_EDITING
#undef CONFIG_AUTO_COMPLETE
#else
#define CONFIG_AUTO_COMPLETE
#endif
#endif /* __CONFIG_H */

362
include/configs/spc1920.h Normal file
View File

@@ -0,0 +1,362 @@
/*
* (C) Copyright 2006
* Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
*
* Configuation settings for the SPC1920 board.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __H
#define __CONFIG_H
#define CONFIG_SPC1920 1 /* SPC1920 board */
#define CONFIG_MPC885 1 /* MPC885 CPU */
#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_MII
/* #define MII_DEBUG */
/* #define CONFIG_FEC_ENET */
#undef CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
#define FEC_ENET
/* #define CONFIG_FEC2_PHY_NORXERR */
/* #define CFG_DISCOVER_PHY */
/* #define CONFIG_PHY_ADDR 0x1 */
#define CONFIG_FEC2_PHY 1
#define CONFIG_BAUDRATE 19200
/* use PLD CLK4 instead of brg */
#undef CFG_SPC1920_SMC1_CLK4
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
#define CFG_8xx_CPUCLK_MIN 40000000
#define CFG_8xx_CPUCLK_MAX 133000000
#define CFG_RESET_ADDRESS 0xf8000000
#define CONFIG_BOARD_EARLY_INIT_F
#if 1
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_ENV_OVERWRITE
#define CONFIG_NFSBOOTCOMMAND \
"dhcp;" \
"setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
"bootm"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
"bootm fe080000"
#undef CONFIG_BOOTARGS
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
#ifndef CONFIG_COMMANDS
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
| CFG_CMD_ECHO \
| CFG_CMD_IMMAP \
| CFG_CMD_JFFS2 \
| CFG_CMD_PING \
| CFG_CMD_DHCP \
| CFG_CMD_IMMAP \
| CFG_CMD_MII)
/* & ~( CFG_CMD_NET)) */
#endif /* !CONFIG_COMMANDS */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=>" /* Monitor Command Prompt */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_LOAD_ADDR 0x00100000
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CFG_IMMR 0xF0000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
#ifdef CONFIG_BZIP2
#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
#else
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
#endif /* CONFIG_BZIP2 */
#define CFG_ALLOC_DPRAM 1 /* use allocation routines */
/*
* Flash
*/
/*-----------------------------------------------------------------------
* Flash organisation
*/
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
/* Environment is in flash */
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CONFIG_ENV_OVERWRITE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
/*-----------------------------------------------------------------------
* I2C configuration
*/
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
#define CFG_I2C_SLAVE 0x7F
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
/* #define CFG_SCCR SCCR_TBS */
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
/*-----------------------------------------------------------------------
* DER - Debug Enable Register
*-----------------------------------------------------------------------
* Set to zero to prevent the processor from entering debug mode
*/
#define CFG_DER 0
/* Because of the way the 860 starts up and assigns CS0 the entire
* address space, we have to set the memory controller differently.
* Normally, you write the option register first, and then enable the
* chip select by writing the base register. For CS0, you must write
* the base register first, followed by the option register.
*/
/*
* Init Memory Controller:
*/
/* BR0 and OR0 (FLASH) */
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
/* used to re-map FLASH both when starting from SRAM or FLASH:
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/*
* FLASH timing:
*/
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_3_CLK | OR_EHTR | OR_BI)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
/*
* SDRAM CS1 UPMB
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
#define CFG_PRELIM_OR1_AM 0xF0000000
/* #define CFG_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
#define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
/* #define CFG_OR1_FINAL ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
/* #define CFG_BR1_FINAL ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
#define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
#define CFG_PTA_PER_CLK 195
#define CFG_MBMR_PTB 195
#define CFG_MPTPR MPTPR_PTP_DIV16
#define CFG_MAR 0x88
#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
MBMR_AMB_TYPE_0 | \
MBMR_G0CLB_A10 | \
MBMR_DSB_1_CYCL | \
MBMR_RLFB_1X | \
MBMR_WLFB_1X | \
MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
#define CFG_MBMR_9COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
MBMR_AMB_TYPE_1 | \
MBMR_G0CLB_A10 | \
MBMR_DSB_1_CYCL | \
MBMR_RLFB_1X | \
MBMR_WLFB_1X | \
MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
/* PLD CS5 */
#define CFG_SPC1920_PLD_BASE 0x80000000
#define CFG_PRELIM_OR5_AM 0xffff8000
#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \
OR_CSNT_SAM | \
OR_ACS_DIV1 | \
OR_BI | \
OR_SCY_0_CLK | \
OR_TRLX)
#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
/* #define CFG_PLD_BASE 0x30000000 */
/* #define CFG_OR5_PRELIM 0xffff1110 */
/* #define CFG_BR5_PRELIM 0x30000401 */
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/* Machine type
*/
#define _MACH_8xx (_MACH_fads)
#endif /* __CONFIG_H */

31
include/configs/spieval.h
View File

@@ -191,16 +191,6 @@
#undef CONFIG_BOOTARGS
#if defined (CONFIG_TQM5200_AA)
# define CONFIG_U_BOOT_SUFFIX "-AA\0"
#elif defined (CONFIG_TQM5200_AB)
# define CONFIG_U_BOOT_SUFFIX "-AB\0"
#elif defined (CONFIG_TQM5200_AC)
# define CONFIG_U_BOOT_SUFFIX "-AC\0"
#else
# define CONFIG_U_BOOT_SUFFIX "\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
@@ -217,7 +207,7 @@
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
"bootfile=/tftpboot/tqm5200/uImage\0" \
"load=tftp 200000 ${u-boot}\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin" CONFIG_U_BOOT_SUFFIX \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
@@ -283,13 +273,6 @@
#endif
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_TQM5200_AA) || defined (CONFIG_TQM5200_AB)
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
CFG_I2C_SLAVE }
#elif defined (CONFIG_TQM5200_AC)
#define I2C_ADDR_LIST { CFG_I2C_SLAVE }
#endif
#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
@@ -469,37 +452,25 @@
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
/* automatic configuration of chip selects */
#ifdef CONFIG_CS_AUTOCONF
#define CONFIG_LAST_STAGE_INIT
#endif
/*
* SRAM - Do not map below 2 GB in address space, because this area is used
* for SDRAM autosizing.
*/
#if defined CONFIG_TQM5200_AB || defined (CONFIG_CS_AUTOCONF)
#define CFG_CS2_START 0xE5000000
#ifdef CONFIG_TQM5200_AB
#define CFG_CS2_SIZE 0x80000 /* 512 kByte */
#else /* CONFIG_CS_AUTOCONF */
#define CFG_CS2_SIZE 0x100000 /* 1 MByte */
#endif
#define CFG_CS2_CFG 0x0004D930
#endif
/*
* Grafic controller - Do not map below 2 GB in address space, because this
* area is used for SDRAM autosizing.
*/
#if defined (CONFIG_TQM5200_AB) || defined (CONFIG_TQM5200_AC) || \
defined (CONFIG_CS_AUTOCONF)
#define SM501_FB_BASE 0xE0000000
#define CFG_CS1_START (SM501_FB_BASE)
#define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
#define CFG_CS1_CFG 0x8F48FF70
#define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
#endif
#define CFG_CS_BURST 0x00000000
#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */

8
include/configs/trab.h
View File

@@ -160,7 +160,6 @@
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_FAT | \
CFG_CMD_JFFS2 | \
CFG_CMD_NFS | \
CFG_CMD_SNTP | \
CFG_CMD_USB )
@@ -174,7 +173,6 @@
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_FAT | \
CFG_CMD_JFFS2 | \
CFG_CMD_NFS | \
CFG_CMD_SNTP | \
CFG_CMD_USB )
@@ -384,10 +382,10 @@
#define MTDIDS_DEFAULT "nor0=0"
/* production flash layout */
#define MTDPARTS_DEFAULT "mtdparts=0:32k(Firmware1)ro," \
#define MTDPARTS_DEFAULT "mtdparts=0:16k(Firmware1)ro," \
"16k(Env1)," \
"16k(Env2)," \
"320k(Firmware2)ro," \
"336k(Firmware2)ro," \
"896k(Kernel)," \
"5376k(Root-FS)," \
"1408k(JFFS2)," \
@@ -404,7 +402,7 @@
#endif
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_ERASE_TOUT (15*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_IN_FLASH 1

56
include/configs/voiceblue.h
View File

@@ -47,6 +47,8 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*
* Physical Memory Map
*/
@@ -94,7 +96,6 @@
#define CONFIG_ENV_OVERWRITE
#define CFG_JFFS_CUSTOM_PART /* see board/voiceblue/jffs2parts.c */
#endif
/*
@@ -104,9 +105,11 @@
#ifdef VOICEBLUE_SMALL_FLASH
#define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKSIZE SZ_8K
#define PHYS_SDRAM_1_RESERVED 0
#else
#define CFG_MALLOC_LEN SZ_4M
#define CONFIG_STACKSIZE SZ_1M
#define PHYS_SDRAM_1_RESERVED (CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
#endif
/*
@@ -174,6 +177,7 @@
#define CONFIG_BOOTCOMMAND "run nboot"
#define CONFIG_PREBOOT "run setup"
#define CONFIG_EXTRA_ENV_SETTINGS \
"silent=1\0" \
"ospart=0\0" \
"swapos=no\0" \
"setpart=" \
@@ -185,15 +189,37 @@
"fi\0" \
"setup=setenv bootargs console=ttyS0,$baudrate " \
"mtdparts=$mtdparts\0" \
"nfsargs=run setpart; setenv bootargs $bootargs " \
"root=/dev/nfs ip=dhcp\0" \
"nfsargs=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
"nfsroot=$rootpath root=/dev/nfs\0" \
"flashargs=run setpart; setenv bootargs $bootargs " \
"root=/dev/mtdblock$partition ro " \
"rootfstype=jffs2\0" \
"nboot=run nfsargs; bootp; tftp; bootm\0" \
"fboot=run flashargs; fsload /boot/uImage; bootm\0"
"initrdargs=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
"fboot=run flashargs; fsload /boot/uImage; bootm\0" \
"iboot=bootp; run initrdargs; tftp; bootm\0" \
"nboot=bootp; run nfsargs; tftp; bootm\0"
#endif
#ifndef VOICEBLUE_SMALL_FLASH
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#if 1 /* feel free to disable for development */
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
#define CONFIG_AUTOBOOT_PROMPT "\nVoiceBlue Enterprise - booting...\n"
#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
#endif
/*
* JFFS2 partitions (mtdparts command line support)
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=omapflash.0"
#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:128k(uboot),64k(env),64k(r_env),16256k(data1),-(data2)"
#endif /* VOICEBLUE_SMALL_FLASH */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@ -213,7 +239,7 @@
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START PHYS_SDRAM_1
#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - PHYS_SDRAM_1_RESERVED
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
@@ -247,22 +273,4 @@
#define VOICEBLUE_LED_REG 0x04030000
/*
* JFFS2 partitions
*
*/
/* No command line, one static partition */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV "nor0"
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET 0x00040000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=voiceblue-0"
#define MTDPARTS_DEFAULT "mtdparts=voiceblue-0:128k(uboot),64k(env),64k(renv),-(jffs2)"
*/
#endif /* __CONFIG_H */

6
include/configs/xm250.h
View File

@@ -119,9 +119,9 @@
/*
* Definitions related to passing arguments to kernel.
*/
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
#undef CONFIG_INITRD_TAG /* do not send initrd params */
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
#define CONFIG_INITRD_TAG 1 /* do not send initrd params */
#undef CONFIG_VFD /* do not send framebuffer setup */
/*

526
include/configs/yucca.h Normal file
View File

@@ -0,0 +1,526 @@
/*
* (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* 1 january 2005 Alain Saurel <asaurel@amcc.com>
* Adapted to current Das U-Boot source
***********************************************************************/
/************************************************************************
* yucca.h - configuration for AMCC 440SPe Ref (yucca)
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
#define DEBUG
#undef DEBUG
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_440SPE 1 /* Specifc SPe support */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
#define EXTCLK_33_33 33333333
#define EXTCLK_66_66 66666666
#define EXTCLK_50 50000000
#define EXTCLK_83 83333333
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#undef CONFIG_SHOW_BOOT_PROGRESS
#undef CONFIG_STRESS
#undef ENABLE_ECC
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
#define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/
/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */
/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */
/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
#define CFG_FPGA_BASE 0xe2000000 /* epld */
#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
/* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer (placed in internal SRAM)
*----------------------------------------------------------------------*/
#define CFG_TEMP_STACK_OCM 1
#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
#define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_UART1_CONSOLE
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#undef CFG_EXT_SERIAL_CLOCK
/* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */
#define IIC0_DIMM0_ADDR 0x53
#define IIC0_DIMM1_ADDR 0x52
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define IIC0_BOOTPROM_ADDR 0x50
#define IIC0_ALT_BOOTPROM_ADDR 0x54
/* Don't probe these addrs */
#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */
/* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* #endif */
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
/* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"hostname=yucca\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xx\0" \
"bootfile=yucca/uImage\0" \
"kernel_addr=E7F10000\0" \
"ramdisk_addr=E7F20000\0" \
"load=tftp 100000 yuca/u-boot.bin\0" \
"update=protect off 2:4-7;era 2:4-7;" \
"cp.b ${fileaddr} FFFB0000 ${filesize};" \
"setenv filesize;saveenv\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_EEPROM | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_MII 1 /* MII PHY management */
#undef CONFIG_NET_MULTI
#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
#define CONFIG_HAS_ETH0
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET_DELAY 1000
#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_ADDR0 0x5555
#define CFG_FLASH_ADDR1 0x2aaa
#define CFG_FLASH_WORD_SIZE unsigned char
#define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR 0xfffa0000
/* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#undef CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
/*
* NETWORK Support (PCI):
*/
/* Support for Intel 82557/82559/82559ER chips. */
#define CONFIG_EEPRO100
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/* FB Divisor selection */
#define FPGA_FB_DIV_6 6
#define FPGA_FB_DIV_10 10
#define FPGA_FB_DIV_12 12
#define FPGA_FB_DIV_20 20
/* VCO Divisor selection */
#define FPGA_VCO_DIV_4 4
#define FPGA_VCO_DIV_6 6
#define FPGA_VCO_DIV_8 8
#define FPGA_VCO_DIV_10 10
/*----------------------------------------------------------------------------+
| FPGA registers and bit definitions
+----------------------------------------------------------------------------*/
/* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
/* TLB initialization makes it correspond to logical address 0xE2000000. */
/* => Done init_chip.s in bootlib */
#define FPGA_REG_BASE_ADDR 0xE2000000
#define FPGA_GPIO_BASE_ADDR 0xE2010000
#define FPGA_INT_BASE_ADDR 0xE2020000
/*----------------------------------------------------------------------------+
| Display
+----------------------------------------------------------------------------*/
#define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR
#define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06)
#define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04)
#define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02)
#define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00)
/*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
/*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/
/*----------------------------------------------------------------------------+
| ethernet/reset/boot Register 1
+----------------------------------------------------------------------------*/
#define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10)
#define FPGA_REG10_10MHZ_ENABLE 0x8000
#define FPGA_REG10_100MHZ_ENABLE 0x4000
#define FPGA_REG10_GIGABIT_ENABLE 0x2000
#define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/
#define FPGA_REG10_RESET_ETH 0x0800
#define FPGA_REG10_AUTO_NEG_DIS 0x0400
#define FPGA_REG10_INTP_ETH 0x0200
#define FPGA_REG10_RESET_HISR 0x0080
#define FPGA_REG10_ENABLE_DISPLAY 0x0040
#define FPGA_REG10_RESET_SDRAM 0x0020
#define FPGA_REG10_OPER_BOOT 0x0010
#define FPGA_REG10_SRAM_BOOT 0x0008
#define FPGA_REG10_SMALL_BOOT 0x0004
#define FPGA_REG10_FORCE_COLA 0x0002
#define FPGA_REG10_COLA_MANUAL 0x0001
#define FPGA_REG10_SDRAM_ENABLE 0x0020
#define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
#define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
/*----------------------------------------------------------------------------+
| MUX control
+----------------------------------------------------------------------------*/
#define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12)
#define FPGA_REG12_EBC_CTL 0x8000
#define FPGA_REG12_UART1_CTS_RTS 0x4000
#define FPGA_REG12_UART0_RX_ENABLE 0x2000
#define FPGA_REG12_UART1_RX_ENABLE 0x1000
#define FPGA_REG12_UART2_RX_ENABLE 0x0800
#define FPGA_REG12_EBC_OUT_ENABLE 0x0400
#define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200
#define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100
#define FPGA_REG12_GPIO_SELECT 0x0010
#define FPGA_REG12_GPIO_CHREG 0x0008
#define FPGA_REG12_GPIO_CLK_CHREG 0x0004
#define FPGA_REG12_GPIO_OETRI 0x0002
#define FPGA_REG12_EBC_ERROR 0x0001
/*----------------------------------------------------------------------------+
| PCI Clock control
+----------------------------------------------------------------------------*/
#define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16)
#define FPGA_REG16_PCI_CLK_CTL0 0x8000
#define FPGA_REG16_PCI_CLK_CTL1 0x4000
#define FPGA_REG16_PCI_CLK_CTL2 0x2000
#define FPGA_REG16_PCI_CLK_CTL3 0x1000
#define FPGA_REG16_PCI_CLK_CTL4 0x0800
#define FPGA_REG16_PCI_CLK_CTL5 0x0400
#define FPGA_REG16_PCI_CLK_CTL6 0x0200
#define FPGA_REG16_PCI_CLK_CTL7 0x0100
#define FPGA_REG16_PCI_CLK_CTL8 0x0080
#define FPGA_REG16_PCI_CLK_CTL9 0x0040
#define FPGA_REG16_PCI_EXT_ARB0 0x0020
#define FPGA_REG16_PCI_MODE_1 0x0010
#define FPGA_REG16_PCI_TARGET_MODE 0x0008
#define FPGA_REG16_PCI_INTP_MODE 0x0004
/* FB1 Divisor selection */
#define FPGA_REG16_FB2_DIV_MASK 0x1000
#define FPGA_REG16_FB2_DIV_LOW 0x0000
#define FPGA_REG16_FB2_DIV_HIGH 0x1000
/* FB2 Divisor selection */
/* S3 switch on Board */
#define FPGA_REG16_FB1_DIV_MASK 0x2000
#define FPGA_REG16_FB1_DIV_LOW 0x0000
#define FPGA_REG16_FB1_DIV_HIGH 0x2000
/* PCI0 Clock Selection */
/* S3 switch on Board */
#define FPGA_REG16_PCI0_CLK_MASK 0x0c00
#define FPGA_REG16_PCI0_CLK_33_33 0x0000
#define FPGA_REG16_PCI0_CLK_66_66 0x0800
#define FPGA_REG16_PCI0_CLK_100 0x0400
#define FPGA_REG16_PCI0_CLK_133_33 0x0c00
/* VCO Divisor selection */
/* S3 switch on Board */
#define FPGA_REG16_VCO_DIV_MASK 0xc000
#define FPGA_REG16_VCO_DIV_4 0x0000
#define FPGA_REG16_VCO_DIV_8 0x4000
#define FPGA_REG16_VCO_DIV_6 0x8000
#define FPGA_REG16_VCO_DIV_10 0xc000
/* Master Clock Selection */
/* S3, S4 switches on Board */
#define FPGA_REG16_MASTER_CLK_MASK 0x01c0
#define FPGA_REG16_MASTER_CLK_EXT 0x0000
#define FPGA_REG16_MASTER_CLK_66_66 0x0040
#define FPGA_REG16_MASTER_CLK_50 0x0080
#define FPGA_REG16_MASTER_CLK_33_33 0x00c0
#define FPGA_REG16_MASTER_CLK_25 0x0100
/*----------------------------------------------------------------------------+
| PCI Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18)
#define FPGA_REG18_PCI_PRSNT1 0x8000
#define FPGA_REG18_PCI_PRSNT2 0x4000
#define FPGA_REG18_PCI_INTA 0x2000
#define FPGA_REG18_PCI_SLOT0_INTP 0x1000
#define FPGA_REG18_PCI_SLOT1_INTP 0x0800
#define FPGA_REG18_PCI_SLOT2_INTP 0x0400
#define FPGA_REG18_PCI_SLOT3_INTP 0x0200
#define FPGA_REG18_PCI_PCI0_VC 0x0100
#define FPGA_REG18_PCI_PCI0_VTH1 0x0080
#define FPGA_REG18_PCI_PCI0_VTH2 0x0040
#define FPGA_REG18_PCI_PCI0_VTH3 0x0020
/*----------------------------------------------------------------------------+
| PCIe Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A)
#define FPGA_REG1A_PE0_GLED 0x8000
#define FPGA_REG1A_PE1_GLED 0x4000
#define FPGA_REG1A_PE2_GLED 0x2000
#define FPGA_REG1A_PE0_YLED 0x1000
#define FPGA_REG1A_PE1_YLED 0x0800
#define FPGA_REG1A_PE2_YLED 0x0400
#define FPGA_REG1A_PE0_PWRON 0x0200
#define FPGA_REG1A_PE1_PWRON 0x0100
#define FPGA_REG1A_PE2_PWRON 0x0080
#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
#define FPGA_REG1A_PE_SPREAD0 0x0008
#define FPGA_REG1A_PE_SPREAD1 0x0004
#define FPGA_REG1A_PE_SELSOURCE_0 0x0002
#define FPGA_REG1A_PE_SELSOURCE_1 0x0001
/*----------------------------------------------------------------------------+
| PCIe Miscellaneous
+----------------------------------------------------------------------------*/
#define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C)
#define FPGA_REG1C_PE0_ROOTPOINT 0x8000
#define FPGA_REG1C_PE1_ENDPOINT 0x4000
#define FPGA_REG1C_PE2_ENDPOINT 0x2000
#define FPGA_REG1C_PE0_PRSNT 0x1000
#define FPGA_REG1C_PE1_PRSNT 0x0800
#define FPGA_REG1C_PE2_PRSNT 0x0400
#define FPGA_REG1C_PE0_WAKE 0x0080
#define FPGA_REG1C_PE1_WAKE 0x0040
#define FPGA_REG1C_PE2_WAKE 0x0020
#define FPGA_REG1C_PE0_PERST 0x0010
#define FPGA_REG1C_PE1_PERST 0x0080
#define FPGA_REG1C_PE2_PERST 0x0040
/*----------------------------------------------------------------------------+
| Defines
+----------------------------------------------------------------------------*/
#define PERIOD_133_33MHZ 7500 /* 7,5ns */
#define PERIOD_100_00MHZ 10000 /* 10ns */
#define PERIOD_83_33MHZ 12000 /* 12ns */
#define PERIOD_75_00MHZ 13333 /* 13,333ns */
#define PERIOD_66_66MHZ 15000 /* 15ns */
#define PERIOD_50_00MHZ 20000 /* 20ns */
#define PERIOD_33_33MHZ 30000 /* 30ns */
#define PERIOD_25_00MHZ 40000 /* 40ns */
/*---------------------------------------------------------------------------*/
#endif /* __CONFIG_H */

3
include/galileo/core.h
View File

@@ -110,7 +110,10 @@ extern unsigned int INTERNAL_REG_BASE_ADDR;
#define _1G 0x40000000
#define _2G 0x80000000
#ifndef BOOL_WAS_DEFINED
#define BOOL_WAS_DEFINED
typedef enum _bool{false,true} bool;
#endif
/* Little to Big endian conversion macros */

74
include/linux/mtd/nand.h
View File

@@ -2,7 +2,7 @@
* linux/include/linux/mtd/nand.h
*
* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
* Steven J. Hill <sjhill@realitydiluted.com>
* Steven J. Hill <sjhill@realitydiluted.com>
* Thomas Gleixner <tglx@linutronix.de>
*
* $Id: nand.h,v 1.68 2004/11/12 10:40:37 gleixner Exp $
@@ -15,15 +15,15 @@
* Contains standard defines and IDs for NAND flash devices
*
* Changelog:
* 01-31-2000 DMW Created
* 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
* 01-31-2000 DMW Created
* 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
* so it can be used by other NAND flash device
* drivers. I also changed the copyright since none
* of the original contents of this file are specific
* to DoC devices. David can whack me with a baseball
* bat later if I did something naughty.
* 10-11-2000 SJH Added private NAND flash structure for driver
* 10-24-2000 SJH Added prototype for 'nand_scan' function
* 10-11-2000 SJH Added private NAND flash structure for driver
* 10-24-2000 SJH Added prototype for 'nand_scan' function
* 10-29-2001 TG changed nand_chip structure to support
* hardwarespecific function for accessing control lines
* 02-21-2002 TG added support for different read/write adress and
@@ -36,7 +36,7 @@
* CONFIG_MTD_NAND_ECC_JFFS2 is not set
* 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
*
* 08-29-2002 tglx nand_chip structure: data_poi for selecting
* 08-29-2002 tglx nand_chip structure: data_poi for selecting
* internal / fs-driver buffer
* support for 6byte/512byte hardware ECC
* read_ecc, write_ecc extended for different oob-layout
@@ -45,8 +45,8 @@
* 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
* Split manufacturer and device ID structures
*
* 02-08-2004 tglx added option field to nand structure for chip anomalities
* 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
* 02-08-2004 tglx added option field to nand structure for chip anomalities
* 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
* update of nand_chip structure description
*/
#ifndef __LINUX_MTD_NAND_H
@@ -75,7 +75,7 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
* Constants for hardware specific CLE/ALE/NCE function
*/
/* Select the chip by setting nCE to low */
#define NAND_CTL_SETNCE 1
#define NAND_CTL_SETNCE 1
/* Deselect the chip by setting nCE to high */
#define NAND_CTL_CLRNCE 2
/* Select the command latch by setting CLE to high */
@@ -215,7 +215,7 @@ struct nand_chip;
#if 0
/**
* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
* @lock: protection lock
* @lock: protection lock
* @active: the mtd device which holds the controller currently
*/
struct nand_hw_control {
@@ -244,20 +244,20 @@ struct nand_hw_control {
* is read from the chip status register
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
* @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
* @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
* @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
* @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
* be provided if a hardware ECC is available
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
* @scan_bbt: [REPLACEABLE] function to scan bad block table
* @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
* @eccsize: [INTERN] databytes used per ecc-calculation
* @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
* @eccsize: [INTERN] databytes used per ecc-calculation
* @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
* @eccsteps: [INTERN] number of ecc calculation steps per page
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
* @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
* @state: [INTERN] the current state of the NAND device
* @state: [INTERN] the current state of the NAND device
* @page_shift: [INTERN] number of address bits in a page (column address bits)
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
@@ -284,7 +284,7 @@ struct nand_hw_control {
struct nand_chip {
void __iomem *IO_ADDR_R;
void __iomem *IO_ADDR_W;
void __iomem *IO_ADDR_W;
u_char (*read_byte)(struct mtd_info *mtd);
void (*write_byte)(struct mtd_info *mtd, u_char byte);
@@ -297,12 +297,12 @@ struct nand_chip {
void (*select_chip)(struct mtd_info *mtd, int chip);
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
int (*dev_ready)(struct mtd_info *mtd);
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
int (*dev_ready)(struct mtd_info *mtd);
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
void (*enable_hwecc)(struct mtd_info *mtd, int mode);
void (*erase_cmd)(struct mtd_info *mtd, int page);
int (*scan_bbt)(struct mtd_info *mtd);
@@ -310,17 +310,17 @@ struct nand_chip {
int eccsize;
int eccbytes;
int eccsteps;
int chip_delay;
int chip_delay;
#if 0
spinlock_t chip_lock;
wait_queue_head_t wq;
nand_state_t state;
nand_state_t state;
#endif
int page_shift;
int page_shift;
int phys_erase_shift;
int bbt_erase_shift;
int chip_shift;
u_char *data_buf;
u_char *data_buf;
u_char *oob_buf;
int oobdirty;
u_char *data_poi;
@@ -335,7 +335,7 @@ struct nand_chip {
struct nand_bbt_descr *bbt_td;
struct nand_bbt_descr *bbt_md;
struct nand_bbt_descr *badblock_pattern;
struct nand_hw_control *controller;
struct nand_hw_control *controller;
void *priv;
};
@@ -352,14 +352,14 @@ struct nand_chip {
/**
* struct nand_flash_dev - NAND Flash Device ID Structure
*
* @name: Identify the device type
* @id: device ID code
* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
* @name: Identify the device type
* @id: device ID code
* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
* If the pagesize is 0, then the real pagesize
* and the eraseize are determined from the
* extended id bytes in the chip
* @erasesize: Size of an erase block in the flash device.
* @chipsize: Total chipsize in Mega Bytes
* @erasesize: Size of an erase block in the flash device.
* @chipsize: Total chipsize in Mega Bytes
* @options: Bitfield to store chip relevant options
*/
struct nand_flash_dev {
@@ -374,7 +374,7 @@ struct nand_flash_dev {
/**
* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
* @name: Manufacturer name
* @id: manufacturer ID code of device.
* @id: manufacturer ID code of device.
*/
struct nand_manufacturers {
int id;
@@ -398,7 +398,7 @@ extern struct nand_manufacturers nand_manuf_ids[];
* blocks is reserved at the end of the device where the tables are
* written.
* @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
* bad) block in the stored bbt
* bad) block in the stored bbt
* @pattern: pattern to identify bad block table or factory marked good /
* bad blocks, can be NULL, if len = 0
*
@@ -412,11 +412,11 @@ struct nand_bbt_descr {
int pages[NAND_MAX_CHIPS];
int offs;
int veroffs;
uint8_t version[NAND_MAX_CHIPS];
uint8_t version[NAND_MAX_CHIPS];
int len;
int maxblocks;
int maxblocks;
int reserved_block_code;
uint8_t *pattern;
uint8_t *pattern;
};
/* Options for the bad block table descriptors */
@@ -428,7 +428,7 @@ struct nand_bbt_descr {
#define NAND_BBT_4BIT 0x00000004
#define NAND_BBT_8BIT 0x00000008
/* The bad block table is in the last good block of the device */
#define NAND_BBT_LASTBLOCK 0x00000010
#define NAND_BBT_LASTBLOCK 0x00000010
/* The bbt is at the given page, else we must scan for the bbt */
#define NAND_BBT_ABSPAGE 0x00000020
/* The bbt is at the given page, else we must scan for the bbt */
@@ -451,7 +451,7 @@ struct nand_bbt_descr {
#define NAND_BBT_SCAN2NDPAGE 0x00004000
/* The maximum number of blocks to scan for a bbt */
#define NAND_BBT_SCAN_MAXBLOCKS 4
#define NAND_BBT_SCAN_MAXBLOCKS 4
extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);

5
include/nios2-epcs.h
View File

@@ -38,6 +38,11 @@ typedef struct epcs_devinfo_t {
unsigned char prot_mask; /* Protection mask */
}epcs_devinfo_t;
/* Resets the epcs controller -- to prevent (potential) soft-reset
* problems when booting from the epcs controller
*/
extern int epcs_reset (void);
/* Returns the devinfo struct if EPCS device is found;
* NULL otherwise.
*/

22
include/ns16550.h
View File

@@ -7,6 +7,9 @@
* added prototypes for ns16550.c
* reduced no of com ports to 2
* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
*
* added support for port on 64-bit bus
* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
*/
#if (CFG_NS16550_REG_SIZE == 1)
@@ -82,6 +85,25 @@ struct NS16550 {
int pad10:24;
#endif
} __attribute__ ((packed));
#elif (CFG_NS16550_REG_SIZE == -8)
struct NS16550 {
unsigned char rbr; /* 0 */
unsigned char pad0[7];
unsigned char ier; /* 1 */
unsigned char pad1[7];
unsigned char fcr; /* 2 */
unsigned char pad2[7];
unsigned char lcr; /* 3 */
unsigned char pad3[7];
unsigned char mcr; /* 4 */
unsigned char pad4[7];
unsigned char lsr; /* 5 */
unsigned char pad5[7];
unsigned char msr; /* 6 */
unsigned char pad6[7];
unsigned char scr; /* 7 */
unsigned char pad7[7];
} __attribute__ ((packed));
#else
#error "Please define NS16550 registers size."
#endif

10
include/pcmcia.h
View File

@@ -308,4 +308,14 @@ typedef struct {
#endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */
#ifdef CONFIG_8xx
extern u_int *pcmcia_pgcrx[];
#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \
|| defined(CONFIG_PXA_PCMCIA)
extern int check_ide_device(int slot);
#endif
#endif /* _PCMCIA_H */

1296
include/ppc440.h
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File diff suppressed because it is too large Load Diff

26
include/ppc4xx_enet.h
View File

@@ -133,12 +133,21 @@ typedef struct emac_4xx_hw_st {
#define EMAC_NUM_DEV 4
#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
defined(CONFIG_NET_MULTI) && \
!defined(CONFIG_440SP)
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
#define EMAC_NUM_DEV 2
#else
#define EMAC_NUM_DEV 1
#endif
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
#define EMAC_STACR_OC_MASK (0x00008000)
#else
#define EMAC_STACR_OC_MASK (0x00000000)
#endif
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define SDR0_PFC1_EM_1000 (0x00200000)
#endif
/*ZMII Bridge Register addresses */
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
@@ -323,7 +332,7 @@ typedef struct emac_4xx_hw_st {
#define EMAC_M0_WKE (0x04000000)
/* on 440GX EMAC_MR1 has a different layout! */
#if defined(CONFIG_440GX) || defined(CONFIG_440SP)
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/* MODE Reg 1 */
#define EMAC_M1_FDE (0x80000000)
#define EMAC_M1_ILE (0x40000000)
@@ -424,8 +433,21 @@ typedef struct emac_4xx_hw_st {
/* STA CONTROL REG */
#define EMAC_STACR_OC (0x00008000)
#define EMAC_STACR_PHYE (0x00004000)
#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
#define EMAC_STACR_INDIRECT_MODE (0x00002000)
#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
#define EMAC_STACR_READ (0x00001000) /* $BUC */
#define EMAC_STACR_OP_MASK (0x00001800)
#define EMAC_STACR_MDIO_ADDR (0x00000000)
#define EMAC_STACR_MDIO_WRITE (0x00000800)
#define EMAC_STACR_MDIO_READ (0x00001800)
#define EMAC_STACR_MDIO_READ_INC (0x00001000)
#else
#define EMAC_STACR_WRITE (0x00002000)
#define EMAC_STACR_READ (0x00001000)
#endif
#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
#define EMAC_STACR_CLK_66MHZ (0x00000400)
#define EMAC_STACR_CLK_100MHZ (0x00000C00)

34
include/s3c2400.h
View File

@@ -63,71 +63,71 @@ typedef enum {
#include <s3c24x0.h>
static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
{
return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
}
static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
{
return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
}
static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
{
return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
}
static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
{
return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
}
static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
{
return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
}
static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
{
return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
}
static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
{
return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
}
static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
{
return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
}
static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
{
return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
}
static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
{
return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
}
static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
{
return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
}
static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
{
return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
}
static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
{
return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
}
static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
{
return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
}
static inline S3C2400_ADC * const S3C2400_GetBase_ADC(void)
static inline S3C2400_ADC * S3C2400_GetBase_ADC(void)
{
return (S3C2400_ADC * const)S3C24X0_ADC_BASE;
}
static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
{
return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
}
static inline S3C2400_MMC * const S3C2400_GetBase_MMC(void)
static inline S3C2400_MMC * S3C2400_GetBase_MMC(void)
{
return (S3C2400_MMC * const)S3C2400_MMC_BASE;
}

2
include/serial.h
View File

@@ -23,7 +23,7 @@ extern struct serial_device serial_scc_device;
extern struct serial_device * default_serial_console (void);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|| defined(CONFIG_405EP)
|| defined(CONFIG_405EP) || defined(CONFIG_MPC5xxx)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#endif

1
include/usb.h
View File

@@ -108,6 +108,7 @@ struct usb_interface_descriptor {
unsigned char iInterface;
unsigned char no_of_ep;
unsigned char num_altsetting;
unsigned char act_altsetting;
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
} __attribute__ ((packed));

3
include/xyzModem.h
View File

@@ -97,7 +97,10 @@ typedef struct {
#endif
} connection_info_t;
#ifndef BOOL_WAS_DEFINED
#define BOOL_WAS_DEFINED
typedef unsigned int bool;
#endif
#define false 0
#define true 1