* Code cleanup
* Patch by Sascha Hauer, 28 Jun: - add generic support for Motorola i.MX architecture - add support for mx1ads, mx1fs2 and scb9328 boards * Patches by Marc Leeman, 23 Jul 2004: - Add define for the PCI/Memory Buffer Configuration Register - corrected comments in cpu/mpc824x/cpu_init.c * Add support for multiple serial interfaces (for example to allow modem dial-in / dial-out)
This commit is contained in:
wdenk
571
include/asm-arm/arch-arm920t/imx-regs.h
Normal file
571
include/asm-arm/arch-arm920t/imx-regs.h
Normal file
@@ -0,0 +1,571 @@
|
||||
#ifndef _IMX_REGS_H
|
||||
#define _IMX_REGS_H
|
||||
/* ------------------------------------------------------------------------
|
||||
* Motorola IMX system registers
|
||||
* ------------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
|
||||
# ifndef __ASSEMBLY__
|
||||
# define __REG(x) (*((volatile u32 *)(x)))
|
||||
# define __REG2(x,y) \
|
||||
( __builtin_constant_p(y) ? (__REG((x) + (y))) \
|
||||
: (*(volatile u32 *)((u32)&__REG(x) + (y))) )
|
||||
# else
|
||||
# define __REG(x) (x)
|
||||
# define __REG2(x,y) ((x)+(y))
|
||||
#endif
|
||||
|
||||
#define IMX_IO_BASE 0x00200000
|
||||
|
||||
/*
|
||||
* Register BASEs, based on OFFSETs
|
||||
*
|
||||
*/
|
||||
#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
|
||||
#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
|
||||
#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
|
||||
#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
|
||||
#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
|
||||
#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
|
||||
#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
|
||||
#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
|
||||
#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
|
||||
#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
|
||||
#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
|
||||
#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
|
||||
#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
|
||||
#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
|
||||
#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
|
||||
#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
|
||||
#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
|
||||
#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
|
||||
#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
|
||||
#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
|
||||
#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
|
||||
#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
|
||||
#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
|
||||
#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
|
||||
#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
|
||||
#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
|
||||
#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
|
||||
#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
|
||||
#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
|
||||
|
||||
/* SYSCTRL Registers */
|
||||
#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
|
||||
#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
|
||||
#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
|
||||
|
||||
/* Chip Select Registers */
|
||||
#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
|
||||
#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
|
||||
#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
|
||||
#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
|
||||
#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
|
||||
#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
|
||||
#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
|
||||
#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
|
||||
#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
|
||||
#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
|
||||
#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
|
||||
#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
|
||||
#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
|
||||
|
||||
/* SDRAM controller registers */
|
||||
|
||||
#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
|
||||
#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
|
||||
#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
|
||||
#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
|
||||
|
||||
/* PLL registers */
|
||||
#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
|
||||
#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
|
||||
#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
|
||||
#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
|
||||
#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
|
||||
#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
|
||||
|
||||
#define CSCR_MPLL_RESTART (1<<21)
|
||||
|
||||
/*
|
||||
* GPIO Module and I/O Multiplexer
|
||||
* x = 0..3 for reg_A, reg_B, reg_C, reg_D
|
||||
*/
|
||||
#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
|
||||
#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
|
||||
#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
|
||||
#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
|
||||
#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
|
||||
#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
|
||||
#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
|
||||
#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
|
||||
#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
|
||||
#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
|
||||
#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
|
||||
#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
|
||||
#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
|
||||
#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
|
||||
#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
|
||||
#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
|
||||
#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
|
||||
|
||||
#define GPIO_PIN_MASK 0x1f
|
||||
#define GPIO_PORT_MASK (0x3 << 5)
|
||||
|
||||
#define GPIO_PORTA (0<<5)
|
||||
#define GPIO_PORTB (1<<5)
|
||||
#define GPIO_PORTC (2<<5)
|
||||
#define GPIO_PORTD (3<<5)
|
||||
|
||||
#define GPIO_OUT (1<<7)
|
||||
#define GPIO_IN (0<<7)
|
||||
#define GPIO_PUEN (1<<8)
|
||||
|
||||
#define GPIO_PF (0<<9)
|
||||
#define GPIO_AF (1<<9)
|
||||
|
||||
#define GPIO_OCR_MASK (3<<10)
|
||||
#define GPIO_AIN (0<<10)
|
||||
#define GPIO_BIN (1<<10)
|
||||
#define GPIO_CIN (2<<10)
|
||||
#define GPIO_GPIO (3<<10)
|
||||
|
||||
#define GPIO_AOUT (1<<12)
|
||||
#define GPIO_BOUT (1<<13)
|
||||
|
||||
/* assignements for GPIO alternate/primary functions */
|
||||
|
||||
/* FIXME: This list is not completed. The correct directions are
|
||||
* missing on some (many) pins
|
||||
*/
|
||||
#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
|
||||
#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
|
||||
#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
|
||||
#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
|
||||
#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
|
||||
#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
|
||||
#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
|
||||
#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
|
||||
#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
|
||||
#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
|
||||
#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
|
||||
#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
|
||||
#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
|
||||
#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
|
||||
#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
|
||||
#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
|
||||
#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
|
||||
#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
|
||||
#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
|
||||
#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
|
||||
#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
|
||||
#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
|
||||
#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
|
||||
#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
|
||||
#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
|
||||
#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
|
||||
#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
|
||||
#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
|
||||
#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
|
||||
#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
|
||||
#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
|
||||
#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
|
||||
#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
|
||||
#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
|
||||
#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
|
||||
#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
|
||||
#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
|
||||
#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
|
||||
#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
|
||||
#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
|
||||
#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
|
||||
#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
|
||||
#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
|
||||
#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
|
||||
#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
|
||||
#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
|
||||
#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
|
||||
#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
|
||||
#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
|
||||
#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
|
||||
#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
|
||||
#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
|
||||
#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
|
||||
#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
|
||||
#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
|
||||
#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
|
||||
#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
|
||||
#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
|
||||
#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
|
||||
#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
|
||||
#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
|
||||
#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
|
||||
#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
|
||||
#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
|
||||
#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
|
||||
#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
|
||||
#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
|
||||
#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
|
||||
#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
|
||||
#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
|
||||
#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
|
||||
#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
|
||||
#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
|
||||
#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
|
||||
#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
|
||||
#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
|
||||
#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
|
||||
#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
|
||||
#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
|
||||
#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
|
||||
#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
|
||||
#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
|
||||
#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
|
||||
#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
|
||||
#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
|
||||
#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
|
||||
#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
|
||||
#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
|
||||
#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
|
||||
#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
|
||||
#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
|
||||
#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
|
||||
#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
|
||||
#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
|
||||
#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
|
||||
#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
|
||||
#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
|
||||
#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
|
||||
#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
|
||||
#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
|
||||
#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
|
||||
#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
|
||||
#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
|
||||
#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
|
||||
#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
|
||||
#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
|
||||
#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
|
||||
#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
|
||||
#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
|
||||
#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
|
||||
#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
|
||||
#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
|
||||
#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
|
||||
#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
|
||||
#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
|
||||
#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
|
||||
#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
|
||||
#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
|
||||
#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
|
||||
#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
|
||||
#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
|
||||
#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
|
||||
#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
|
||||
#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
|
||||
|
||||
/*
|
||||
* DMA Controller
|
||||
*/
|
||||
#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
|
||||
#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
|
||||
#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
|
||||
#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
|
||||
#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
|
||||
#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
|
||||
#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
|
||||
#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
|
||||
#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
|
||||
#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
|
||||
#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
|
||||
#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
|
||||
#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
|
||||
#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
|
||||
#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
|
||||
#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
|
||||
#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
|
||||
#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
|
||||
#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
|
||||
#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
|
||||
#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
|
||||
#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
|
||||
|
||||
/* TODO: define DMA_REQ lines */
|
||||
|
||||
#define DCR_DRST (1<<1)
|
||||
#define DCR_DEN (1<<0)
|
||||
#define DBTOCR_EN (1<<15)
|
||||
#define DBTOCR_CNT(x) ((x) & 0x7fff )
|
||||
#define CNTR_CNT(x) ((x) & 0xffffff )
|
||||
#define CCR_DMOD_LINEAR ( 0x0 << 12 )
|
||||
#define CCR_DMOD_2D ( 0x1 << 12 )
|
||||
#define CCR_DMOD_FIFO ( 0x2 << 12 )
|
||||
#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
|
||||
#define CCR_SMOD_LINEAR ( 0x0 << 10 )
|
||||
#define CCR_SMOD_2D ( 0x1 << 10 )
|
||||
#define CCR_SMOD_FIFO ( 0x2 << 10 )
|
||||
#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
|
||||
#define CCR_MDIR_DEC (1<<9)
|
||||
#define CCR_MSEL_B (1<<8)
|
||||
#define CCR_DSIZ_32 ( 0x0 << 6 )
|
||||
#define CCR_DSIZ_8 ( 0x1 << 6 )
|
||||
#define CCR_DSIZ_16 ( 0x2 << 6 )
|
||||
#define CCR_SSIZ_32 ( 0x0 << 4 )
|
||||
#define CCR_SSIZ_8 ( 0x1 << 4 )
|
||||
#define CCR_SSIZ_16 ( 0x2 << 4 )
|
||||
#define CCR_REN (1<<3)
|
||||
#define CCR_RPT (1<<2)
|
||||
#define CCR_FRC (1<<1)
|
||||
#define CCR_CEN (1<<0)
|
||||
#define RTOR_EN (1<<15)
|
||||
#define RTOR_CLK (1<<14)
|
||||
#define RTOR_PSC (1<<13)
|
||||
|
||||
/*
|
||||
* LCD Controller
|
||||
*/
|
||||
|
||||
#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
|
||||
|
||||
#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
|
||||
#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
|
||||
#define SIZE_YMAX(y) ( (y) & 0x1ff )
|
||||
|
||||
#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
|
||||
#define VPW_VPW(x) ( (x) & 0x3ff )
|
||||
|
||||
#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
|
||||
#define CPOS_CC1 (1<<31)
|
||||
#define CPOS_CC0 (1<<30)
|
||||
#define CPOS_OP (1<<28)
|
||||
#define CPOS_CXP(x) (((x) & 3ff) << 16)
|
||||
#define CPOS_CYP(y) ((y) & 0x1ff)
|
||||
|
||||
#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
|
||||
#define LCWHB_BK_EN (1<<31)
|
||||
#define LCWHB_CW(w) (((w) & 0x1f) << 24)
|
||||
#define LCWHB_CH(h) (((h) & 0x1f) << 16)
|
||||
#define LCWHB_BD(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
|
||||
#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
|
||||
#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
|
||||
#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
|
||||
|
||||
#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
|
||||
#define PCR_TFT (1<<31)
|
||||
#define PCR_COLOR (1<<30)
|
||||
#define PCR_PBSIZ_1 (0<<28)
|
||||
#define PCR_PBSIZ_2 (1<<28)
|
||||
#define PCR_PBSIZ_4 (2<<28)
|
||||
#define PCR_PBSIZ_8 (3<<28)
|
||||
#define PCR_BPIX_1 (0<<25)
|
||||
#define PCR_BPIX_2 (1<<25)
|
||||
#define PCR_BPIX_4 (2<<25)
|
||||
#define PCR_BPIX_8 (3<<25)
|
||||
#define PCR_BPIX_12 (4<<25)
|
||||
#define PCR_BPIX_16 (4<<25)
|
||||
#define PCR_PIXPOL (1<<24)
|
||||
#define PCR_FLMPOL (1<<23)
|
||||
#define PCR_LPPOL (1<<22)
|
||||
#define PCR_CLKPOL (1<<21)
|
||||
#define PCR_OEPOL (1<<20)
|
||||
#define PCR_SCLKIDLE (1<<19)
|
||||
#define PCR_END_SEL (1<<18)
|
||||
#define PCR_END_BYTE_SWAP (1<<17)
|
||||
#define PCR_REV_VS (1<<16)
|
||||
#define PCR_ACD_SEL (1<<15)
|
||||
#define PCR_ACD(x) (((x) & 0x7f) << 8)
|
||||
#define PCR_SCLK_SEL (1<<7)
|
||||
#define PCR_SHARP (1<<6)
|
||||
#define PCR_PCD(x) ((x) & 0x3f)
|
||||
|
||||
#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
|
||||
#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
|
||||
#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
|
||||
#define HCR_H_WAIT_2(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
|
||||
#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
|
||||
#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
|
||||
#define VCR_V_WAIT_2(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
|
||||
#define POS_POS(x) ((x) & 1f)
|
||||
|
||||
#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
|
||||
#define LSCR1_GRAY1(x) (((x) & 0xf) << 4)
|
||||
#define LSCR1_GRAY2(x) ((x) & 0xf)
|
||||
|
||||
#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
|
||||
#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
|
||||
#define PWMR_LDMSK (1<<15)
|
||||
#define PWMR_SCR1 (1<<10)
|
||||
#define PWMR_SCR0 (1<<9)
|
||||
#define PWMR_CC_EN (1<<8)
|
||||
#define PWMR_PW(x) ((x) & 0xff)
|
||||
|
||||
#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
|
||||
#define DMACR_BURST (1<<31)
|
||||
#define DMACR_HM(x) (((x) & 0xf) << 16)
|
||||
#define DMACR_TM(x) ((x) &0xf)
|
||||
|
||||
#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
|
||||
#define RMCR_LCDC_EN (1<<1)
|
||||
#define RMCR_SELF_REF (1<<0)
|
||||
|
||||
#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
|
||||
#define LCDICR_INT_SYN (1<<2)
|
||||
#define LCDICR_INT_CON (1)
|
||||
|
||||
#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
|
||||
#define LCDISR_UDR_ERR (1<<3)
|
||||
#define LCDISR_ERR_RES (1<<2)
|
||||
#define LCDISR_EOF (1<<1)
|
||||
#define LCDISR_BOF (1<<0)
|
||||
/*
|
||||
* UART Module
|
||||
*/
|
||||
#define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */
|
||||
#define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */
|
||||
#define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */
|
||||
#define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */
|
||||
#define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */
|
||||
#define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */
|
||||
#define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */
|
||||
#define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */
|
||||
#define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */
|
||||
#define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */
|
||||
#define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */
|
||||
#define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */
|
||||
#define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */
|
||||
#define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */
|
||||
#define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */
|
||||
#define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */
|
||||
#define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */
|
||||
#define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */
|
||||
#define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */
|
||||
#define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */
|
||||
#define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */
|
||||
#define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */
|
||||
#define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */
|
||||
|
||||
/* UART Control Register Bit Fields.*/
|
||||
#define URXD_CHARRDY (1<<15)
|
||||
#define URXD_ERR (1<<14)
|
||||
#define URXD_OVRRUN (1<<13)
|
||||
#define URXD_FRMERR (1<<12)
|
||||
#define URXD_BRK (1<<11)
|
||||
#define URXD_PRERR (1<<10)
|
||||
#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
|
||||
#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
|
||||
#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
|
||||
#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
|
||||
#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
|
||||
#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
|
||||
#define UCR1_IREN (1<<7) /* Infrared interface enable */
|
||||
#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
|
||||
#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
|
||||
#define UCR1_SNDBRK (1<<4) /* Send break */
|
||||
#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
|
||||
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
|
||||
#define UCR1_DOZE (1<<1) /* Doze */
|
||||
#define UCR1_UARTEN (1<<0) /* UART enabled */
|
||||
#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
|
||||
#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
|
||||
#define UCR2_CTSC (1<<13) /* CTS pin control */
|
||||
#define UCR2_CTS (1<<12) /* Clear to send */
|
||||
#define UCR2_ESCEN (1<<11) /* Escape enable */
|
||||
#define UCR2_PREN (1<<8) /* Parity enable */
|
||||
#define UCR2_PROE (1<<7) /* Parity odd/even */
|
||||
#define UCR2_STPB (1<<6) /* Stop */
|
||||
#define UCR2_WS (1<<5) /* Word size */
|
||||
#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
|
||||
#define UCR2_TXEN (1<<2) /* Transmitter enabled */
|
||||
#define UCR2_RXEN (1<<1) /* Receiver enabled */
|
||||
#define UCR2_SRST (1<<0) /* SW reset */
|
||||
#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
|
||||
#define UCR3_PARERREN (1<<12) /* Parity enable */
|
||||
#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
|
||||
#define UCR3_DSR (1<<10) /* Data set ready */
|
||||
#define UCR3_DCD (1<<9) /* Data carrier detect */
|
||||
#define UCR3_RI (1<<8) /* Ring indicator */
|
||||
#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
|
||||
#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
|
||||
#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
|
||||
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
|
||||
#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
|
||||
#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
|
||||
#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
|
||||
#define UCR3_BPEN (1<<0) /* Preset registers enable */
|
||||
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
|
||||
#define UCR4_INVR (1<<9) /* Inverted infrared reception */
|
||||
#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
|
||||
#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
|
||||
#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
|
||||
#define UCR4_IRSC (1<<5) /* IR special case */
|
||||
#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
|
||||
#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
|
||||
#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
|
||||
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
|
||||
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
|
||||
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
|
||||
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
|
||||
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
|
||||
#define USR1_RTSS (1<<14) /* RTS pin status */
|
||||
#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
|
||||
#define USR1_RTSD (1<<12) /* RTS delta */
|
||||
#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
|
||||
#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
|
||||
#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
|
||||
#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
|
||||
#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
|
||||
#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
|
||||
#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
|
||||
#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
|
||||
#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
|
||||
#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
|
||||
#define USR2_IDLE (1<<12) /* Idle condition */
|
||||
#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
|
||||
#define USR2_WAKE (1<<7) /* Wake */
|
||||
#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
|
||||
#define USR2_TXDC (1<<3) /* Transmitter complete */
|
||||
#define USR2_BRCD (1<<2) /* Break condition */
|
||||
#define USR2_ORE (1<<1) /* Overrun error */
|
||||
#define USR2_RDR (1<<0) /* Recv data ready */
|
||||
#define UTS_FRCPERR (1<<13) /* Force parity error */
|
||||
#define UTS_LOOP (1<<12) /* Loop tx and rx */
|
||||
#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
|
||||
#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
|
||||
#define UTS_TXFULL (1<<4) /* TxFIFO full */
|
||||
#define UTS_RXFULL (1<<3) /* RxFIFO full */
|
||||
#define UTS_SOFTRST (1<<0) /* Software reset */
|
||||
|
||||
/* General purpose timers registers */
|
||||
#define TCTL1 __REG(IMX_TIM1_BASE)
|
||||
#define TPRER1 __REG(IMX_TIM1_BASE + 0x4)
|
||||
#define TCMP1 __REG(IMX_TIM1_BASE + 0x8)
|
||||
#define TCR1 __REG(IMX_TIM1_BASE + 0xc)
|
||||
#define TCN1 __REG(IMX_TIM1_BASE + 0x10)
|
||||
#define TSTAT1 __REG(IMX_TIM1_BASE + 0x14)
|
||||
#define TCTL2 __REG(IMX_TIM2_BASE)
|
||||
#define TPRER2 __REG(IMX_TIM2_BASE + 0x4)
|
||||
#define TCMP2 __REG(IMX_TIM2_BASE + 0x8)
|
||||
#define TCR2 __REG(IMX_TIM2_BASE + 0xc)
|
||||
#define TCN2 __REG(IMX_TIM2_BASE + 0x10)
|
||||
#define TSTAT2 __REG(IMX_TIM2_BASE + 0x14)
|
||||
|
||||
/* General purpose timers bitfields */
|
||||
#define TCTL_SWR (1<<15) /* Software reset */
|
||||
#define TCTL_FRR (1<<8) /* Freerun / restart */
|
||||
#define TCTL_CAP (3<<6) /* Capture Edge */
|
||||
#define TCTL_OM (1<<5) /* output mode */
|
||||
#define TCTL_IRQEN (1<<4) /* interrupt enable */
|
||||
#define TCTL_CLKSOURCE (7<<1) /* Clock source */
|
||||
#define TCTL_TEN (1) /* Timer enable */
|
||||
#define TPRER_PRES (0xff) /* Prescale */
|
||||
#define TSTAT_CAPT (1<<1) /* Capture event */
|
||||
#define TSTAT_COMP (1) /* Compare event */
|
||||
|
||||
#endif /* _IMX_REGS_H */
|
||||
@@ -126,6 +126,17 @@ typedef void (interrupt_handler_t)(void *);
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SERIAL_MULTI
|
||||
|
||||
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \
|
||||
|| defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
|
||||
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
|
||||
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_SERIAL_MULTI */
|
||||
|
||||
/*
|
||||
* General Purpose Utilities
|
||||
@@ -403,6 +414,15 @@ ulong get_PLLCLK (void);
|
||||
#if defined CONFIG_INCA_IP
|
||||
uint incaip_get_cpuclk (void);
|
||||
#endif
|
||||
#if defined(CONFIG_IMX)
|
||||
ulong get_systemPLLCLK(void);
|
||||
ulong get_FCLK(void);
|
||||
ulong get_HCLK(void);
|
||||
ulong get_BCLK(void);
|
||||
ulong get_PERCLK1(void);
|
||||
ulong get_PERCLK2(void);
|
||||
ulong get_PERCLK3(void);
|
||||
#endif
|
||||
ulong get_bus_freq (ulong);
|
||||
|
||||
#if defined(CONFIG_MPC85xx)
|
||||
|
||||
@@ -74,9 +74,10 @@
|
||||
#define CPM_I2C_BASE 0x0820
|
||||
#define CPM_SPI_BASE 0x0840
|
||||
#define CPM_FEC_BASE 0x0860
|
||||
#define CPM_WLKBD_BASE 0x0880
|
||||
#define CPM_SERIAL2_BASE 0x0880
|
||||
#define CPM_SCC_BASE 0x0900
|
||||
#define CPM_POST_BASE 0x0980
|
||||
#define CPM_WLKBD_BASE 0x0a00
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1041,7 +1042,7 @@ typedef struct scc_enet {
|
||||
|
||||
/*** LWMON **********************************************************/
|
||||
|
||||
#if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
|
||||
#if defined(CONFIG_LWMON)
|
||||
/* Bits in parallel I/O port registers that have to be set/cleared
|
||||
* to configure the pins for SCC2 use.
|
||||
*/
|
||||
|
||||
@@ -43,6 +43,9 @@
|
||||
* CONFIG_PPCHAMELEON_CLK_25
|
||||
* CONFIG_PPCHAMELEON_CLK_33
|
||||
*/
|
||||
#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
|
||||
#define CONFIG_PPCHAMELEON_CLK_33
|
||||
#endif
|
||||
|
||||
#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
|
||||
#error "* Two external frequencies (SysClk) are defined! *"
|
||||
@@ -74,11 +77,11 @@
|
||||
|
||||
|
||||
#ifdef CONFIG_PPCHAMELEON_CLK_25
|
||||
#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
|
||||
# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
|
||||
#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
# define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
#else
|
||||
#error "* External frequency (SysClk) not defined! *"
|
||||
# error "* External frequency (SysClk) not defined! *"
|
||||
#endif
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
@@ -64,6 +64,7 @@
|
||||
* Video console
|
||||
*/
|
||||
#if 1
|
||||
#define CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_SED13806
|
||||
#define CONFIG_VIDEO_SED13806_16BPP
|
||||
|
||||
|
||||
@@ -47,11 +47,9 @@
|
||||
|
||||
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
|
||||
|
||||
#if 1
|
||||
#define CONFIG_SERIAL_MULTI 1
|
||||
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
|
||||
#else
|
||||
#define CONFIG_8xx_CONS_SCC2
|
||||
#endif
|
||||
#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
|
||||
|
||||
@@ -151,17 +149,6 @@
|
||||
#define CFG_CMD_POST_DIAG 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_8xx_CONS_SCC2 /* Can't use ethernet, then */
|
||||
#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_BMP | \
|
||||
CFG_CMD_POST_DIAG )
|
||||
#else
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
@@ -172,7 +159,6 @@
|
||||
CFG_CMD_BSP | \
|
||||
CFG_CMD_BMP | \
|
||||
CFG_CMD_POST_DIAG )
|
||||
#endif
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
|
||||
@@ -16,7 +16,7 @@
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
@@ -25,7 +25,6 @@
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
@@ -40,14 +39,19 @@
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
|
||||
#define CONFIG_MC9328 1 /* It's a Motorola MC9328 SoC */
|
||||
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
|
||||
#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */
|
||||
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*/
|
||||
#define CONFIG_IMX_SERIAL1 /* internal uart 1 */
|
||||
/* #define _CONFIG_UART2 */ /* internal uart 2 */
|
||||
/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */
|
||||
|
||||
#define BOARD_LATE_INIT 1
|
||||
|
||||
|
||||
#define USE_920T_MMU 1
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#if 0
|
||||
#define CFG_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
|
||||
@@ -60,6 +64,8 @@
|
||||
*/
|
||||
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
@@ -67,13 +73,13 @@
|
||||
*/
|
||||
#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
|
||||
#define CS8900_BASE 0x15000300
|
||||
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
|
||||
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_UART1 1
|
||||
/* #define CONFIG_UART1 */
|
||||
/* #define CONFIG_UART2 1 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
@@ -85,24 +91,20 @@
|
||||
#define CONFIG_COMMANDS \
|
||||
(CONFIG_CMD_DFL | \
|
||||
CFG_CMD_CACHE | \
|
||||
/*CFG_CMD_NAND |*/ \
|
||||
/*CFG_CMD_EEPROM |*/ \
|
||||
/*CFG_CMD_I2C |*/ \
|
||||
/*CFG_CMD_USB |*/ \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_ELF)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS "root=/dev/docbp mem=48M"
|
||||
#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
|
||||
#define CONFIG_ETHADDR 08:00:3e:26:0a:5c
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 192.168.0.22
|
||||
#define CONFIG_SERVERIP 192.168.0.11
|
||||
#define CONFIG_BOOTFILE "mx1ads"
|
||||
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
|
||||
#define CONFIG_BOOTCOMMAND "tftp; bootm"
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
@@ -114,10 +116,10 @@
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
#define CFG_HUSH_PARSER 1
|
||||
#define CFG_HUSH_PARSER 1
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
|
||||
@@ -125,21 +127,20 @@
|
||||
#define CFG_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
|
||||
#endif
|
||||
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
|
||||
/* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x09000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x08800000 /* default load address */
|
||||
|
||||
|
||||
#define CFG_HZ 1000
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
#define CFG_LOAD_ADDR 0x08800000 /* default load address */
|
||||
/*#define CFG_HZ 1000 */
|
||||
#define CFG_HZ 3686400
|
||||
#define CFG_CPUSPEED 0x141
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
@@ -159,27 +160,35 @@
|
||||
* Physical Memory Map
|
||||
*/
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
|
||||
#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
|
||||
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
|
||||
#define CFG_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
|
||||
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
|
||||
#define CONFIG_SYNCFLASH 1
|
||||
#define PHYS_FLASH_SIZE 0x01000000
|
||||
#define CFG_MAX_FLASH_SECT (16)
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff0000)
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00ff8000)
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x0f000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_SECT_SIZE 0x100000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Enable passing ATAGS
|
||||
*/
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
291
include/configs/mx1fs2.h
Normal file
291
include/configs/mx1fs2.h
Normal file
@@ -0,0 +1,291 @@
|
||||
/*
|
||||
* Copyright (C) 2004 Sascha Hauer, Pengutronix
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
|
||||
#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
|
||||
#define CONFIG_MX1FS2 1 /* on a mx1fs2 board */
|
||||
#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
|
||||
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*/
|
||||
#undef _CONFIG_UART1 /* internal uart 1 */
|
||||
#define _CONFIG_UART2 /* internal uart 2 */
|
||||
#undef _CONFIG_UART3 /* internal uart 3 */
|
||||
#undef _CONFIG_UART4 /* internal uart 4 */
|
||||
#undef CONFIG_SILENT_CONSOLE /* use this to disable output */
|
||||
|
||||
/*
|
||||
* Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
|
||||
* neccessary in include/cmd_confdefs.h file. (Un)comment for getting
|
||||
* functionality or size of u-boot code.
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||
& ~CFG_CMD_LOADS \
|
||||
& ~CFG_CMD_CONSOLE \
|
||||
& ~CFG_CMD_AUTOSCRIPT \
|
||||
& ~CFG_CMD_NET \
|
||||
& ~CFG_CMD_PING \
|
||||
& ~CFG_CMD_DHCP \
|
||||
| CFG_CMD_JFFS2 \
|
||||
)
|
||||
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Boot options. Setting delay to -1 stops autostart count down.
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 10
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2"
|
||||
#define CONFIG_BOOTCOMMAND "bootm 10080000"
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
/*
|
||||
* General options for u-boot. Modify to save memory foot print
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef saves memory */
|
||||
#define CFG_PROMPT "mx1fs2> " /* prompt string */
|
||||
#define CFG_CBSIZE 256 /* console I/O buffer */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */
|
||||
#define CFG_MAXARGS 16 /* max command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x08100000 /* memtest test area */
|
||||
#define CFG_MEMTEST_END 0x08F00000
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */
|
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
||||
#define CFG_CPUSPEED 0x141 /* core clock - register value */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
/*
|
||||
* Definitions related to passing arguments to kernel.
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
|
||||
#define CONFIG_INITRD_TAG 1 /* send initrd params */
|
||||
#undef CONFIG_VFD /* do not send framebuffer setup */
|
||||
|
||||
#define CFG_JFFS_CUSTOM_PART
|
||||
/*
|
||||
* Malloc pool need to host env + 128 Kb reserve for other allocations.
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) )
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (120<<10) /* stack size */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/* SDRAM Setup Values
|
||||
* 0x910a8300 Precharge Command CAS 3
|
||||
* 0x910a8200 Precharge Command CAS 2
|
||||
*
|
||||
* 0xa10a8300 AutoRefresh Command CAS 3
|
||||
* 0xa10a8200 Set AutoRefresh Command CAS 2
|
||||
*/
|
||||
#define PRECHARGE_CMD 0x910a8300
|
||||
#define AUTOREFRESH_CMD 0xa10a8300
|
||||
|
||||
#define CONFIG_INIT_CRITICAL
|
||||
|
||||
#define BUS32BIT_VERSION
|
||||
/*
|
||||
* SDRAM Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */
|
||||
#ifdef BUS32BIT_VERSION
|
||||
#define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */
|
||||
#else
|
||||
#define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */
|
||||
#endif
|
||||
/*
|
||||
* Flash Controller settings
|
||||
*/
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
|
||||
#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
|
||||
|
||||
#ifdef BUS32BIT_VERSION
|
||||
#define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
|
||||
#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
|
||||
#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/
|
||||
#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
|
||||
#define MX1FS2_JFFS2_PART0_START 0x10200000
|
||||
#define MX1FS2_JFFS2_PART0_SIZE 0x00500000
|
||||
#define MX1FS2_JFFS2_PART1_START 0x10700000
|
||||
#define MX1FS2_JFFS2_PART1_SIZE 0x00900000
|
||||
#else
|
||||
#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
|
||||
#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
|
||||
#define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/
|
||||
#define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */
|
||||
#endif
|
||||
#define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */
|
||||
#define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */
|
||||
|
||||
/* This should be defined if CFI FLASH device is present. Actually benefit
|
||||
is not so clear to me. In other words we can provide more informations
|
||||
to user, but this expects more complex flash handling we do not provide
|
||||
now.*/
|
||||
#undef CFG_FLASH_CFI
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */
|
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */
|
||||
|
||||
#define CFG_FLASH_BASE MX1FS2_FLASH_BASE
|
||||
|
||||
/*
|
||||
* This is setting for JFFS2 support in u-boot.
|
||||
* Right now there is no gain for user, but later on booting kernel might be
|
||||
* possible. Consider using XIP kernel running from flash to save RAM
|
||||
* footprint.
|
||||
* NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
|
||||
*/
|
||||
#define CFG_JFFS2_FIRST_BANK 0
|
||||
#define CFG_JFFS2_FIRST_SECTOR 5
|
||||
#define CFG_JFFS2_NUM_BANKS 1
|
||||
|
||||
/*
|
||||
* Environment setup. Definitions of monitor location and size with
|
||||
* definition of environment setup ends up in 2 possibilities.
|
||||
* 1. Embeded environment - in u-boot code is space for environment
|
||||
* 2. Environment is read from predefined sector of flash
|
||||
* Right now we support 2. possiblity, but expecting no env placed
|
||||
* on mentioned address right now. This also needs to provide whole
|
||||
* sector for it - for us 256Kb is really waste of memory. U-boot uses
|
||||
* default env. and until kernel parameters could be sent to kernel
|
||||
* env. has no sense to us.
|
||||
*/
|
||||
|
||||
#define CFG_MONITOR_BASE 0x10000000
|
||||
#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */
|
||||
#define CFG_ENV_SIZE 0x20000
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
|
||||
|
||||
/* Setup CS4 and CS5 */
|
||||
#define CFG_GIUS_A_VAL 0x0003fffe
|
||||
|
||||
/*
|
||||
* CSxU_VAL:
|
||||
* 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
|
||||
* |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
|
||||
*
|
||||
* CSxL_VAL:
|
||||
* 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
|
||||
* | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
|
||||
*/
|
||||
|
||||
#define CFG_CS0U_VAL 0x00008C00
|
||||
#define CFG_CS0L_VAL 0x22222601
|
||||
#define CFG_CS1U_VAL 0x00008C00
|
||||
#define CFG_CS1L_VAL 0x22222301
|
||||
#define CFG_CS4U_VAL 0x00008C00
|
||||
#define CFG_CS4L_VAL 0x22222301
|
||||
#define CFG_CS5U_VAL 0x00008C00
|
||||
#define CFG_CS5L_VAL 0x22222301
|
||||
|
||||
/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
|
||||
f_ref=16,777MHz
|
||||
|
||||
0x002a141f: 191,9944MHz
|
||||
0x040b2007: 144MHz
|
||||
0x042a141f: 96MHz
|
||||
0x0811140d: 64MHz
|
||||
0x040e200e: 150MHz
|
||||
0x00321431: 200MHz
|
||||
|
||||
0x08001800: 64MHz mit 16er Quarz
|
||||
0x04001800: 96MHz mit 16er Quarz
|
||||
0x04002400: 144MHz mit 16er Quarz
|
||||
|
||||
31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
|
||||
|XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
|
||||
|
||||
#define CFG_MPCTL0_VAL 0x07E723AD
|
||||
#define CFG_MPCTL1_VAL 0x00000040
|
||||
#define CFG_PCDR_VAL 0x00010005
|
||||
#define CFG_GPCR_VAL 0x00000FFB
|
||||
|
||||
#define USE_16M_OSZI /* If you have one, you want to use it
|
||||
The internal 32kHz oszillator jitters */
|
||||
#ifdef USE_16M_OSZI
|
||||
|
||||
#define CFG_SPCTL0_VAL 0x04001401
|
||||
#define CFG_SPCTL1_VAL 0x0C000040
|
||||
#define CFG_CSCR_VAL 0x07030003
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16000000
|
||||
|
||||
#else
|
||||
|
||||
#define CFG_SPCTL0_VAL 0x07E716D1
|
||||
#define CFG_CSCR_VAL 0x06000003
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16780000
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Well this has to be defined, but on the other hand it is used differently
|
||||
* one may expect. For instance loadb command do not cares :-)
|
||||
* So advice is - do not relay on this...
|
||||
*/
|
||||
#define CFG_LOAD_ADDR 0x08400000
|
||||
|
||||
#define CFG_FMCR_VAL 0x00000003 /* Reset Default */
|
||||
|
||||
/* Bit[0:3] contain PERCLK1DIV for UART 1
|
||||
0x000b00b ->b<- -> 192MHz/12=16MHz
|
||||
0x000b00b ->8<- -> 144MHz/09=16MHz
|
||||
0x000b00b ->3<- -> 64MHz/4=16MHz */
|
||||
|
||||
#ifdef _CONFIG_UART1
|
||||
#define CONFIG_IMX_SERIAL1
|
||||
#elif defined _CONFIG_UART2
|
||||
#define CONFIG_IMX_SERIAL2
|
||||
#elif defined _CONFIG_UART3 | defined _CONFIG_UART4
|
||||
#define CONFIG_IMX_SERIAL_NONE
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_CLK 3686400
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#ifdef _CONFIG_UART3
|
||||
#define CFG_NS16550_COM1 0x15000000
|
||||
#elif defined _CONFIG_UART4
|
||||
#define CFG_NS16550_COM1 0x16000000
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
357
include/configs/scb9328.h
Normal file
357
include/configs/scb9328.h
Normal file
@@ -0,0 +1,357 @@
|
||||
/*
|
||||
* Copyright (C) 2003 ETC s.r.o.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Written by Peter Figuli <peposh@etc.sk>, 2003.
|
||||
*
|
||||
* 2003/13/06 Initial MP10 Support copied from wepep250
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
|
||||
#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
|
||||
#define CONFIG_SCB9328 1 /* on a scb9328tronix board */
|
||||
#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
|
||||
|
||||
#define CONFIG_IMX_SERIAL1
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
|
||||
* neccessary in include/cmd_confdefs.h file. (Un)comment for getting
|
||||
* functionality or size of u-boot code.
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||
& ~CFG_CMD_LOADS \
|
||||
& ~CFG_CMD_CONSOLE \
|
||||
& ~CFG_CMD_AUTOSCRIPT \
|
||||
| CFG_CMD_NET \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_DHCP \
|
||||
)
|
||||
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Boot options. Setting delay to -1 stops autostart count down.
|
||||
* NOTE: Sending parameters to kernel depends on kernel version and
|
||||
* 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
|
||||
* parameters at all! Do not get confused by them so.
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
#define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
|
||||
#define CONFIG_BOOTCOMMAND "bootm 10040000"
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
#define CONFIG_ETHADDR 80:81:82:83:84:85
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 10.10.10.9
|
||||
#define CONFIG_SERVERIP 10.10.10.10
|
||||
|
||||
/*
|
||||
* General options for u-boot. Modify to save memory foot print
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef saves memory */
|
||||
#define CFG_PROMPT "scb9328> " /* prompt string */
|
||||
#define CFG_CBSIZE 256 /* console I/O buffer */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */
|
||||
#define CFG_MAXARGS 16 /* max command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x08100000 /* memtest test area */
|
||||
#define CFG_MEMTEST_END 0x08F00000
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */
|
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
||||
#define CFG_CPUSPEED 0x141 /* core clock - register value */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
/*
|
||||
* Definitions related to passing arguments to kernel.
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
|
||||
#define CONFIG_INITRD_TAG 1 /* send initrd params */
|
||||
#undef CONFIG_VFD /* do not send framebuffer setup */
|
||||
|
||||
|
||||
/*
|
||||
* Malloc pool need to host env + 128 Kb reserve for other allocations.
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) )
|
||||
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (120<<10) /* stack size */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/* SDRAM Setup Values
|
||||
0x910a8300 Precharge Command CAS 3
|
||||
0x910a8200 Precharge Command CAS 2
|
||||
|
||||
0xa10a8300 AutoRefresh Command CAS 3
|
||||
0xa10a8200 Set AutoRefresh Command CAS 2 */
|
||||
|
||||
#define PRECHARGE_CMD 0x910a8200
|
||||
#define AUTOREFRESH_CMD 0xa10a8200
|
||||
#define CONFIG_INIT_CRITICAL
|
||||
|
||||
/*
|
||||
* SDRAM Memory Map
|
||||
*/
|
||||
/* SH FIXME */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
|
||||
#define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
|
||||
|
||||
/*
|
||||
* Flash Controller settings
|
||||
*/
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Configuration for FLASH memory for the Synertronixx board
|
||||
*/
|
||||
|
||||
/* #define SCB9328_FLASH_32M */
|
||||
|
||||
/* 32MB */
|
||||
#ifdef SCB9328_FLASH_32M
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
|
||||
#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
|
||||
#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
|
||||
#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
|
||||
#define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
|
||||
#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
|
||||
#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
|
||||
#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
|
||||
#else
|
||||
|
||||
/* 16MB */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
|
||||
#define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
|
||||
#define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
|
||||
#define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
|
||||
#define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
|
||||
#define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
|
||||
#define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
|
||||
#define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
|
||||
#endif /* SCB9328_FLASH_32M */
|
||||
|
||||
/* This should be defined if CFI FLASH device is present. Actually benefit
|
||||
is not so clear to me. In other words we can provide more informations
|
||||
to user, but this expects more complex flash handling we do not provide
|
||||
now.*/
|
||||
#undef CFG_FLASH_CFI
|
||||
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */
|
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */
|
||||
|
||||
#define CFG_FLASH_BASE SCB9328_FLASH_BASE
|
||||
|
||||
/*
|
||||
* This is setting for JFFS2 support in u-boot.
|
||||
* Right now there is no gain for user, but later on booting kernel might be
|
||||
* possible. Consider using XIP kernel running from flash to save RAM
|
||||
* footprint.
|
||||
* NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
|
||||
*/
|
||||
#define CFG_JFFS2_FIRST_BANK 0
|
||||
#define CFG_JFFS2_FIRST_SECTOR 5
|
||||
#define CFG_JFFS2_NUM_BANKS 1
|
||||
|
||||
/*
|
||||
* Environment setup. Definitions of monitor location and size with
|
||||
* definition of environment setup ends up in 2 possibilities.
|
||||
* 1. Embeded environment - in u-boot code is space for environment
|
||||
* 2. Environment is read from predefined sector of flash
|
||||
* Right now we support 2. possiblity, but expecting no env placed
|
||||
* on mentioned address right now. This also needs to provide whole
|
||||
* sector for it - for us 256Kb is really waste of memory. U-boot uses
|
||||
* default env. and until kernel parameters could be sent to kernel
|
||||
* env. has no sense to us.
|
||||
*/
|
||||
|
||||
/* Setup for PA23 which is Reset Default PA23 but has to become
|
||||
CS5 */
|
||||
|
||||
#define CFG_GPR_A_VAL 0x00800000
|
||||
#define CFG_GIUS_A_VAL 0x0043fffe
|
||||
|
||||
#define CFG_MONITOR_BASE 0x10000000
|
||||
#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */
|
||||
#define CFG_ENV_SIZE 0x20000
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
|
||||
|
||||
/*
|
||||
* CSxU_VAL:
|
||||
* 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
|
||||
* |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
|
||||
*
|
||||
* CSxL_VAL:
|
||||
* 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
|
||||
* | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
|
||||
*/
|
||||
|
||||
#define CFG_CS0U_VAL 0x000F2000
|
||||
#define CFG_CS0L_VAL 0x11110d01
|
||||
#define CFG_CS1U_VAL 0x000F0a00
|
||||
#define CFG_CS1L_VAL 0x11110601
|
||||
#define CFG_CS2U_VAL 0x0
|
||||
#define CFG_CS2L_VAL 0x0
|
||||
|
||||
#define CFG_CS3U_VAL 0x000FFFFF
|
||||
#define CFG_CS3L_VAL 0x00000303
|
||||
|
||||
#define CFG_CS4U_VAL 0x000F0a00
|
||||
#define CFG_CS4L_VAL 0x11110301
|
||||
|
||||
/* CNC == 3 too long
|
||||
#define CFG_CS5U_VAL 0x0000C210 */
|
||||
|
||||
/* #define CFG_CS5U_VAL 0x00008400
|
||||
mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
|
||||
kaum langsamer ist */
|
||||
/* #define CFG_CS5U_VAL 0x00009400
|
||||
#define CFG_CS5L_VAL 0x11010D03 */
|
||||
|
||||
#define CFG_CS5U_VAL 0x00008400
|
||||
#define CFG_CS5L_VAL 0x00000D03
|
||||
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
#define CONFIG_DM9000_BASE 0x16000000
|
||||
#define DM9000_IO CONFIG_DM9000_BASE
|
||||
#define DM9000_DATA (CONFIG_DM9000_BASE+4)
|
||||
/* #define CONFIG_DM9000_USE_8BIT */
|
||||
#define CONFIG_DM9000_USE_16BIT
|
||||
/* #define CONFIG_DM9000_USE_32BIT */
|
||||
|
||||
/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
|
||||
f_ref=16,777MHz
|
||||
|
||||
0x002a141f: 191,9944MHz
|
||||
0x040b2007: 144MHz
|
||||
0x042a141f: 96MHz
|
||||
0x0811140d: 64MHz
|
||||
0x040e200e: 150MHz
|
||||
0x00321431: 200MHz
|
||||
|
||||
0x08001800: 64MHz mit 16er Quarz
|
||||
0x04001800: 96MHz mit 16er Quarz
|
||||
0x04002400: 144MHz mit 16er Quarz
|
||||
|
||||
31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
|
||||
|XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
|
||||
|
||||
#define CPU200
|
||||
|
||||
#ifdef CPU200
|
||||
#define CFG_MPCTL0_VAL 0x00321431
|
||||
#else
|
||||
#define CFG_MPCTL0_VAL 0x040e200e
|
||||
#endif
|
||||
|
||||
/* #define BUS64 */
|
||||
#define BUS72
|
||||
|
||||
#ifdef BUS72
|
||||
#define CFG_SPCTL0_VAL 0x04002400
|
||||
#endif
|
||||
|
||||
#ifdef BUS96
|
||||
#define CFG_SPCTL0_VAL 0x04001800
|
||||
#endif
|
||||
|
||||
#ifdef BUS64
|
||||
#define CFG_SPCTL0_VAL 0x08001800
|
||||
#endif
|
||||
|
||||
/* Das ist der BCLK Divider, der aus der System PLL
|
||||
BCLK und HCLK erzeugt:
|
||||
31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
|
||||
0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
|
||||
0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
|
||||
0x2f001003 : 192MHz/5=38,4MHz
|
||||
0x2f000003 : 64MHz/1
|
||||
Bit 22: SPLL Restart
|
||||
Bit 21: MPLL Restart */
|
||||
|
||||
#ifdef BUS64
|
||||
#define CFG_CSCR_VAL 0x2f030003
|
||||
#endif
|
||||
|
||||
#ifdef BUS72
|
||||
#define CFG_CSCR_VAL 0x2f030403
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Well this has to be defined, but on the other hand it is used differently
|
||||
* one may expect. For instance loadb command do not cares :-)
|
||||
* So advice is - do not relay on this...
|
||||
*/
|
||||
#define CFG_LOAD_ADDR 0x08400000
|
||||
|
||||
#define MHZ16QUARZINUSE
|
||||
|
||||
#ifdef MHZ16QUARZINUSE
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16000000
|
||||
#else
|
||||
#define CONFIG_SYSPLL_CLK_FREQ 16780000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000
|
||||
|
||||
/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
|
||||
#define CFG_FMCR_VAL 0x00000001
|
||||
|
||||
/* Bit[0:3] contain PERCLK1DIV for UART 1
|
||||
0x000b00b ->b<- -> 192MHz/12=16MHz
|
||||
0x000b00b ->8<- -> 144MHz/09=16MHz
|
||||
0x000b00b ->3<- -> 64MHz/4=16MHz */
|
||||
|
||||
#ifdef BUS96
|
||||
#define CFG_PCDR_VAL 0x000b00b5
|
||||
#endif
|
||||
|
||||
#ifdef BUS64
|
||||
#define CFG_PCDR_VAL 0x000b00b3
|
||||
#endif
|
||||
|
||||
#ifdef BUS72
|
||||
#define CFG_PCDR_VAL 0x000b00b8
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -39,7 +39,7 @@
|
||||
typedef struct {
|
||||
int flags; /* Device flags: input/output/system */
|
||||
int ext; /* Supported extensions */
|
||||
char name[8]; /* Device name */
|
||||
char name[16]; /* Device name */
|
||||
|
||||
/* GENERAL functions */
|
||||
|
||||
|
||||
1051
include/mc9328.h
1051
include/mc9328.h
File diff suppressed because it is too large
Load Diff
@@ -297,6 +297,7 @@
|
||||
#define PBESR 0x800000c7 /* PCI Bus Error Status Register */
|
||||
#define PBEAR 0x800000c8 /* Processor/PCI Bus Error Status Register */
|
||||
#define AMBOR 0x800000e0 /* Address Map B Options Register */
|
||||
#define PCMBCR 0x800000e1 /* PCI/Memory Buffer Configuration */
|
||||
#define MCCR1 0x800000f0 /* Memory Control Configuration Register 1 */
|
||||
#define MCCR2 0x800000f4 /* Memory Control Configuration Register 2 */
|
||||
#define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */
|
||||
|
||||
30
include/serial.h
Normal file
30
include/serial.h
Normal file
@@ -0,0 +1,30 @@
|
||||
#ifndef __SERIAL_H__
|
||||
#define __SERIAL_H__
|
||||
|
||||
#define NAMESIZE 16
|
||||
#define CTLRSIZE 8
|
||||
|
||||
struct serial_device {
|
||||
char name[NAMESIZE];
|
||||
char ctlr[CTLRSIZE];
|
||||
|
||||
int (*init) (void);
|
||||
void (*setbrg) (void);
|
||||
int (*getc) (void);
|
||||
int (*tstc) (void);
|
||||
void (*putc) (const char c);
|
||||
void (*puts) (const char *s);
|
||||
|
||||
struct serial_device *next;
|
||||
};
|
||||
|
||||
extern struct serial_device serial_smc_device;
|
||||
extern struct serial_device serial_scc_device;
|
||||
extern struct serial_device * default_serial_console (void);
|
||||
|
||||
extern void serial_initialize(void);
|
||||
extern void serial_devices_init(void);
|
||||
extern int serial_assign(char * name);
|
||||
extern void serial_reinit_all(void);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user