From adc983b4d676e4ca958067f86bec1bb02cb17950 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 10:13:48 +0000 Subject: [PATCH 01/50] dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdef This can avoid build error: The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only defined on the platforms that select the CONFIG_FOO, while it's not defined on platforms that do not select the CONFIG_FOO. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 69 ++++++++++++++++++++++-------------------- 1 file changed, 36 insertions(+), 33 deletions(-) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 4d61a46cef..1879d8104c 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -299,8 +299,9 @@ static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx, out_be32(&pi->piwbear, 0); #endif - if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434)) - flag = 0; +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + flag = 0; +#endif flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; if (pf) @@ -401,47 +402,47 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) fsl_pcie_init_atmu(pcie); - if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) { - val_32 = 0; - fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); - val_32 &= ~0x03; - fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); - udelay(1); - } +#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM + val_32 = 0; + fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); + val_32 &= ~0x03; + fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); + udelay(1); +#endif - if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) { - u16 ltssm; - int i; +#ifdef CONFIG_FSL_PCIE_RESET + u16 ltssm; + int i; - if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } else { + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + if (ltssm == 1) { /* assert PCIe reset */ setbits_be32(®s->pdb_stat, 0x08000000); (void)in_be32(®s->pdb_stat); - udelay(1000); + udelay(100); /* clear PCIe reset */ clrbits_be32(®s->pdb_stat, 0x08000000); asm("sync;isync"); - for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + for (i = 0; i < 100 && + !fsl_pcie_link_up(pcie); i++) udelay(1000); - } else { - fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); - if (ltssm == 1) { - /* assert PCIe reset */ - setbits_be32(®s->pdb_stat, 0x08000000); - (void)in_be32(®s->pdb_stat); - udelay(100); - /* clear PCIe reset */ - clrbits_be32(®s->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i = 0; i < 100 && - !fsl_pcie_link_up(pcie); i++) - udelay(1000); - } } } +#endif - if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) && - !fsl_pcie_link_up(pcie)) { +#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 + if (!fsl_pcie_link_up(pcie)) { serdes_corenet_t *srds_regs; srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; @@ -460,13 +461,15 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) udelay(1000); } } +#endif /* * The Read-Only Write Enable bit defaults to 1 instead of 0. * Set to 0 to protect the read-only registers. */ - if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815)) - clrbits_be32(®s->dbi_ro_wr_en, 0x01); +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + clrbits_be32(®s->dbi_ro_wr_en, 0x01); +#endif /* * Enable All Error Interrupts except From d18d06ac35229345a0af80977a408cfbe1d1015b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 10:13:51 +0000 Subject: [PATCH 02/50] dm: pcie_fsl: Fix the Class Code fixup function The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones. So add the Class Code fixup for the block revision < 3.0. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 17 +++++++++++++---- drivers/pci/pcie_fsl.h | 3 +++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 1879d8104c..1be5063467 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -503,14 +503,23 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) { ccsr_fsl_pci_t *regs = pcie->regs; + u32 classcode_reg; u32 val; - setbits_be32(®s->dbi_ro_wr_en, 0x01); - fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val); + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + classcode_reg = PCI_CLASS_REVISION; + setbits_be32(®s->dbi_ro_wr_en, 0x01); + } else { + classcode_reg = CSR_CLASSCODE; + } + + fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val); val &= 0xff; val |= PCI_CLASS_BRIDGE_PCI << 16; - fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val); - clrbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val); + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) + clrbits_be32(®s->dbi_ro_wr_en, 0x01); return 0; } diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 5eefc31fa9..032775ca05 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -9,6 +9,9 @@ #ifndef _PCIE_FSL_H_ #define _PCIE_FSL_H_ +/* GPEX CSR */ +#define CSR_CLASSCODE 0x474 + #ifdef CONFIG_SYS_FSL_PCI_VER_3_X #define FSL_PCIE_CAP_ID 0x70 #else From fbcb2ff5c6477c7d2ddc9f54967a5cfc21aefbed Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 10:13:54 +0000 Subject: [PATCH 03/50] dm: pcie_fsl: Fix the calculation of controller index The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index. Fix it by adding the related info to the driver data structure. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 14 ++++++++++++-- drivers/pci/pcie_fsl.h | 7 +++++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 1be5063467..d3d2c191e5 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -582,6 +582,7 @@ static int fsl_pcie_probe(struct udevice *dev) static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) { struct fsl_pcie *pcie = dev_get_priv(dev); + struct fsl_pcie_data *info; int ret; pcie->regs = dev_remap_addr(dev); @@ -596,7 +597,10 @@ static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) return ret; } - pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000; + info = (struct fsl_pcie_data *)dev_get_driver_data(dev); + pcie->info = info; + pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) - + info->block_offset) / info->stride; return 0; } @@ -606,8 +610,14 @@ static const struct dm_pci_ops fsl_pcie_ops = { .write_config = fsl_pcie_write_config, }; +static struct fsl_pcie_data t2080_data = { + .block_offset = 0x240000, + .block_offset_mask = 0x3fffff, + .stride = 0x10000, +}; + static const struct udevice_id fsl_pcie_ids[] = { - { .compatible = "fsl,pcie-t2080" }, + { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { } }; diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 032775ca05..dc8368d559 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -43,6 +43,12 @@ #define LTSSM_L0_REV3 0x11 #define LTSSM_L0 0x16 +struct fsl_pcie_data { + u32 block_offset; /* Offset from CCSR of 1st controller */ + u32 block_offset_mask; /* Mask out the CCSR base */ + u32 stride; /* Offset stride between controllers */ +}; + struct fsl_pcie { int idx; struct udevice *bus; @@ -52,6 +58,7 @@ struct fsl_pcie { bool mode; /* RC&EP mode flag */ bool enabled; /* Enable status */ struct list_head list; + struct fsl_pcie_data *info; }; extern struct list_head fsl_pcie_list; From fb0d98da83b25143e84a558876a64af2cd799a39 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:02:52 +0000 Subject: [PATCH 04/50] powerpc: T208xRDB: Compile legacy PCIe routines conditionally Compile the legacy PCIe initialization routines only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- board/freescale/t208xrdb/pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c index 161b8cb403..adc128d924 100644 --- a/board/freescale/t208xrdb/pci.c +++ b/board/freescale/t208xrdb/pci.c @@ -11,6 +11,7 @@ #include #include +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif From d85fa79d7b073f24ebc53ba82ad439f1160cbf37 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:02:56 +0000 Subject: [PATCH 05/50] powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- include/configs/T208xRDB.h | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ab92ca3b68..3d95c4afa2 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -433,49 +433,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif From 57afc23c7dad5665a672eb33d8bf8c96e1deb9ab Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:02:59 +0000 Subject: [PATCH 06/50] configs: T2080RDB: Enable PCIe driver Enable the DM PCIe driver in T2080RDB defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/T2080RDB_NAND_defconfig | 4 ++++ configs/T2080RDB_SDCARD_defconfig | 4 ++++ configs/T2080RDB_SPIFLASH_defconfig | 4 ++++ configs/T2080RDB_defconfig | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index e2ab855bf7..dcd57f7b3a 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index b7f6baaba0..235e8ee514 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index f80e39f6c0..7b64b7d490 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index c928059e71..69ee626ee0 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -44,6 +44,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y From f9c0c79a5a32256276eea39ec7ac2badcd031a23 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:03 +0000 Subject: [PATCH 07/50] powerpc: T4RDB: Compile legacy PCIe routines conditionally Compile the legacy PCIe initialization routines only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- board/freescale/t4rdb/pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c index 4100370e20..7d670e1a2f 100644 --- a/board/freescale/t4rdb/pci.c +++ b/board/freescale/t4rdb/pci.c @@ -11,6 +11,7 @@ #include #include +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif From 9acc038b3990a3f74292f9c77c535e569e41dd74 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:06 +0000 Subject: [PATCH 08/50] dm: pcie_fsl: Add T4240 PCIe support Add compatible string for T4240 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index d3d2c191e5..f15deb0495 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -618,6 +618,7 @@ static struct fsl_pcie_data t2080_data = { static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, + { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { } }; From 948d8118827928b59626d51ab6d896829397b9d8 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:10 +0000 Subject: [PATCH 09/50] t4240: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T4240 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/t4240.dtsi | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi index 4d8fc7192e..fc34974c7f 100644 --- a/arch/powerpc/dts/t4240.dtsi +++ b/arch/powerpc/dts/t4240.dtsi @@ -99,4 +99,52 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x4000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x4000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe270000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe270000 0x0 0x4000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; From 75a9137ddc2b266d491f5359ec4daaddb3a713ab Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:13 +0000 Subject: [PATCH 10/50] powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- include/configs/T4240RDB.h | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 0accdc6119..57d8d171a7 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -61,7 +61,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -176,44 +175,48 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ From 46031228200df95ac3c8d04f837b6d7d2d20bd07 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:16 +0000 Subject: [PATCH 11/50] configs: T4240RDB: Enable PCIe driver Enable the DM PCIe driver in T4240RDB defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/T4240RDB_SDCARD_defconfig | 4 ++++ configs/T4240RDB_defconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index b82de5cd22..7f97166860 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -51,6 +51,10 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index d8ff848349..81bd59566d 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -38,6 +38,10 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y From 5c8219ee7b07db465a8577d46b9d470e16b54125 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:20 +0000 Subject: [PATCH 12/50] powerpc: T102xRDB: Compile legacy PCIe routines conditionally Compile the legacy PCIe initialization routines only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- board/freescale/t102xrdb/pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c index 161b8cb403..adc128d924 100644 --- a/board/freescale/t102xrdb/pci.c +++ b/board/freescale/t102xrdb/pci.c @@ -11,6 +11,7 @@ #include #include +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif From a8c79f6189c608cf000218db5d08876425b5f71c Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:24 +0000 Subject: [PATCH 13/50] dm: pcie_fsl: Add T102x PCIe support Add compatible string for T102x PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index f15deb0495..fd7aae59f7 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -617,6 +617,7 @@ static struct fsl_pcie_data t2080_data = { }; static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { } From efd7d712dd3d3a7343bd34ad6e8f819d8ecc6a0c Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:27 +0000 Subject: [PATCH 14/50] t102x: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T102x integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/t102x.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index 2393e316f8..c49fd21088 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -49,4 +49,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; }; From 233044dd3e987dd811186b134120e1df7c304080 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:30 +0000 Subject: [PATCH 15/50] powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040 Remove the macro CONFIG_ARCH_T1040 from the T102xRDB.h and the PCIE4 related macros, as there are only 3 PCIe controllers on T102x SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- include/configs/T102xRDB.h | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 5ab51e3233..b76ce8d69f 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -494,9 +494,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#ifdef CONFIG_ARCH_T1040 -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#endif #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_PCI_INDIRECT_BRIDGE @@ -565,27 +562,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif -/* controller 4, Base address 203000, to be removed */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#else -#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 -#endif -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#else -#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 -#endif -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#endif - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ From f9abe6dd17c8d6afa1df4cad7a8cd717dedf0ef6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:34 +0000 Subject: [PATCH 16/50] powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- include/configs/T102xRDB.h | 54 +++++++++++--------------------------- 1 file changed, 15 insertions(+), 39 deletions(-) diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b76ce8d69f..8c1434fb10 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -494,72 +494,48 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE #ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ From 50801d4eb0285d268ff64061a125de643956ba79 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:37 +0000 Subject: [PATCH 17/50] configs: T1024RDB: Enable PCIe driver Enable the DM PCIe driver in T1024RDB defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/T1024RDB_NAND_defconfig | 4 ++++ configs/T1024RDB_SDCARD_defconfig | 4 ++++ configs/T1024RDB_SPIFLASH_defconfig | 4 ++++ configs/T1024RDB_defconfig | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 27ed0e7b8c..c38912dc38 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -64,6 +64,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 010b49c705..5215953caf 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -61,6 +61,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index ff267fc32a..2e6b81b0c2 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -62,6 +62,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index a781738801..ccd9112832 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -48,6 +48,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y From 6aefcc8cc79e1c5d3b66b29576d456c30435b8d7 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:41 +0000 Subject: [PATCH 18/50] powerpc: T104xRDB: Compile legacy PCIe routines conditionally Compile the legacy PCIe initialization routines only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- board/freescale/t104xrdb/pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c index 9fd66594f4..6b666ba2d2 100644 --- a/board/freescale/t104xrdb/pci.c +++ b/board/freescale/t104xrdb/pci.c @@ -11,6 +11,7 @@ #include #include +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif From 4392ddbbbba50df69687a4ea0e043d25c944835f Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:44 +0000 Subject: [PATCH 19/50] dm: pcie_fsl: Add T104x PCIe support Add compatible string for T104x PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index fd7aae59f7..a085c0cab9 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -618,6 +618,7 @@ static struct fsl_pcie_data t2080_data = { static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, + { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { } From 3e89360e115e5aece681f7aec22f40258abc7fa2 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:47 +0000 Subject: [PATCH 20/50] t104x: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T104x integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/t104x.dtsi | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi index ff0da9397e..59989677a2 100644 --- a/arch/powerpc/dts/t104x.dtsi +++ b/arch/powerpc/dts/t104x.dtsi @@ -59,4 +59,52 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe270000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; }; From 75974847becfc96d8f7562797048b0048f8a458d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:51 +0000 Subject: [PATCH 21/50] powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- include/configs/T104xRDB.h | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 56ddef07f5..53ee1484d0 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -145,13 +145,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -524,51 +522,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif /* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #endif +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ From 7a9639780182962ebc42b371c92b82747cd88ec4 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:54 +0000 Subject: [PATCH 22/50] configs: T1042D4RDB: Enable PCIe driver Enable the DM PCIe driver in T1042D4RDB defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/T1042D4RDB_NAND_defconfig | 4 ++++ configs/T1042D4RDB_SDCARD_defconfig | 4 ++++ configs/T1042D4RDB_SPIFLASH_defconfig | 4 ++++ configs/T1042D4RDB_defconfig | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 700e83a967..920af5b4c4 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -62,6 +62,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 8fa917a42f..e532366218 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 2dfe8867cc..78e4582113 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 084651344a..3a4699b3ef 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y From 7e4248c5d835ab840609e408c3754658936c6cce Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:03:58 +0000 Subject: [PATCH 23/50] powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally Compile the legacy PCIe initialization routines for P1020, P1021, P1024, P1025 and P2020 RDB boards only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index a04a73528f..3649f16598 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -278,7 +278,7 @@ int checkboard(void) return 0; } -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -444,7 +444,9 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); +#if !defined(CONFIG_DM_PCI) FT_FSL_PCI_SETUP; +#endif #ifdef CONFIG_QE do_fixup_by_compat(blob, "fsl,qe", "status", "okay", From ba827365f7e1ad7546e6ec3098221ebd1bcfaf27 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:01 +0000 Subject: [PATCH 24/50] dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs Add compatible string for PCIe of P1020, P1021, P1024, P1025 and P2020 SoCs. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index a085c0cab9..31cb5d25ad 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -610,6 +610,12 @@ static const struct dm_pci_ops fsl_pcie_ops = { .write_config = fsl_pcie_write_config, }; +static struct fsl_pcie_data p1_p2_data = { + .block_offset = 0xa000, + .block_offset_mask = 0xffff, + .stride = 0x1000, +}; + static struct fsl_pcie_data t2080_data = { .block_offset = 0x240000, .block_offset_mask = 0x3fffff, @@ -617,6 +623,7 @@ static struct fsl_pcie_data t2080_data = { }; static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, From 594708dd9dc9f1204ae0ea236d00e57fd25ddf0d Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:04 +0000 Subject: [PATCH 25/50] P1020: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P1020 integrated 2 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/p1020-post.dtsi | 20 ++++++++++++++++++++ arch/powerpc/dts/p1020rdb-pc.dts | 12 ++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 ++++++++++++ arch/powerpc/dts/p1020rdb-pd.dts | 12 ++++++++++++ 4 files changed, 56 insertions(+) diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index e1a4f500a6..1e5e67804b 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -25,3 +25,23 @@ last-interrupt-source = <255>; }; }; + +/* PCIe controller base address 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts index fd68b8b440..7ebaa619df 100644 --- a/arch/powerpc/dts/p1020rdb-pc.dts +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -18,6 +18,18 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts index a23d031eee..c0e5ef4cf4 100644 --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -18,6 +18,18 @@ soc: soc@fffe00000 { ranges = <0x0 0xf 0xffe00000 0x100000>; }; + + pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts index 81f25a3866..21174a09be 100644 --- a/arch/powerpc/dts/p1020rdb-pd.dts +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -18,6 +18,18 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "p1020-post.dtsi" From c1e486e81a8d8aa6ecc1979cd3de69d61b96f606 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:08 +0000 Subject: [PATCH 26/50] powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled for P1020, P1021, P1024, P1025 and P2020 RDB boards. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- include/configs/p1_p2_rdb_pc.h | 36 ++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e07d2a178f..1481d683e5 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -207,8 +207,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -572,44 +570,56 @@ */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ From 2bc49ecb68ed71b36337f5c81f7edc8e816c1048 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:11 +0000 Subject: [PATCH 27/50] configs: P1020RDB: Enable PCIe driver Enable the DM PCIe driver in P1020RDB defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/P1020RDB-PC_36BIT_NAND_defconfig | 4 ++++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 4 ++++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++++ configs/P1020RDB-PC_36BIT_defconfig | 4 ++++ configs/P1020RDB-PC_NAND_defconfig | 4 ++++ configs/P1020RDB-PC_SDCARD_defconfig | 4 ++++ configs/P1020RDB-PC_SPIFLASH_defconfig | 4 ++++ configs/P1020RDB-PC_defconfig | 4 ++++ configs/P1020RDB-PD_NAND_defconfig | 4 ++++ configs/P1020RDB-PD_SDCARD_defconfig | 4 ++++ configs/P1020RDB-PD_SPIFLASH_defconfig | 4 ++++ configs/P1020RDB-PD_defconfig | 4 ++++ 12 files changed, 48 insertions(+) diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index dde2e1863a..c4e41f2010 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 9f956c6590..b21fc2159b 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -53,6 +53,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 78aaf49ca6..2f69683379 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -54,6 +54,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 8d7efd773e..6145bf2cc6 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -42,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 0eb4bdd2d4..832c96967e 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 6a31d8aa16..2b5537bc32 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -52,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index fe14968f74..dc4f7d6a70 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -53,6 +53,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index ea57e52fe7..bd0bb1796c 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 7b80337c0f..acbb9e0159 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -61,6 +61,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 6ae1dbf451..208138f594 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index da19f18322..960f2718a9 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index f87cfb3ee0..217ae7b1e6 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -45,6 +45,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y From 68751497401a7bdc917c58eec8ceaa40faaeb2e6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:15 +0000 Subject: [PATCH 28/50] P2020: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P2020 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/p2020-post.dtsi | 30 ++++++++++++++++++++++++++++ arch/powerpc/dts/p2020rdb-pc.dts | 17 ++++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 ++++++++++++++++ 3 files changed, 64 insertions(+) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index f20d1fa20d..f696f35960 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -25,3 +25,33 @@ last-interrupt-source = <255>; }; }; + +/* PCIe controller base address 0x8000 */ +&pci2 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 4800b76c1c..08befd4c59 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -18,6 +18,23 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; + + pci2: pcie@ffe08000 { + reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */ + status = "disabled"; + }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "p2020-post.dtsi" diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 8323b90e6d..04b2519e1a 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -18,6 +18,23 @@ soc: soc@fffe00000 { ranges = <0x0 0xf 0xffe00000 0x100000>; }; + + pci2: pcie@fffe08000 { + reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */ + status = "disabled"; + }; + + pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "p2020-post.dtsi" From 7eabbf2512a0db487bddecf36df1a3f854100e72 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:18 +0000 Subject: [PATCH 29/50] configs: P2020RDB: Enable PCIe driver Enable the DM PCIe driver in P2020RDB defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/P2020RDB-PC_36BIT_NAND_defconfig | 4 ++++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 4 ++++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++++ configs/P2020RDB-PC_36BIT_defconfig | 4 ++++ configs/P2020RDB-PC_NAND_defconfig | 4 ++++ configs/P2020RDB-PC_SDCARD_defconfig | 4 ++++ configs/P2020RDB-PC_SPIFLASH_defconfig | 4 ++++ configs/P2020RDB-PC_defconfig | 4 ++++ 8 files changed, 32 insertions(+) diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 542fe36e76..5e279814a1 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -63,6 +63,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 0c2bcb3d46..49a7c8052d 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index b643b571fd..59fce53690 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 6f04bee17a..401742463d 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -47,6 +47,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 28901317ba..3c65108d7d 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -62,6 +62,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 42f6c07ec5..05f42aef8a 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 79d3b4713c..bfb7026f2d 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 54402382ab..6c7ac9d759 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y From 5833a35748dce472a270264b01b32350423721fd Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:22 +0000 Subject: [PATCH 30/50] powerpc: p_corenet: Compile legacy PCIe routines conditionally Compile the legacy PCIe initialization routines for P2041RDB, P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- board/freescale/common/p_corenet/pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c index a2df928fc5..a6abe66dc0 100644 --- a/board/freescale/common/p_corenet/pci.c +++ b/board/freescale/common/p_corenet/pci.c @@ -11,6 +11,7 @@ #include #include +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif From 1a92802e3207ef362e77115654336bfbe76fd5da Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:25 +0000 Subject: [PATCH 31/50] dm: pcie_fsl: Add P2041 PCIe support Add compatible string for P2041 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 31cb5d25ad..687947ed85 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -616,6 +616,12 @@ static struct fsl_pcie_data p1_p2_data = { .stride = 0x1000, }; +static struct fsl_pcie_data p2041_data = { + .block_offset = 0x200000, + .block_offset_mask = 0x3fffff, + .stride = 0x1000, +}; + static struct fsl_pcie_data t2080_data = { .block_offset = 0x240000, .block_offset_mask = 0x3fffff, @@ -624,6 +630,7 @@ static struct fsl_pcie_data t2080_data = { static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, + { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, From 48a33645b0b580815a3fef2b7ea18f6e146e0122 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:29 +0000 Subject: [PATCH 32/50] P2041: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P2041 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/p2041.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi index 9aa0422821..55f7adc50e 100644 --- a/arch/powerpc/dts/p2041.dtsi +++ b/arch/powerpc/dts/p2041.dtsi @@ -60,4 +60,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; From e617bb8d16a7746c0908912700ae1953432f70ff Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:32 +0000 Subject: [PATCH 33/50] powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- include/configs/P2041RDB.h | 55 +++++++++++--------------------------- 1 file changed, 15 insertions(+), 40 deletions(-) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e196f3ce33..f8cfef7b2d 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -37,7 +37,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_SYS_SRIO @@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -483,7 +443,22 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ From a08119bd4711b7c3742e3a629f98724db258e61a Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:35 +0000 Subject: [PATCH 34/50] configs: P2041RDB: Enable PCIe driver Enable the DM PCIe driver in P2041RDB defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/P2041RDB_NAND_defconfig | 4 ++++ configs/P2041RDB_SDCARD_defconfig | 4 ++++ configs/P2041RDB_SPIFLASH_defconfig | 4 ++++ configs/P2041RDB_defconfig | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 3ffc56af3b..70b9190b53 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 1816aa8887..2542526aee 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 389e1fa311..4edb581f7c 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 1fda0f9869..8a158f52b7 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y From 096d5f80151f2160f6defe7b1497b9590cbcecfa Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:39 +0000 Subject: [PATCH 35/50] dm: pcie_fsl: Add P3041 PCIe support Add compatible string for P3041 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 687947ed85..9b60492fc5 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -631,6 +631,7 @@ static struct fsl_pcie_data t2080_data = { static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, From fc81606da901cb26c7fe8abe0ce5634959b4d815 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:42 +0000 Subject: [PATCH 36/50] P3041: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P3041 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/p3041.dtsi | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi index 7d5c7134aa..197896d35a 100644 --- a/arch/powerpc/dts/p3041.dtsi +++ b/arch/powerpc/dts/p3041.dtsi @@ -60,4 +60,52 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe203000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; From 7bf7edd4231c5dbf0d4f7a9606a39ae4a622b4d9 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:45 +0000 Subject: [PATCH 37/50] powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- include/configs/corenet_ds.h | 63 +++++++++++------------------------- 1 file changed, 19 insertions(+), 44 deletions(-) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e5c3a0c3f2..60e09c1939 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -362,68 +361,25 @@ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -499,7 +455,26 @@ #endif #ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ From 453b5604148f534899b02f3f6e8b2a201568b674 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:49 +0000 Subject: [PATCH 38/50] configs: P3041DS: Enable PCIe driver Enable the DM PCIe driver in P3041DS defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/P3041DS_NAND_defconfig | 4 ++++ configs/P3041DS_SDCARD_defconfig | 4 ++++ configs/P3041DS_SPIFLASH_defconfig | 4 ++++ configs/P3041DS_defconfig | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index fdea8117b4..7f8145fe4c 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 70e40b1685..c6b2750cc2 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index e828b009d9..1b247cc931 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 958e95a441..f8e30efbd4 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y From 7b7e4e1b7e10c1b102f12f920fec81997464e568 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:52 +0000 Subject: [PATCH 39/50] dm: pcie_fsl: Add P4080 PCIe support Add compatible string for P4080 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 9b60492fc5..30fff1ede7 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -632,6 +632,7 @@ static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, From 936339a50098d7e0d2fda3a3dcb3c72cb28f572f Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:56 +0000 Subject: [PATCH 40/50] P4080: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P4080 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/p4080.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi index 7c8dbae442..ab766803a3 100644 --- a/arch/powerpc/dts/p4080.dtsi +++ b/arch/powerpc/dts/p4080.dtsi @@ -80,4 +80,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; From 904c4d3a5a486d272f3f7fa95b0043bf3132c925 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:04:59 +0000 Subject: [PATCH 41/50] configs: P4080DS: Enable PCIe driver Enable the DM PCIe driver in P4080DS defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/P4080DS_SDCARD_defconfig | 4 ++++ configs/P4080DS_SPIFLASH_defconfig | 4 ++++ configs/P4080DS_defconfig | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 05e7435579..0c309f92ca 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index bd7ce5e1f0..070ade5cfa 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index c7ce3a67c8..0a35266cd5 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y From 52744596284042f0865f70ce9d12064b6d898452 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:02 +0000 Subject: [PATCH 42/50] dm: pcie_fsl: Add P5040 PCIe support Add compatible string for P5040 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 30fff1ede7..199cec3e9b 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -633,6 +633,7 @@ static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, From a1958b118b481d148908bf7c41e51a8249e76fab Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:06 +0000 Subject: [PATCH 43/50] P5040: dts: Added PCIe DT nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P5040 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/p5040.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi index b6f6c5dd58..8ab123dca4 100644 --- a/arch/powerpc/dts/p5040.dtsi +++ b/arch/powerpc/dts/p5040.dtsi @@ -59,4 +59,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; From e44b5c012ff6b965724cff4c7a5ae335ca8a4aeb Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:09 +0000 Subject: [PATCH 44/50] configs: P5040DS: Enable PCIe driver Enable the DM PCIe driver in P5040DS defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng eviewed-by: Prabhakar Kushwaha --- configs/P5040DS_NAND_defconfig | 4 ++++ configs/P5040DS_SDCARD_defconfig | 4 ++++ configs/P5040DS_SPIFLASH_defconfig | 4 ++++ configs/P5040DS_defconfig | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 9c9d36e1fb..847250e0d9 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -42,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index e40e055879..a61d36d1ff 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 2b009d2122..4eaa35448b 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index ae1c9637f9..2e67dce267 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y From d15471e6c49de61dbd8195c670ede3170c7f3fdb Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:12 +0000 Subject: [PATCH 45/50] powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally Compile the legacy PCIe initialization routines only when DM_PCI is not enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- board/freescale/mpc8548cds/mpc8548cds.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 7d819d8df5..2799b5b5a4 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -164,7 +164,7 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ } -#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. */ @@ -189,6 +189,7 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { static struct pci_controller pci1_hose; #endif /* CONFIG_PCI */ +#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -268,6 +269,7 @@ void pci_init_board(void) fsl_pcie_init_board(first_free_busno); } +#endif void configure_rgmii(void) { @@ -349,7 +351,7 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); } -#if defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI) void ft_pci_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; From 70388039c3b9c2d2f397610ec920d9a13aa826e4 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:16 +0000 Subject: [PATCH 46/50] powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected Disable legacy PCI and PCIe fixup when CONFIG_DM_PCI is selected. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- board/freescale/common/cds_pci_ft.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 3ff2fa416b..fb2e5c7bf3 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -9,6 +9,7 @@ #include "cadmus.h" #if defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) static void cds_pci_fixup(void *blob) { int node; @@ -61,11 +62,12 @@ static void cds_pci_fixup(void *blob) } } } +#endif int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) ft_pci_setup(blob, bd); cds_pci_fixup(blob); #endif From 92e025c6e15be4eb0f045da423eba0f58d61305f Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:19 +0000 Subject: [PATCH 47/50] dm: pcie_fsl: Add MPC8548 PCIe support Add compatible string for MPC8548 PCIe. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 199cec3e9b..ab25aeee73 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -629,6 +629,7 @@ static struct fsl_pcie_data t2080_data = { }; static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, From 00acf26044f320f71458f4bcf479fc88199489c7 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:23 +0000 Subject: [PATCH 48/50] MPC8548: dts: Added PCIe DT node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MPC8548 integrated a PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for the PCIe controller. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- arch/powerpc/dts/mpc8548-post.dtsi | 9 +++++++++ arch/powerpc/dts/mpc8548cds.dts | 6 ++++++ arch/powerpc/dts/mpc8548cds_36b.dts | 6 ++++++ 3 files changed, 21 insertions(+) diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi index 5533a4b598..2206f2da9f 100644 --- a/arch/powerpc/dts/mpc8548-post.dtsi +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -25,3 +25,12 @@ last-interrupt-source = <255>; }; }; + +&pcie { + compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts index cceea345c8..3b927bd265 100644 --- a/arch/powerpc/dts/mpc8548cds.dts +++ b/arch/powerpc/dts/mpc8548cds.dts @@ -18,6 +18,12 @@ soc: soc8548@e0000000 { ranges = <0x0 0x0 0xe0000000 0x100000>; }; + + pcie: pcie@e000a000 { + reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "mpc8548-post.dtsi" diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548cds_36b.dts index faff35cc36..98d7c2410b 100644 --- a/arch/powerpc/dts/mpc8548cds_36b.dts +++ b/arch/powerpc/dts/mpc8548cds_36b.dts @@ -18,6 +18,12 @@ soc: soc8548@fe0000000 { ranges = <0x0 0xf 0xe0000000 0x100000>; }; + + pcie: pcie@fe000a000 { + reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; }; /include/ "mpc8548-post.dtsi" From 2056121d6760c9fc74aa4b671b07d08ffe69ca37 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:26 +0000 Subject: [PATCH 49/50] powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- include/configs/MPC8548CDS.h | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index e2d6350cb0..3a8c074dc5 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -18,8 +18,6 @@ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #undef CONFIG_PCI2 -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -343,24 +341,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif /* @@ -386,6 +378,20 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 +#define CONFIG_SYS_PCIE1_NAME "Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif + #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ From 43e881e38b505835dd3d20ab35b5845bc20a1aae Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Tue, 27 Aug 2019 11:05:29 +0000 Subject: [PATCH 50/50] configs: MPC8548CDS: Enable PCIe driver Enable the DM PCIe driver in MPC8548CDS defconfig. Signed-off-by: Hou Zhiqiang Reviewed-by: Bin Meng Reviewed-by: Prabhakar Kushwaha --- configs/MPC8548CDS_36BIT_defconfig | 4 ++++ configs/MPC8548CDS_defconfig | 4 ++++ configs/MPC8548CDS_legacy_defconfig | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index f259f1992c..102716bc07 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -26,6 +26,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 72239da0c3..9cccb609e5 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index f2420c3ad2..782f8270c8 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2