Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx
For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
committed by
Wolfgang Denk
parent
3a71b5ca77
commit
255a3577c8
@@ -303,11 +303,11 @@
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#endif
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#define CONFIG_GMII 1 /* MII PHY management */
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#define CONFIG_MPC83XX_TSEC1 1
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#define CONFIG_TSEC1 1
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#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC83XX_TSEC2 1
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#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 0x1c
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#define TSEC2_PHY_ADDR 4
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#define TSEC1_PHYIDX 0
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@@ -432,10 +432,10 @@
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#endif
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#define CONFIG_GMII 1 /* MII PHY management */
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#define CONFIG_MPC83XX_TSEC1 1
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#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC83XX_TSEC2 1
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#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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@@ -374,18 +374,18 @@ boards, we say we have two, but don't display a message if we find only one. */
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#define CONFIG_MII
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#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
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#define CONFIG_MPC83XX_TSEC1
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#define CONFIG_TSEC1
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#ifdef CONFIG_MPC83XX_TSEC1
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#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
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#ifdef CONFIG_TSEC1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CFG_TSEC1_OFFSET 0x24000
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#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
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#define TSEC1_PHYIDX 0
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#endif
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#ifdef CONFIG_MPC83XX_TSEC2
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#ifdef CONFIG_TSEC2
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#define CONFIG_HAS_ETH1
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#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CFG_TSEC2_OFFSET 0x25000
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#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
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#define TSEC2_PHY_ADDR 4
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@@ -628,11 +628,11 @@ boards, we say we have two, but don't display a message if we find only one. */
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*/
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#define CONFIG_ENV_OVERWRITE
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#ifdef CONFIG_MPC83XX_TSEC1
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#ifdef CONFIG_TSEC1
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#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
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#endif
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#ifdef CONFIG_MPC83XX_TSEC2
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#ifdef CONFIG_TSEC2
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#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
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#endif
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@@ -366,10 +366,10 @@
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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@@ -212,10 +212,10 @@
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#elif defined(CONFIG_TSEC_ENET)
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#define CONFIG_NET_MULTI 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_MPC85XX_FEC 1
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#define CONFIG_MPC85XX_FEC_NAME "FEC"
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#define TSEC1_PHY_ADDR 7
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@@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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@@ -359,10 +359,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1"
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#define CONFIG_MPC85XX_TSEC3 1
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#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 0
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@@ -391,14 +391,14 @@ extern unsigned long get_clock_freq(void);
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
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#define CONFIG_MPC85XX_TSEC3 1
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#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
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#undef CONFIG_MPC85XX_TSEC4
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#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC2"
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#undef CONFIG_TSEC4
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#define CONFIG_TSEC4_NAME "eTSEC3"
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 0
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@@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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@@ -356,10 +356,10 @@
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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@@ -353,12 +353,12 @@ extern unsigned long get_clock_freq(void);
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
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#undef CONFIG_MPC85XX_TSEC3
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#undef CONFIG_MPC85XX_TSEC4
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#undef CONFIG_TSEC3
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#undef CONFIG_TSEC4
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 2
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@@ -359,14 +359,14 @@
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC86XX_TSEC1 1
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#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1"
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#define CONFIG_MPC86XX_TSEC2 1
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#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2"
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#define CONFIG_MPC86XX_TSEC3 1
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#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3"
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#define CONFIG_MPC86XX_TSEC4 1
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#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC2"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#define CONFIG_TSEC4 1
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#define CONFIG_TSEC4_NAME "eTSEC4"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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@@ -262,10 +262,10 @@
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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@@ -258,10 +258,10 @@
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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@@ -248,10 +248,10 @@ extern int tqm834x_num_flash_banks;
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#define CONFIG_NET_MULTI
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#endif
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#define CONFIG_MPC83XX_TSEC1 1
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#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC83XX_TSEC2 1
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#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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@@ -258,10 +258,10 @@
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#define CONFIG_NET_MULTI 1
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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@@ -401,10 +401,10 @@
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_MPC83XX_TSEC1 1
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#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC83XX_TSEC2 1
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#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define CONFIG_PHY_BCM5421S 1
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#define TSEC1_PHY_ADDR 0x19
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#define TSEC2_PHY_ADDR 0x1a
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@@ -230,10 +230,10 @@
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#undef CONFIG_MPS85XX_FEC
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#define TSEC1_PHY_ADDR 2
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@@ -252,10 +252,10 @@
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MPC85XX_TSEC1 1
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#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
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#define CONFIG_MPC85XX_TSEC2 1
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#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#undef CONFIG_MPS85XX_FEC
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#define TSEC1_PHY_ADDR 2
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