imx6: aristainetos: add support for rev C board
add support for revision C boards. This board has no longer a NAND. Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
committed by
Stefano Babic
Stefano Babic
parent
c08aa77173
commit
227cb30047
@@ -582,6 +582,8 @@ dtb-y += \
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imx6dl-aristainetos2b_7.dtb \
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imx6dl-aristainetos2b_csl_4.dtb \
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imx6dl-aristainetos2b_csl_7.dtb \
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imx6dl-aristainetos2c_4.dtb \
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imx6dl-aristainetos2c_7.dtb \
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imx6dl-brppt2.dtb \
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imx6dl-dhcom-pdk2.dtb \
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imx6dl-icore.dtb \
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13
arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
Normal file
13
arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi
Normal file
@@ -0,0 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0+ or X11
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/*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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*/
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#include <imx6qdl-aristainetos2c-u-boot.dtsi>
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&lcd_panel {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu_disp>;
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enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
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backlight = <&backlight>;
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};
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50
arch/arm/dts/imx6dl-aristainetos2c_4.dts
Normal file
50
arch/arm/dts/imx6dl-aristainetos2c_4.dts
Normal file
@@ -0,0 +1,50 @@
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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* support for the imx6 based aristainetos2c board
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* parts for 4.3 inch LG display on spi1 port1
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*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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*
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*/
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/dts-v1/;
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#include "imx6dl-aristainetos2_4.dtsi"
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#include "imx6qdl-aristainetos2c.dtsi"
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/ {
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model = "aristainetos2c i.MX6 Dual Lite Board 4";
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compatible = "fsl,imx6dl";
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};
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&ecspi1 {
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lcd_panel: display@0 {
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compatible = "lg,lg4573";
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spi-max-frequency = <10000000>;
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reg = <1>;
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power-on-delay = <10>;
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display-timings {
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480x800p57 {
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native-mode;
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clock-frequency = <27000027>;
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hactive = <480>;
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vactive = <800>;
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hfront-porch = <10>;
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hback-porch = <59>;
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hsync-len = <10>;
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vback-porch = <15>;
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vfront-porch = <15>;
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vsync-len = <15>;
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hsync-active = <1>;
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vsync-active = <1>;
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};
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};
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port {
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panel_in: endpoint {
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remote-endpoint = <&display_out>;
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};
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};
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};
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};
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19
arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
Normal file
19
arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi
Normal file
@@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+ or X11
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/*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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*/
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#include <imx6qdl-aristainetos2c-u-boot.dtsi>
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/ {
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vdd_panel_reg: regulator-panel {
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compatible = "regulator-fixed";
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regulator-name = "panel_regulator";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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&panel0 {
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power-supply = <&vdd_panel_reg>;
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};
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16
arch/arm/dts/imx6dl-aristainetos2c_7.dts
Normal file
16
arch/arm/dts/imx6dl-aristainetos2c_7.dts
Normal file
@@ -0,0 +1,16 @@
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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* support for the imx6 based aristainetos2c board
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*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
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*
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*/
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/dts-v1/;
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#include "imx6dl-aristainetos2_7.dtsi"
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#include "imx6qdl-aristainetos2c.dtsi"
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/ {
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model = "aristainetos2c i.MX6 Dual Lite Board 7";
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compatible = "fsl,imx6dl";
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};
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77
arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
Normal file
77
arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi
Normal file
@@ -0,0 +1,77 @@
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// SPDX-License-Identifier: GPL-2.0+ or X11
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/*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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*/
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/ {
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chosen {
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u-boot,dm-pre-reloc;
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stdout-path = &uart2;
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};
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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};
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};
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&uart2 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_gpio {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_uart2 {
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u-boot,dm-pre-reloc;
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};
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&iomuxc {
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u-boot,dm-pre-reloc;
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};
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&aips2 {
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u-boot,dm-pre-reloc;
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};
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&backlight {
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pwms = <&pwm1 0 300000>;
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default-brightness-level = <2>;
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};
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/*
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* allow switching write protect / reset pin by gpio,
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* because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
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*/
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&gpio2 {
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u-boot,dm-pre-reloc;
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wp_spi_nor {
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gpio-hog;
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output-high;
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gpios = <15 GPIO_ACTIVE_HIGH>;
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};
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reset_spi_nor {
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gpio-hog;
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output-high;
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gpios = <28 GPIO_ACTIVE_HIGH>;
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};
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};
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&gpio4 {
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u-boot,dm-pre-reloc;
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};
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&ecspi1 {
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u-boot,dm-pre-reloc;
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};
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&flash {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_ecspi1 {
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u-boot,dm-pre-reloc;
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};
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228
arch/arm/dts/imx6qdl-aristainetos2c.dtsi
Normal file
228
arch/arm/dts/imx6qdl-aristainetos2c.dtsi
Normal file
@@ -0,0 +1,228 @@
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// SPDX-License-Identifier: (GPL-2.0)
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/*
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* support for the imx6 based aristainetos2c board
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*
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* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
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* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
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*
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include "imx6qdl-aristainetos2-common.dtsi"
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/ {
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio>;
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LED_blue {
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label = "led_blue";
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gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
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};
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LED_green {
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label = "led_green";
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gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
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};
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LED_red {
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label = "led_red";
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gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
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};
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LED_yellow {
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label = "led_yellow";
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gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
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};
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LED_ena {
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label = "led_ena";
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gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&ecspi1 {
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fsl,spi-num-chipselects = <3>;
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cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
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&gpio4 10 GPIO_ACTIVE_HIGH
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&gpio4 11 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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status = "okay";
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pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
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pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
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flash: m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q128a11", "jedec,spi-nor";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&ecspi4 {
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi4>;
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status = "okay";
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};
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&i2c1 {
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tpm@20 {
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compatible = "infineon,slb9645tt";
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reg = <0x20>;
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
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no-1-8-v;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>;
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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status = "okay";
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};
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&iomuxc {
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
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MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
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MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
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/* SS0# */
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MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
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/* SS1# */
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MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
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/* SS2# */
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MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
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/* WP pin NOR Flash */
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MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
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/* Flash nReset */
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MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
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>;
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};
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pinctrl_ecspi4: ecspi4grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
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MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
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MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
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MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
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MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
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>;
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};
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pinctrl_gpio: gpiogrp {
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fsl,pins = <
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/* led enable */
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MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
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/* LCD power enable */
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
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/* led yellow */
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MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
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/* led red */
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MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0
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/* led green */
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MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
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/* led blue */
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MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
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/* Profibus IRQ */
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MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
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/* FPGA IRQ currently unused*/
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MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
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/* Display reset because of clock failure */
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MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
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/* spi bus #2 SS driver enable */
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MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
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/* RST_LOC# PHY reset input (has pull-down!)*/
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MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
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/* Touchscreen IRQ */
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MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
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/* PCIe reset */
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MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
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/* make sure pin is GPIO and not ENET_REF_CLK */
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MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
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/* TPM PP */
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MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0
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/* TPM Reset */
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MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
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MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
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MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
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>;
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};
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pinctrl_usbotg: usbotggrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
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MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
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MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
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MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
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MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
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MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
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MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
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/* SD1 card detect input */
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MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
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/* SD1 write protect input */
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MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
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MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
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MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
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MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
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MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
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MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
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MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
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MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
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MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
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MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
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>;
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};
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};
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@@ -158,6 +158,17 @@ config TARGET_ARISTAINETOS2BCSL
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imply CMD_SATA
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imply CMD_DM
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config TARGET_ARISTAINETOS2C
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bool "Support aristainetos2-revC"
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select BOARD_LATE_INIT
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select MX6DL
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select SYS_I2C_MXC
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select MXC_UART
|
||||
select FEC_MXC
|
||||
select DM
|
||||
imply CMD_SATA
|
||||
imply CMD_DM
|
||||
|
||||
config TARGET_CGTQMX6EVAL
|
||||
bool "cgtqmx6eval"
|
||||
select BOARD_LATE_INIT
|
||||
|
||||
Reference in New Issue
Block a user