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board: phytec: phycore_imx8mp: Change debug UART

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With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Teresa Remmet
2021-07-07 12:57:59 +00:00
committed by Stefano Babic
parent 3240d9c63a
commit 1feac813fe
4 changed files with 13 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
View File

@@ -18,7 +18,7 @@
u-boot,dm-spl;
};
&pinctrl_uart2 {
&pinctrl_uart1 {
u-boot,dm-spl;
};
@@ -54,7 +54,7 @@
u-boot,dm-spl;
};
&uart2 {
&uart1 {
u-boot,dm-spl;
};

12
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
View File

@@ -16,7 +16,7 @@
"phytec,imx8mp-phycore-som", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
stdout-path = &uart1;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
@@ -95,9 +95,9 @@
};
/* debug console */
&uart2 {
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
@@ -154,10 +154,10 @@
>;
};
pinctrl_uart2: uart2grp {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
>;
};