From 532a54e65278564ac16878cda7146d247d8b3193 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Sun, 3 Mar 2019 11:02:10 -0600 Subject: [PATCH 01/10] ARM: socfpga: fix data and tag latency values for pl310 cache controller The values for the data and tag latency settings on the PL310 caches controller is an (n-1). For example, the "arm,tag-latency" is specified as <1 1 1>, so the values that should be written to register should be 0x000. And for the "arm,data-latency" specified as <2 1 1>, the register value should be 0x010. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index fcf211d62b..ec8339e045 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -62,8 +62,8 @@ void v7_outer_cache_enable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); - writel(0x111, &pl310->pl310_tag_latency_ctrl); - writel(0x121, &pl310->pl310_data_latency_ctrl); + writel(0x0, &pl310->pl310_tag_latency_ctrl); + writel(0x10, &pl310->pl310_data_latency_ctrl); /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, From 71fc4825f72cc8f9a066e0a23d71e86242738561 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 5 Mar 2019 18:37:02 +0100 Subject: [PATCH 02/10] ddr: socfpga: Fix IO in Arria10 DDR driver The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- drivers/ddr/altera/sdram_arria10.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 29ea7492f3..6724eb29f1 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -304,7 +304,7 @@ static void sdram_mmr_init(void) * bit[9:6] = Minor Release # * bit[14:10] = Major Release # */ - if ((socfpga_io48_mmr_base->niosreserve1 >> 6) & 0x1FF) { + if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) { update_value = readl(&socfpga_io48_mmr_base->niosreserve0); writel(((update_value & 0xFF) >> 5), &socfpga_ecc_hmc_base->ddrioctrl); @@ -394,7 +394,7 @@ static void sdram_mmr_init(void) caltim0_cfg_act_to_rdwr - (ctrlcfg0_cfg_ctrl_burst_len >> 2)); - io48_value = ((((socfpga_io48_mmr_base->dramtiming0 & + io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) & ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 + (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) - /* Up to here was in memory cycles so divide by 2 */ @@ -424,7 +424,7 @@ static void sdram_mmr_init(void) &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode); /* Configure the read latency [0xFFD12414] */ - writel(((socfpga_io48_mmr_base->dramtiming0 & + writel(((readl(&socfpga_io48_mmr_base->dramtiming0) & ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) + DDR_READ_LATENCY_DELAY, &socfpga_noc_ddr_scheduler_base-> From dc3249b91b0c5dffdbd42426a3535bea5e14448f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Mar 2019 17:18:22 +0100 Subject: [PATCH 03/10] ddr: socfpga: Fix newline in debug print on A10 The debug print is missing a newline, add it. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- drivers/ddr/altera/sdram_arria10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index 6724eb29f1..be5ce778e8 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -270,7 +270,7 @@ static u64 sdram_size_calc(void) size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) & ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK)); - debug("SDRAM size=%llu", size); + debug("SDRAM size=%llu\n", size); return size; } From 7544ad0303013e625c9500a4d87d4e5bfe369ee4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 8 May 2018 20:32:01 +0200 Subject: [PATCH 04/10] ARM: socfpga: Disable D cache in SPL The bootrom seems to leave the D-cache in messed up state, make sure the SPL disables it so it can not interfere with operation. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- arch/arm/mach-socfpga/spl_a10.c | 2 ++ include/configs/socfpga_arria10_socdk.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index c97eacb424..c8e73d47c0 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -77,6 +77,8 @@ void spl_board_init(void) void board_init_f(ulong dummy) { + dcache_disable(); + socfpga_init_security_policies(); socfpga_sdram_remap_zero(); diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h index 58e446b60a..0f116fbf2d 100644 --- a/include/configs/socfpga_arria10_socdk.h +++ b/include/configs/socfpga_arria10_socdk.h @@ -15,8 +15,6 @@ /* * U-Boot general configurations */ -/* Cache options */ -#define CONFIG_SYS_DCACHE_OFF /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 From 60082d3b3ff17fc0c5ae6c1cdd176219554ed61f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 8 May 2018 18:44:00 +0200 Subject: [PATCH 05/10] ARM: socfpga: Drop CONFIG_SYS_NAND_BAD_BLOCK_POS This is not used anywhere, so drop it. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- include/configs/socfpga_common.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c9cbf8f5e3..f182e9e71b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -280,7 +280,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 #endif From bd6363a7b77f0a5737b736f80179b6f53ef2cf7c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 8 May 2018 18:44:43 +0200 Subject: [PATCH 06/10] ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB. Handle the difference. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- include/configs/socfpga_common.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f182e9e71b..181af9b646 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -275,12 +275,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* SPL QSPI boot support */ #ifdef CONFIG_SPL_SPI_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x100000 +#endif #endif /* SPL NAND boot support */ #ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 +#endif #endif /* From a356fb60be5a853ab73e5b58c8bfcd8e3abc89ea Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 6 Mar 2019 20:07:55 +0100 Subject: [PATCH 07/10] ARM: socfpga: Fix A10 SoCDK Kconfig The Kconfig checked for SoCFPGA Arria10 as a platform, instead of checking for specific board configuration, which works with one single platform in tree, but not with multiple. Fix it. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- board/altera/arria10-socdk/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig index b80cc6d6f9..621dc97024 100644 --- a/board/altera/arria10-socdk/Kconfig +++ b/board/altera/arria10-socdk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_SOCFPGA_ARRIA10 +if TARGET_SOCFPGA_ARRIA10_SOCDK config SYS_CPU default "armv7" From ffd1e1a336730b6991c2ae7e7b0605e99d4f2b06 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 Mar 2019 19:11:55 +0100 Subject: [PATCH 08/10] ddr: socfpga: Fix EMIF clear timeout The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- drivers/ddr/altera/sdram_arria10.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index be5ce778e8..b450a1b1be 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -31,7 +31,6 @@ static u64 sdram_size_calc(void); #define DDR_REG_CORE2SEQ 0xFFD05078 #define DDR_READ_LATENCY_DELAY 40 #define DDR_SIZE_2GB_HEX 0x80000000 -#define DDR_MAX_TRIES 0x00100000 #define IO48_MMR_DRAMSTS 0xFFCFA0EC #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110 @@ -133,22 +132,16 @@ static unsigned char ddr_wait_bit(u32 ereg, u32 bit, static int emif_clear(void) { - u32 i = DDR_MAX_TRIES; - u8 ret = 0; - writel(0, DDR_REG_CORE2SEQ); - do { - ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, - SEQ2CORE_MASK, 1, 50, 0); - } while (ret && (--i > 0)); - - return !i; + return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, + SEQ2CORE_MASK, 0, 1000, 0); } static int emif_reset(void) { u32 c2s, s2c; + int ret; c2s = readl(DDR_REG_CORE2SEQ); s2c = readl(DDR_REG_SEQ2CORE); @@ -159,9 +152,12 @@ static int emif_reset(void) readl(IO48_MMR_NIOS2_RESERVE2), readl(IO48_MMR_DRAMSTS)); - if ((s2c & SEQ2CORE_MASK) && emif_clear()) { - debug("failed emif_clear()\n"); - return -EPERM; + if (s2c & SEQ2CORE_MASK) { + ret = emif_clear(); + if (ret) { + debug("failed emif_clear()\n"); + return -EPERM; + } } writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); @@ -173,7 +169,8 @@ static int emif_reset(void) debug("emif_reset interrupt acknowledged\n"); } - if (emif_clear()) { + ret = emif_clear(); + if (ret) { debug("emif_clear() failed\n"); return -EPERM; } From 8297dd1d934281175ffa8646a2e3200755402db5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 Mar 2019 21:57:58 +0100 Subject: [PATCH 09/10] ddr: socfpga: Clean up EMIF reset The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- drivers/ddr/altera/sdram_arria10.c | 33 +++++++----------------------- 1 file changed, 7 insertions(+), 26 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index b450a1b1be..ff83c61002 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -108,28 +108,6 @@ static int is_sdram_cal_success(void) return readl(&socfpga_ecc_hmc_base->ddrcalstat); } -static unsigned char ddr_get_bit(u32 ereg, unsigned char bit) -{ - u32 reg = readl(ereg); - - return (reg & BIT(bit)) ? 1 : 0; -} - -static unsigned char ddr_wait_bit(u32 ereg, u32 bit, - u32 expected, u32 timeout_usec) -{ - u32 tmr; - - for (tmr = 0; tmr < timeout_usec; tmr += 100) { - udelay(100); - WATCHDOG_RESET(); - if (ddr_get_bit(ereg, bit) == expected) - return 0; - } - - return 1; -} - static int emif_clear(void) { writel(0, DDR_REG_CORE2SEQ); @@ -162,13 +140,16 @@ static int emif_reset(void) writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ); - if (ddr_wait_bit(DDR_REG_SEQ2CORE, SEQ2CORE_INT_RESP_BIT, 0, 1000000)) { + ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE, + SEQ2CORE_INT_RESP_BIT, false, 1000, false); + if (ret) { debug("emif_reset failed to see interrupt acknowledge\n"); - return -EPERM; - } else { - debug("emif_reset interrupt acknowledged\n"); + emif_clear(); + return ret; } + mdelay(1); + ret = emif_clear(); if (ret) { debug("emif_clear() failed\n"); From 88c3bb49e1bf2b808cbad1fbdeda09480ae580a7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 9 Mar 2019 21:58:09 +0100 Subject: [PATCH 10/10] ddr: socfpga: Clean up ddr_setup() Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Simon Goldschmidt Cc: Tien Fong Chee --- drivers/ddr/altera/sdram_arria10.c | 39 ++++++++++-------------------- 1 file changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c index ff83c61002..1777e7e1a5 100644 --- a/drivers/ddr/altera/sdram_arria10.c +++ b/drivers/ddr/altera/sdram_arria10.c @@ -102,12 +102,6 @@ static int match_ddr_conf(u32 ddr_conf) return 0; } -/* Check whether SDRAM is successfully Calibrated */ -static int is_sdram_cal_success(void) -{ - return readl(&socfpga_ecc_hmc_base->ddrcalstat); -} - static int emif_clear(void) { writel(0, DDR_REG_CORE2SEQ); @@ -167,30 +161,23 @@ static int emif_reset(void) static int ddr_setup(void) { - int i, j, ddr_setup_complete = 0; + int i, ret; - /* Try 3 times to do a calibration */ - for (i = 0; (i < 3) && !ddr_setup_complete; i++) { - WATCHDOG_RESET(); + /* Try 32 times to do a calibration */ + for (i = 0; i < 32; i++) { + mdelay(500); + ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat, + BIT(0), true, 500, false); + if (!ret) + return 0; - /* A delay to wait for calibration bit to set */ - for (j = 0; (j < 10) && !ddr_setup_complete; j++) { - mdelay(500); - ddr_setup_complete = is_sdram_cal_success(); - } - - if (!ddr_setup_complete) - if (emif_reset()) - puts("Error: Failed to reset EMIF\n"); + ret = emif_reset(); + if (ret) + puts("Error: Failed to reset EMIF\n"); } - /* After 3 times trying calibration */ - if (!ddr_setup_complete) { - puts("Error: Could Not Calibrate SDRAM\n"); - return -EPERM; - } - - return 0; + puts("Error: Could Not Calibrate SDRAM\n"); + return -EPERM; } static int sdram_is_ecc_enabled(void)