Merge git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
@@ -19,7 +19,6 @@
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#else
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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@@ -80,8 +79,6 @@
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR 0x77
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@@ -51,7 +51,6 @@
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#define CONFIG_FSL_IFC /* Enable IFC Support */
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#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_TSEC_ENET
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#define CONFIG_ENV_OVERWRITE
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@@ -103,7 +103,6 @@
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#define CONFIG_DOS_PARTITION
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_TSEC_ENET /* ethernet */
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@@ -102,7 +102,6 @@
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#define CONFIG_DOS_PARTITION
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_TSEC_ENET
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#define CONFIG_ENV_OVERWRITE
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@@ -51,7 +51,6 @@
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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@@ -36,7 +36,6 @@
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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/*
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* sysclk for MPC85xx
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@@ -25,8 +25,6 @@
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#ifndef __ASSEMBLY__
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@@ -28,8 +28,6 @@
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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@@ -35,7 +35,6 @@
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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@@ -24,7 +24,6 @@
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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@@ -34,7 +34,6 @@
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
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/*
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@@ -28,7 +28,6 @@
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_QE /* Enable QE */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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@@ -26,7 +26,6 @@
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_QE /* Enable QE */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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@@ -39,8 +39,6 @@
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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@@ -42,7 +42,6 @@
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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@@ -72,7 +71,6 @@
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
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@@ -44,7 +44,6 @@
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#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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@@ -87,7 +86,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
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@@ -19,7 +19,6 @@
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xD0001000
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#define CONFIG_SPL_PAD_TO 0x18000
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@@ -45,7 +44,6 @@
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#define CONFIG_SPL_SPI_FLASH_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xD0001000
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#define CONFIG_SPL_PAD_TO 0x18000
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@@ -201,7 +199,6 @@
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#define CONFIG_DOS_PARTITION
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_TSEC_ENET
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#define CONFIG_ENV_OVERWRITE
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@@ -15,7 +15,6 @@
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_PAD_TO 0x20000
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@@ -36,7 +35,6 @@
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#define CONFIG_SPL_SPI_FLASH_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_PAD_TO 0x20000
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@@ -115,8 +113,6 @@
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
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@@ -35,7 +35,6 @@
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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@@ -58,8 +58,6 @@
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_DPAA_RMAN /* RMan */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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#ifdef CONFIG_SYS_NO_FLASH
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@@ -28,7 +28,6 @@
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#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
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#define CONFIG_FSL_IFC /* Enable IFC Support */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_DEEP_SLEEP
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@@ -42,7 +41,6 @@
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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@@ -28,7 +28,6 @@
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#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
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#define CONFIG_FSL_IFC /* Enable IFC Support */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
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@@ -45,7 +44,6 @@
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x30001000
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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@@ -69,8 +69,6 @@
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
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#ifdef CONFIG_SYS_NO_FLASH
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@@ -24,7 +24,6 @@
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#define CONFIG_SPL_FLUSH_IMAGE
|
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x30001000
|
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
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#define CONFIG_SPL_PAD_TO 0x40000
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@@ -180,8 +179,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#ifndef CONFIG_SYS_NO_FLASH
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@@ -41,7 +41,6 @@
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#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
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#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
@@ -49,7 +48,6 @@
|
||||
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||
#define CONFIG_SPL_PAD_TO 0x40000
|
||||
|
||||
@@ -34,7 +34,6 @@
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
@@ -42,7 +41,6 @@
|
||||
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||
#define CONFIG_SPL_PAD_TO 0x40000
|
||||
|
||||
@@ -24,7 +24,6 @@
|
||||
#else
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||
#define CONFIG_SPL_PAD_TO 0x40000
|
||||
|
||||
@@ -23,7 +23,6 @@
|
||||
#else
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||
#define CONFIG_SPL_PAD_TO 0x40000
|
||||
@@ -85,8 +84,6 @@
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
|
||||
@@ -124,8 +124,6 @@
|
||||
|
||||
#define CONFIG_MP
|
||||
|
||||
#define CONFIG_FSL_LAW
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_CMD_SATA
|
||||
|
||||
@@ -42,7 +42,6 @@
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_ADDR_MAP
|
||||
|
||||
@@ -69,8 +69,6 @@
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#ifdef CONFIG_SYS_NO_FLASH
|
||||
|
||||
@@ -59,8 +59,6 @@
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
@@ -46,8 +46,6 @@
|
||||
|
||||
#define CONFIG_SYS_DPAA_RMAN /* RMan */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
/* Environment in SPI Flash */
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
|
||||
@@ -174,7 +174,6 @@
|
||||
#define CONFIG_SPL_MMC_MINIMAL
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x11001000
|
||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
||||
#define CONFIG_SPL_PAD_TO 0x20000
|
||||
@@ -195,7 +194,6 @@
|
||||
#define CONFIG_SPL_SPI_FLASH_MINIMAL
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x11001000
|
||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
||||
#define CONFIG_SPL_PAD_TO 0x20000
|
||||
@@ -274,7 +272,6 @@
|
||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
|
||||
@@ -52,7 +52,6 @@
|
||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_FSL_LAW
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
|
||||
@@ -69,8 +69,6 @@
|
||||
|
||||
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
|
||||
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
|
||||
/*
|
||||
* Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
|
||||
*/
|
||||
|
||||
@@ -46,7 +46,6 @@
|
||||
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
@@ -87,7 +86,6 @@
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
|
||||
|
||||
|
||||
@@ -31,8 +31,6 @@
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
|
||||
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
|
||||
/*
|
||||
* Only possible on E500 Version 2 or newer cores.
|
||||
*/
|
||||
|
||||
@@ -40,8 +40,6 @@
|
||||
#define CONFIG_SRIO1 /* SRIO port 1 */
|
||||
#define CONFIG_SRIO2 /* SRIO port 2 */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
|
||||
@@ -31,7 +31,6 @@
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
|
||||
/*
|
||||
* DDR config
|
||||
@@ -76,7 +75,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
||||
@@ -30,7 +30,6 @@
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
|
||||
/*
|
||||
* DDR config
|
||||
|
||||
@@ -31,7 +31,6 @@
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
#define CONFIG_FSL_ELBC 1
|
||||
|
||||
/*
|
||||
|
||||
@@ -32,7 +32,6 @@
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
|
||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
||||
#define CONFIG_FSL_ELBC 1
|
||||
|
||||
/*
|
||||
|
||||
Reference in New Issue
Block a user