Add support for AMCC Bamboo PPC440EP eval board
Patch by Stefan Roese, 04 Aug 2005
This commit is contained in:
Stefan Roese
@@ -318,6 +318,8 @@ typedef struct emac_440gx_hw_st {
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#define EMAC_M0_RXE (0x08000000)
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#define EMAC_M0_WKE (0x04000000)
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/* on 440GX EMAC_MR1 has a different layout! */
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#if defined(CONFIG_440_GX)
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/* MODE Reg 1 */
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#define EMAC_M1_FDE (0x80000000)
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#define EMAC_M1_ILE (0x40000000)
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@@ -347,6 +349,31 @@ typedef struct emac_440gx_hw_st {
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#define EMAC_M1_OBCI_83 (0x00000010)
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#define EMAC_M1_OBCI_66 (0x00000008)
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#define EMAC_M1_RSVD1 (0x00000007)
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#else /* defined(CONFIG_440_GX) */
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/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
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#define EMAC_M1_FDE 0x80000000
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#define EMAC_M1_ILE 0x40000000
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#define EMAC_M1_VLE 0x20000000
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#define EMAC_M1_EIFC 0x10000000
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#define EMAC_M1_APP 0x08000000
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#define EMAC_M1_AEMI 0x02000000
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#define EMAC_M1_IST 0x01000000
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#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
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#define EMAC_M1_MF_100MBPS 0x00400000
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#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
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#define EMAC_M1_RFS_2K 0x00200000
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#define EMAC_M1_RFS_1K 0x00100000
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#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
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#define EMAC_M1_TX_FIFO_1K 0x00040000
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#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
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#define EMAC_M1_TR0_MULTI 0x00008000
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#define EMAC_M1_TR1_DEPEND 0x00004000
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#define EMAC_M1_TR1_MULTI 0x00002000
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#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
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#define EMAC_M1_JUMBO_ENABLE 0x00001000
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#endif /* defined(CONFIG_440_EP) || defined(CONFIG_440_GR) */
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#endif /* defined(CONFIG_440_GX) */
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/* Transmit Mode Register 0 */
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#define EMAC_TXM0_GNP0 (0x80000000)
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#define EMAC_TXM0_GNP1 (0x40000000)
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@@ -30,59 +30,52 @@
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
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#define CONFIG_440_EP 1 /* Specific PPC440EP support */
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#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
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#define CONFIG_440_EP 1 /* Specific PPC440EP support */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#undef CFG_DRAM_TEST /* disable - takes long time! */
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/*#define CONFIG_SYS_CLK_FREQ 66666666 /X* external freq to pll */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory */
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
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#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
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#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
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#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
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#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
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#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
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#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
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/*Don't change either of these*/
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#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
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#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs */
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#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/
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#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/
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/*Don't change either of these*/
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#define CFG_USB_DEVICE 0x50000000
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#define CFG_NVRAM_BASE_ADDR 0x80000000
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#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
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#define CFG_USB_DEVICE 0x50000000
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#define CFG_NVRAM_BASE_ADDR 0x80000000
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#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000)
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in SDRAM)
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*----------------------------------------------------------------------*/
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#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
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#define CFG_INIT_RAM_END 0x2000
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_INIT_RAM_ADDR 0xf0000000 /* DCache */
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#define CFG_INIT_RAM_END 0x1000
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
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#define CFG_KBYTES_SDRAM ( 128 * 1024) /* 128MB */
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/*#define CFG_SDRAM_BANKS (2) */
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#define CFG_SDRAM_BANKS (1)
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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/*define this if you want console on UART1*/
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#define CONFIG_SERIAL_MULTI 1
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/* define this if you want console on UART1 */
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#undef CONFIG_UART1_CONSOLE
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#define CFG_BAUDRATE_TABLE \
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@@ -95,37 +88,57 @@
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* The DS1558 code assumes this condition
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*
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*----------------------------------------------------------------------*/
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#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
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#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
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#define CFG_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */
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#define CONFIG_RTC_DS1556 1 /* DS1556 RTC */
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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/*
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* Define here the location of the environment variables (FLASH or EEPROM).
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* Note: DENX encourages to use redundant environment in FLASH.
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*/
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#if 1
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#else
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#endif
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#if 0 /* test-only */
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
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#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 120000 /* Timeout for Flash Write (in ms) */
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#else
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_ADDR0 0x555
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#define CFG_FLASH_ADDR1 0x2aa
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#define CFG_FLASH_WORD_SIZE unsigned char
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#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
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#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#if 0 /* test-only */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
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*----------------------------------------------------------------------------- */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS {0x50,0x51} /* SPD i2c spd addresses */
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#define CFG_SDRAM_ONBOARD_SIZE (64 << 20) /* Bamboo has onboard and DIMM-slots!*/
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/*-----------------------------------------------------------------------
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* I2C
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@@ -135,44 +148,71 @@
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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#undef CFG_ENV_IS_IN_NVRAM /*No NVRAM on board*/
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#undef CFG_ENV_IS_IN_FLASH /* ... not in flash */
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#define CFG_ENV_IS_IN_EEPROM 1
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CFG_I2C_MULTI_EEPROMS
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#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
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#define CFG_ENV_OFFSET 0x0
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#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_BOOTCOMMAND "bootm 0xfe000000" /* autoboot command */
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#define CONFIG_BOOTDELAY 3 /* disable autoboot */
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#ifdef CFG_ENV_IS_IN_EEPROM
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#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
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#define CFG_ENV_OFFSET 0x0
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#endif /* CFG_ENV_IS_IN_EEPROM */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=bamboo\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath)\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
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":$(hostname):$(netdev):off panic=1\0" \
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"addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm $(kernel_addr)\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm $(kernel_addr) $(ramdisk_addr)\0" \
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"net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/eldk/ppc_4xx\0" \
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"bootfile=/tftpboot/bamboo/uImage\0" \
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"kernel_addr=fff00000\0" \
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"ramdisk_addr=fff10000\0" \
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"load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \
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"update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \
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"cp.b 100000 fff80000 80000;" \
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"setenv filesize;saveenv\0" \
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"upd=run load;run update\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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#if 0
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_NET_MULTI 1 /* required for netconsole */
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#define CONFIG_PHY1_ADDR 3
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#define CONFIG_NET_MULTI 1 /* required for netconsole */
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#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
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#define CONFIG_PHY1_ADDR 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 10.0.4.251
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#define CONFIG_ETHADDR 00:10:EC:00:12:34
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#define CONFIG_ETH1ADDR 00:10:EC:00:12:35
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#define CONFIG_NO_PHY_RESET 1 /* no PHY reset on bamboo!!! */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CONFIG_SERVERIP 10.0.4.115
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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/* Partitions */
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#define CONFIG_MAC_PARTITION
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@@ -188,59 +228,23 @@
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#define USB_2_0_DEVICE
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#endif /*CONFIG_440_EP*/
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#ifdef DEBUG
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#define CONFIG_PANIC_HANG
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#else
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#define CONFIG_HW_WATCHDOG /* watchdog */
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#endif
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#ifdef CONFIG_440_EP
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/* Need to define POST */
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_ECHO | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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/* CFG_CMD_EXT2 |*/ \
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/* CFG_CMD_FAT |*/ \
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CFG_CMD_I2C | \
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/* CFG_CMD_IDE |*/ \
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CFG_CMD_IRQ | \
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/* CFG_CMD_KGDB |*/ \
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CFG_CMD_MII | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_FLASH | \
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/* CFG_CMD_SPI |*/ \
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CFG_CMD_USB | \
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0 ) & ~CFG_CMD_IMLS)
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#else
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#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_ECHO | \
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CFG_CMD_EEPROM | \
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CFG_CMD_ELF | \
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/* CFG_CMD_EXT2 |*/ \
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/* CFG_CMD_FAT |*/ \
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CFG_CMD_I2C | \
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/* CFG_CMD_IDE |*/ \
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CFG_CMD_IRQ | \
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/* CFG_CMD_KGDB |*/ \
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CFG_CMD_MII | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_FLASH | \
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/* CFG_CMD_SPI |*/ \
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0 ) & ~CFG_CMD_IMLS)
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#endif
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
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CFG_CMD_ASKENV | \
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CFG_CMD_DATE | \
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CFG_CMD_DHCP | \
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CFG_CMD_DIAG | \
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CFG_CMD_ELF | \
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CFG_CMD_I2C | \
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CFG_CMD_IRQ | \
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CFG_CMD_MII | \
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CFG_CMD_NET | \
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CFG_CMD_NFS | \
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CFG_CMD_PCI | \
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CFG_CMD_PING | \
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CFG_CMD_REGINFO | \
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CFG_CMD_SDRAM | \
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CFG_CMD_USB | \
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CFG_CMD_SNTP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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@@ -263,8 +267,8 @@
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#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x100000 /* default load address */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_LYNXKDI 1 /* support kdi files */
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CONFIG_LYNXKDI 1 /* support kdi files */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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@@ -273,18 +277,18 @@
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*-----------------------------------------------------------------------
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
|
||||
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
|
||||
#define CFG_PCI_TARGET_INIT
|
||||
#define CFG_PCI_MASTER_INIT
|
||||
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
|
||||
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
|
||||
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
@@ -292,10 +296,11 @@
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
|
||||
#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
|
||||
#define CFG_CACHELINE_SIZE 32 /* ... */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
|
||||
152
include/ppc440.h
152
include/ppc440.h
@@ -331,6 +331,158 @@
|
||||
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
|
||||
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
|
||||
|
||||
/* Pin Function Control Register 1 */
|
||||
#define SDR0_PFC1 0x4101
|
||||
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
|
||||
#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
|
||||
#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
|
||||
#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
|
||||
#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
|
||||
#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
|
||||
#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
|
||||
#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
|
||||
#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
|
||||
#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
|
||||
#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
|
||||
#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
|
||||
#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
|
||||
#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
|
||||
#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
|
||||
#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
|
||||
#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
|
||||
#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
|
||||
#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
|
||||
#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
|
||||
#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
|
||||
#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
|
||||
#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
|
||||
#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
|
||||
|
||||
#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
|
||||
#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
|
||||
|
||||
/* USB Control Register */
|
||||
#define SDR0_USB0 0x0320
|
||||
#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
|
||||
#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
|
||||
#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
|
||||
#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
|
||||
#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
|
||||
#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
|
||||
|
||||
/* CUST0 Customer Configuration Register0 */
|
||||
#define SDR0_CUST0 0x4000
|
||||
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
|
||||
#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
|
||||
#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
|
||||
#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
|
||||
|
||||
#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
|
||||
#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
|
||||
#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
|
||||
|
||||
#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
|
||||
#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
|
||||
#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
|
||||
|
||||
#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
|
||||
#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
|
||||
#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
|
||||
|
||||
#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
|
||||
#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
|
||||
#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
|
||||
|
||||
#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
|
||||
#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
|
||||
#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
|
||||
|
||||
#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
|
||||
#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
|
||||
#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
|
||||
|
||||
#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
|
||||
#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
|
||||
#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
|
||||
|
||||
#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
|
||||
#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
|
||||
|
||||
/* CUST1 Customer Configuration Register1 */
|
||||
#define SDR0_CUST1 0x4002
|
||||
#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
|
||||
#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||
#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||
|
||||
/* Pin Function Control Register 0 */
|
||||
#define SDR0_PFC0 0x4100
|
||||
#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
|
||||
#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
|
||||
#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
|
||||
#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
|
||||
#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
|
||||
|
||||
/* Pin Function Control Register 1 */
|
||||
#define SDR0_PFC1 0x4101
|
||||
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
|
||||
#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
|
||||
#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
|
||||
#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
|
||||
#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
|
||||
#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
|
||||
#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
|
||||
#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
|
||||
#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
|
||||
#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
|
||||
#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
|
||||
#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
|
||||
#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
|
||||
#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
|
||||
#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
|
||||
#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
|
||||
#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
|
||||
#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
|
||||
#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
|
||||
#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
|
||||
#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
|
||||
#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
|
||||
#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
|
||||
#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
|
||||
|
||||
#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
|
||||
#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
|
||||
#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
|
||||
|
||||
/* Miscealleneaous Function Reg. */
|
||||
#define SDR0_MFR 0x4300
|
||||
#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
|
||||
#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
|
||||
#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
|
||||
#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
|
||||
#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
|
||||
#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
|
||||
#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
|
||||
#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
|
||||
#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
|
||||
#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||
#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
|
||||
|
||||
#define SDR0_MFR_ERRATA3_EN0 0x00800000
|
||||
#define SDR0_MFR_ERRATA3_EN1 0x00400000
|
||||
#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
|
||||
#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
|
||||
#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
|
||||
#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
|
||||
#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
|
||||
|
||||
#else
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
|
||||
Reference in New Issue
Block a user