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ARM: dts: rmobile: Import R8A7790 DTS from Linux 4.15-rc8

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Import the Renesas R8A7790 DTS and headers from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut
2018-01-07 20:17:23 +01:00
committed by Marek Vasut
parent 319202640a
commit 16b6e4aa37
5 changed files with 2769 additions and 0 deletions
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162
include/dt-bindings/clock/r8a7790-clock.h Normal file
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/*
* Copyright 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
#define __DT_BINDINGS_CLOCK_R8A7790_H__
/* CPG */
#define R8A7790_CLK_MAIN 0
#define R8A7790_CLK_PLL0 1
#define R8A7790_CLK_PLL1 2
#define R8A7790_CLK_PLL3 3
#define R8A7790_CLK_LB 4
#define R8A7790_CLK_QSPI 5
#define R8A7790_CLK_SDH 6
#define R8A7790_CLK_SD0 7
#define R8A7790_CLK_SD1 8
#define R8A7790_CLK_Z 9
#define R8A7790_CLK_RCAN 10
#define R8A7790_CLK_ADSP 11
/* MSTP0 */
#define R8A7790_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7790_CLK_VCP1 0
#define R8A7790_CLK_VCP0 1
#define R8A7790_CLK_VPC1 2
#define R8A7790_CLK_VPC0 3
#define R8A7790_CLK_JPU 6
#define R8A7790_CLK_SSP1 9
#define R8A7790_CLK_TMU1 11
#define R8A7790_CLK_3DG 12
#define R8A7790_CLK_2DDMAC 15
#define R8A7790_CLK_FDP1_2 17
#define R8A7790_CLK_FDP1_1 18
#define R8A7790_CLK_FDP1_0 19
#define R8A7790_CLK_TMU3 21
#define R8A7790_CLK_TMU2 22
#define R8A7790_CLK_CMT0 24
#define R8A7790_CLK_TMU0 25
#define R8A7790_CLK_VSP1_DU1 27
#define R8A7790_CLK_VSP1_DU0 28
#define R8A7790_CLK_VSP1_R 30
#define R8A7790_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7790_CLK_SCIFA2 2
#define R8A7790_CLK_SCIFA1 3
#define R8A7790_CLK_SCIFA0 4
#define R8A7790_CLK_MSIOF2 5
#define R8A7790_CLK_SCIFB0 6
#define R8A7790_CLK_SCIFB1 7
#define R8A7790_CLK_MSIOF1 8
#define R8A7790_CLK_MSIOF3 15
#define R8A7790_CLK_SCIFB2 16
#define R8A7790_CLK_SYS_DMAC1 18
#define R8A7790_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7790_CLK_IIC2 0
#define R8A7790_CLK_TPU0 4
#define R8A7790_CLK_MMCIF1 5
#define R8A7790_CLK_SCIF2 10
#define R8A7790_CLK_SDHI3 11
#define R8A7790_CLK_SDHI2 12
#define R8A7790_CLK_SDHI1 13
#define R8A7790_CLK_SDHI0 14
#define R8A7790_CLK_MMCIF0 15
#define R8A7790_CLK_IIC0 18
#define R8A7790_CLK_PCIEC 19
#define R8A7790_CLK_IIC1 23
#define R8A7790_CLK_SSUSB 28
#define R8A7790_CLK_CMT1 29
#define R8A7790_CLK_USBDMAC0 30
#define R8A7790_CLK_USBDMAC1 31
/* MSTP4 */
#define R8A7790_CLK_IRQC 7
#define R8A7790_CLK_INTC_SYS 8
/* MSTP5 */
#define R8A7790_CLK_AUDIO_DMAC1 1
#define R8A7790_CLK_AUDIO_DMAC0 2
#define R8A7790_CLK_ADSP_MOD 6
#define R8A7790_CLK_THERMAL 22
#define R8A7790_CLK_PWM 23
/* MSTP7 */
#define R8A7790_CLK_EHCI 3
#define R8A7790_CLK_HSUSB 4
#define R8A7790_CLK_HSCIF1 16
#define R8A7790_CLK_HSCIF0 17
#define R8A7790_CLK_SCIF1 20
#define R8A7790_CLK_SCIF0 21
#define R8A7790_CLK_DU2 22
#define R8A7790_CLK_DU1 23
#define R8A7790_CLK_DU0 24
#define R8A7790_CLK_LVDS1 25
#define R8A7790_CLK_LVDS0 26
/* MSTP8 */
#define R8A7790_CLK_MLB 2
#define R8A7790_CLK_VIN3 8
#define R8A7790_CLK_VIN2 9
#define R8A7790_CLK_VIN1 10
#define R8A7790_CLK_VIN0 11
#define R8A7790_CLK_ETHERAVB 12
#define R8A7790_CLK_ETHER 13
#define R8A7790_CLK_SATA1 14
#define R8A7790_CLK_SATA0 15
/* MSTP9 */
#define R8A7790_CLK_GPIO5 7
#define R8A7790_CLK_GPIO4 8
#define R8A7790_CLK_GPIO3 9
#define R8A7790_CLK_GPIO2 10
#define R8A7790_CLK_GPIO1 11
#define R8A7790_CLK_GPIO0 12
#define R8A7790_CLK_RCAN1 15
#define R8A7790_CLK_RCAN0 16
#define R8A7790_CLK_QSPI_MOD 17
#define R8A7790_CLK_IICDVFS 26
#define R8A7790_CLK_I2C3 28
#define R8A7790_CLK_I2C2 29
#define R8A7790_CLK_I2C1 30
#define R8A7790_CLK_I2C0 31
/* MSTP10 */
#define R8A7790_CLK_SSI_ALL 5
#define R8A7790_CLK_SSI9 6
#define R8A7790_CLK_SSI8 7
#define R8A7790_CLK_SSI7 8
#define R8A7790_CLK_SSI6 9
#define R8A7790_CLK_SSI5 10
#define R8A7790_CLK_SSI4 11
#define R8A7790_CLK_SSI3 12
#define R8A7790_CLK_SSI2 13
#define R8A7790_CLK_SSI1 14
#define R8A7790_CLK_SSI0 15
#define R8A7790_CLK_SCU_ALL 17
#define R8A7790_CLK_SCU_DVC1 18
#define R8A7790_CLK_SCU_DVC0 19
#define R8A7790_CLK_SCU_CTU1_MIX1 20
#define R8A7790_CLK_SCU_CTU0_MIX0 21
#define R8A7790_CLK_SCU_SRC9 22
#define R8A7790_CLK_SCU_SRC8 23
#define R8A7790_CLK_SCU_SRC7 24
#define R8A7790_CLK_SCU_SRC6 25
#define R8A7790_CLK_SCU_SRC5 26
#define R8A7790_CLK_SCU_SRC4 27
#define R8A7790_CLK_SCU_SRC3 28
#define R8A7790_CLK_SCU_SRC2 29
#define R8A7790_CLK_SCU_SRC1 30
#define R8A7790_CLK_SCU_SRC0 31
#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */

52
include/dt-bindings/clock/r8a7790-cpg-mssr.h Normal file
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/*
* Copyright (C) 2015 Renesas Electronics Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a7790 CPG Core Clocks */
#define R8A7790_CLK_Z 0
#define R8A7790_CLK_Z2 1
#define R8A7790_CLK_ZG 2
#define R8A7790_CLK_ZTR 3
#define R8A7790_CLK_ZTRD2 4
#define R8A7790_CLK_ZT 5
#define R8A7790_CLK_ZX 6
#define R8A7790_CLK_ZS 7
#define R8A7790_CLK_HP 8
#define R8A7790_CLK_I 9
#define R8A7790_CLK_B 10
#define R8A7790_CLK_LB 11
#define R8A7790_CLK_P 12
#define R8A7790_CLK_CL 13
#define R8A7790_CLK_M2 14
#define R8A7790_CLK_ADSP 15
#define R8A7790_CLK_IMP 16
#define R8A7790_CLK_ZB3 17
#define R8A7790_CLK_ZB3D2 18
#define R8A7790_CLK_DDR 19
#define R8A7790_CLK_SDH 20
#define R8A7790_CLK_SD0 21
#define R8A7790_CLK_SD1 22
#define R8A7790_CLK_SD2 23
#define R8A7790_CLK_SD3 24
#define R8A7790_CLK_MMC0 25
#define R8A7790_CLK_MMC1 26
#define R8A7790_CLK_MP 27
#define R8A7790_CLK_SSP 28
#define R8A7790_CLK_SSPRS 29
#define R8A7790_CLK_QSPI 30
#define R8A7790_CLK_CP 31
#define R8A7790_CLK_RCAN 32
#define R8A7790_CLK_R 33
#define R8A7790_CLK_OSC 34
#endif /* __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__ */

34
include/dt-bindings/power/r8a7790-sysc.h Normal file
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/*
* Copyright (C) 2016 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__
#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A7790_PD_CA15_CPU0 0
#define R8A7790_PD_CA15_CPU1 1
#define R8A7790_PD_CA15_CPU2 2
#define R8A7790_PD_CA15_CPU3 3
#define R8A7790_PD_CA7_CPU0 5
#define R8A7790_PD_CA7_CPU1 6
#define R8A7790_PD_CA7_CPU2 7
#define R8A7790_PD_CA7_CPU3 8
#define R8A7790_PD_CA15_SCU 12
#define R8A7790_PD_SH_4A 16
#define R8A7790_PD_RGX 20
#define R8A7790_PD_CA7_SCU 21
#define R8A7790_PD_IMP 24
/* Always-on power area */
#define R8A7790_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */