Merge branch 'master' of git://git.denx.de/u-boot-pxa
This commit is contained in:
Wolfgang Denk
@@ -112,6 +112,39 @@ vidinfo_t panel_info = {
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vl_efw: 0,
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};
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#endif /* CONFIG_SHARP_LM8V31 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_VOIPAC_LCD
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# define LCD_BPP LCD_COLOR8
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# define LCD_INVERT_COLORS
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x043008f8
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# define REG_LCCR3 0x0340FF08
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vidinfo_t panel_info = {
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vl_col: 640,
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vl_row: 480,
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vl_width: 157,
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vl_height: 118,
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vl_clkp: CONFIG_SYS_HIGH,
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vl_oep: CONFIG_SYS_HIGH,
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vl_hsp: CONFIG_SYS_HIGH,
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vl_vsp: CONFIG_SYS_HIGH,
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vl_dp: CONFIG_SYS_HIGH,
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vl_bpix: LCD_BPP,
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vl_lbw: 0,
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vl_splt: 1,
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vl_clor: 1,
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vl_tft: 1,
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vl_hpw: 32,
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vl_blw: 144,
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vl_elw: 32,
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vl_vpw: 2,
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vl_bfw: 13,
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vl_efw: 30,
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};
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#endif /* CONFIG_VOIPAC_LCD */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_HITACHI_SX14
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@@ -146,6 +179,40 @@ vidinfo_t panel_info = {
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};
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#endif /* CONFIG_HITACHI_SX14 */
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/*----------------------------------------------------------------------*/
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#ifdef CONFIG_LMS283GF05
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# define LCD_BPP LCD_COLOR8
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//# define LCD_INVERT_COLORS
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/* you have to set lccr0 and lccr3 (including pcd) */
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# define REG_LCCR0 0x043008f8
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# define REG_LCCR3 0x03b00009
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vidinfo_t panel_info = {
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vl_col: 240,
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vl_row: 320,
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vl_width: 240,
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vl_height: 320,
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vl_clkp: CONFIG_SYS_HIGH,
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vl_oep: CONFIG_SYS_LOW,
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vl_hsp: CONFIG_SYS_LOW,
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vl_vsp: CONFIG_SYS_LOW,
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vl_dp: CONFIG_SYS_HIGH,
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vl_bpix: LCD_BPP,
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vl_lbw: 0,
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vl_splt: 1,
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vl_clor: 1,
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vl_tft: 1,
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vl_hpw: 4,
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vl_blw: 4,
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vl_elw: 8,
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vl_vpw: 4,
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vl_bfw: 4,
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vl_efw: 8,
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};
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#endif /* CONFIG_LMS283GF05 */
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/*----------------------------------------------------------------------*/
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#if LCD_BPP == LCD_COLOR8
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@@ -292,7 +359,9 @@ static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
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return 0;
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}
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#ifdef CONFIG_CPU_MONAHANS
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static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
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#else
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static void pxafb_setup_gpio (vidinfo_t *vid)
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{
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u_long lccr0;
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@@ -349,6 +418,7 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
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printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
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}
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}
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#endif
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static void pxafb_enable_controller (vidinfo_t *vid)
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{
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@@ -363,7 +433,11 @@ static void pxafb_enable_controller (vidinfo_t *vid)
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FDADR1 = vid->pxa.fdadr1;
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LCCR0 |= LCCR0_ENB;
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#ifdef CONFIG_CPU_MONAHANS
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CKENA |= CKENA_1_LCD;
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#else
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CKEN |= CKEN16_LCD;
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#endif
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debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
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debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
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@@ -34,6 +34,25 @@
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.globl _start
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_start: b reset
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#ifdef CONFIG_PRELOADER
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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ldr pc, _hang
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_hang:
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.word do_hang
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678
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.word 0x12345678 /* now 16*4=64 */
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#else
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ldr pc, _undefined_instruction
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ldr pc, _software_interrupt
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ldr pc, _prefetch_abort
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@@ -49,6 +68,7 @@ _data_abort: .word data_abort
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_not_used: .word not_used
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_irq: .word irq
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_fiq: .word fiq
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#endif /* CONFIG_PRELOADER */
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.balignl 16,0xdeadbeef
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@@ -117,8 +137,10 @@ reset:
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relocate: /* relocate U-Boot to RAM */
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adr r0, _start /* r0 <- current position of code */
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ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
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#ifndef CONFIG_PRELOADER
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cmp r0, r1 /* don't reloc during debug */
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beq stack_setup
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#endif
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ldr r2, _armboot_start
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ldr r3, _bss_start
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@@ -135,28 +157,37 @@ copy_loop:
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/* Set up the stack */
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stack_setup:
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ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
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sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
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sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
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#ifdef CONFIG_PRELOADER
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sub sp, r0, #128 /* leave 32 words for abort-stack */
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#else
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sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
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sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
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#ifdef CONFIG_USE_IRQ
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sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
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#endif /* CONFIG_USE_IRQ */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
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#endif
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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mov r2, #0x00000000 /* clear */
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#ifndef CONFIG_PRELOADER
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clbss_l:str r2, [r0] /* clear loop... */
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add r0, r0, #4
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cmp r0, r1
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ble clbss_l
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#endif
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ldr pc, _start_armboot
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#ifdef CONFIG_ONENAND_IPL
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_start_armboot: .word start_oneboot
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#else
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_start_armboot: .word start_armboot
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#endif
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/****************************************************************************/
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/* */
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@@ -296,7 +327,7 @@ setspeed_done:
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*/
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mov pc, lr
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#ifndef CONFIG_PRELOADER
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/****************************************************************************/
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/* */
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/* Interrupt handling */
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@@ -394,6 +425,7 @@ setspeed_done:
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.macro get_fiq_stack @ setup FIQ stack
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ldr sp, FIQ_STACK_START
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.endm
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#endif /* CONFIG_PRELOADER */
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/****************************************************************************/
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@@ -402,6 +434,12 @@ setspeed_done:
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/* */
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/****************************************************************************/
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#ifdef CONFIG_PRELOADER
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.align 5
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do_hang:
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ldr sp, _TEXT_BASE /* use 32 words abort stack */
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bl hang /* hang and never return */
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#else /* !CONFIG_PRELOADER */
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.align 5
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undefined_instruction:
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get_bad_stack
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@@ -461,7 +499,7 @@ fiq:
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get_bad_stack
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bad_save_user_regs
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bl do_fiq
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#endif /* CONFIG_PRELOADER */
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#endif /* CONFIG_USE_IRQ */
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/****************************************************************************/
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324
arch/arm/include/asm/arch-pxa/macro.h
Normal file
324
arch/arm/include/asm/arch-pxa/macro.h
Normal file
@@ -0,0 +1,324 @@
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/*
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* arch/arm/include/asm/arch-pxa/macro.h
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*
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* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_PXA_MACRO_H__
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#define __ASM_ARCH_PXA_MACRO_H__
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#ifdef __ASSEMBLY__
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#include <asm/macro.h>
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#include <asm/arch/pxa-regs.h>
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/*
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* This macro performs a 32bit write to a memory location and makes sure the
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* write operation really happened by performing a read back.
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*
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* Clobbered regs: r4, r5
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*/
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.macro write32rb addr, data
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ldr r4, =\addr
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ldr r5, =\data
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str r5, [r4]
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ldr r5, [r4]
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.endm
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/*
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* This macro waits according to OSCR incrementation
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*
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* Clobbered regs: r4, r5, r6
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*/
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.macro pxa_wait_ticks ticks
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ldr r4, =OSCR
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mov r5, #0
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str r5, [r4]
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ldr r5, =\ticks
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1:
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ldr r6, [r4]
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cmp r5, r6
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bgt 1b
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.endm
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/*
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* This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
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*
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* Clobbered regs: r4, r5
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*/
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.macro pxa_gpio_setup
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write32 GPSR0, CONFIG_SYS_GPSR0_VAL
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write32 GPSR1, CONFIG_SYS_GPSR1_VAL
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write32 GPSR2, CONFIG_SYS_GPSR2_VAL
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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write32 GPSR3, CONFIG_SYS_GPSR3_VAL
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#endif
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write32 GPCR0, CONFIG_SYS_GPCR0_VAL
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write32 GPCR1, CONFIG_SYS_GPCR1_VAL
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write32 GPCR2, CONFIG_SYS_GPCR2_VAL
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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write32 GPCR3, CONFIG_SYS_GPCR3_VAL
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#endif
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write32 GPDR0, CONFIG_SYS_GPDR0_VAL
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write32 GPDR1, CONFIG_SYS_GPDR1_VAL
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write32 GPDR2, CONFIG_SYS_GPDR2_VAL
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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write32 GPDR3, CONFIG_SYS_GPDR3_VAL
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#endif
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write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
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write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
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write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
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write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
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write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
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write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
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#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
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write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
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write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
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#endif
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write32 PSSR, CONFIG_SYS_PSSR_VAL
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.endm
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||||
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||||
/*
|
||||
* This macro sets up the Memory controller of the PXA2xx CPU
|
||||
*
|
||||
* Clobbered regs: r3, r4, r5
|
||||
*/
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.macro pxa_mem_setup
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||||
/* This comes handy when setting MDREFR */
|
||||
ldr r3, =MEMC_BASE
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|
||||
/*
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||||
* 1) Initialize Asynchronous static memory controller
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*/
|
||||
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||||
/* MSC0: nCS(0,1) */
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||||
write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
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||||
/* MSC1: nCS(2,3) */
|
||||
write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
|
||||
/* MSC2: nCS(4,5) */
|
||||
write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
|
||||
|
||||
/*
|
||||
* 2) Initialize Card Interface
|
||||
*/
|
||||
|
||||
/* MECR: Memory Expansion Card Register */
|
||||
write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
|
||||
/* MCMEM0: Card Interface slot 0 timing */
|
||||
write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
|
||||
/* MCMEM1: Card Interface slot 1 timing */
|
||||
write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
|
||||
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
|
||||
write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
|
||||
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
|
||||
write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
|
||||
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
|
||||
write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
|
||||
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
|
||||
write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
|
||||
|
||||
/*
|
||||
* 3) Configure Fly-By DMA register
|
||||
*/
|
||||
|
||||
write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
|
||||
|
||||
/*
|
||||
* 4) Initialize Timing for Sync Memory (SDCLK0)
|
||||
*/
|
||||
|
||||
/*
|
||||
* Before accessing MDREFR we need a valid DRI field, so we set
|
||||
* this to power on defaults + DRI field.
|
||||
*/
|
||||
ldr r5, [r3, #MDREFR_OFFSET]
|
||||
bic r5, r5, #0x0ff
|
||||
bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
|
||||
|
||||
ldr r4, =CONFIG_SYS_MDREFR_VAL
|
||||
mov r6, r4
|
||||
lsl r4, #20
|
||||
lsr r4, #20 /* Get a valid DRI field */
|
||||
|
||||
orr r5, r5, r4 /* MDREFR user config with correct DRI */
|
||||
|
||||
orr r5, #MDREFR_K0RUN
|
||||
orr r5, #MDREFR_SLFRSH
|
||||
bic r5, #MDREFR_APD
|
||||
bic r5, #MDREFR_E1PIN
|
||||
|
||||
str r5, [r3, #MDREFR_OFFSET]
|
||||
ldr r4, [r3, #MDREFR_OFFSET]
|
||||
|
||||
/*
|
||||
* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
|
||||
*/
|
||||
|
||||
/* Initialize SXCNFG register. Assert the enable bits.
|
||||
*
|
||||
* Write SXMRS to cause an MRS command to all enabled banks of
|
||||
* synchronous static memory. Note that SXLCR need not be written
|
||||
* at this time.
|
||||
*/
|
||||
write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
|
||||
|
||||
/*
|
||||
* 6) Initialize SDRAM
|
||||
*/
|
||||
|
||||
bic r6, #MDREFR_SLFRSH
|
||||
str r6, [r3, #MDREFR_OFFSET]
|
||||
ldr r4, [r3, #MDREFR_OFFSET]
|
||||
|
||||
orr r6, #MDREFR_E1PIN
|
||||
str r6, [r3, #MDREFR_OFFSET]
|
||||
ldr r4, [r3, #MDREFR_OFFSET]
|
||||
|
||||
/*
|
||||
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
|
||||
* but not enable each SDRAM partition pair.
|
||||
*/
|
||||
|
||||
/* Fetch platform value of MDCNFG */
|
||||
ldr r4, =CONFIG_SYS_MDCNFG_VAL
|
||||
/* Disable all sdram banks */
|
||||
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
|
||||
bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
|
||||
/* Write initial value of MDCNFG, w/o enabling sdram banks */
|
||||
str r4, [r3, #MDCNFG_OFFSET]
|
||||
ldr r4, [r3, #MDCNFG_OFFSET]
|
||||
|
||||
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
|
||||
pxa_wait_ticks 0x300
|
||||
|
||||
/*
|
||||
* 8) Trigger a number (usually 8) refresh cycles by attempting
|
||||
* non-burst read or write accesses to disabled SDRAM, as commonly
|
||||
* specified in the power up sequence documented in SDRAM data
|
||||
* sheets. The address(es) used for this purpose must not be
|
||||
* cacheable.
|
||||
*/
|
||||
|
||||
ldr r4, =CONFIG_SYS_DRAM_BASE
|
||||
.rept 9
|
||||
str r5, [r4]
|
||||
.endr
|
||||
|
||||
/*
|
||||
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
|
||||
*/
|
||||
|
||||
ldr r5, =CONFIG_SYS_MDCNFG_VAL
|
||||
ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
|
||||
and r5, r5, r4
|
||||
ldr r4, [r3, #MDCNFG_OFFSET]
|
||||
orr r4, r4, r5
|
||||
str r4, [r3, #MDCNFG_OFFSET]
|
||||
ldr r4, [r3, #MDCNFG_OFFSET]
|
||||
|
||||
/*
|
||||
* 10) Write MDMRS.
|
||||
*/
|
||||
|
||||
ldr r4, =CONFIG_SYS_MDMRS_VAL
|
||||
str r4, [r3, #MDMRS_OFFSET]
|
||||
ldr r4, [r3, #MDMRS_OFFSET]
|
||||
|
||||
/*
|
||||
* 11) Enable APD
|
||||
*/
|
||||
|
||||
ldr r4, [r3, #MDREFR_OFFSET]
|
||||
and r6, r6, #MDREFR_APD
|
||||
orr r4, r4, r6
|
||||
str r4, [r3, #MDREFR_OFFSET]
|
||||
ldr r4, [r3, #MDREFR_OFFSET]
|
||||
.endm
|
||||
|
||||
/*
|
||||
* This macro tests if the CPU woke up from sleep and eventually resumes
|
||||
*
|
||||
* Clobbered regs: r4, r5
|
||||
*/
|
||||
.macro pxa_wakeup
|
||||
ldr r4, =RCSR
|
||||
ldr r5, [r4]
|
||||
and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
|
||||
str r5, [r4]
|
||||
teq r5, #RCSR_SMR
|
||||
|
||||
bne pxa_wakeup_exit
|
||||
|
||||
ldr r4, =PSSR
|
||||
mov r5, #PSSR_PH
|
||||
str r5, [r4]
|
||||
|
||||
ldr r4, =PSPR
|
||||
ldr pc, [r4]
|
||||
pxa_wakeup_exit:
|
||||
.endm
|
||||
|
||||
/*
|
||||
* This macro disables all interupts on PXA2xx/PXA3xx CPU
|
||||
*
|
||||
* Clobbered regs: r4, r5
|
||||
*/
|
||||
.macro pxa_intr_setup
|
||||
write32 ICLR, 0
|
||||
write32 ICMR, 0
|
||||
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
|
||||
write32 ICLR2, 0
|
||||
write32 ICMR2, 0
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/*
|
||||
* This macro configures clock on PXA2xx/PXA3xx CPU
|
||||
*
|
||||
* Clobbered regs: r4, r5
|
||||
*/
|
||||
.macro pxa_clock_setup
|
||||
/* Disable the peripheral clocks, and set the core clock frequency */
|
||||
|
||||
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
|
||||
write32 CKEN, CONFIG_SYS_CKEN
|
||||
|
||||
/* Write CCCR */
|
||||
write32 CCCR, CONFIG_SYS_CCCR
|
||||
|
||||
#ifdef CONFIG_RTC
|
||||
/* enable the 32Khz oscillator for RTC and PowerManager */
|
||||
write32 OSCC, #OSCC_OON
|
||||
ldr r4, =OSCC
|
||||
|
||||
/* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
|
||||
2:
|
||||
ldr r5, [r4]
|
||||
ands r5, r5, #1
|
||||
beq 2b
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASM_ARCH_PXA_MACRO_H__ */
|
||||
@@ -1132,10 +1132,18 @@ typedef void (*ExcpHndlr) (void) ;
|
||||
#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
|
||||
#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
|
||||
|
||||
#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
|
||||
#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */
|
||||
#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
|
||||
#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
|
||||
|
||||
#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */
|
||||
#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */
|
||||
#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */
|
||||
|
||||
#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */
|
||||
#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */
|
||||
#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */
|
||||
|
||||
/*
|
||||
* Interrupt Controller
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user