From afffcc7bfa7634ecd733788d7f4d662c43e09727 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Mon, 21 Nov 2011 05:57:39 +0000
Subject: [PATCH 01/34] vision2: Fix checkpatch warning

Fix the following checkpatch warning:

WARNING: braces {} are not necessary for single statement blocks

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 board/ttcontrol/vision2/vision2.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c
index f556d308e3..282de95e95 100644
--- a/board/ttcontrol/vision2/vision2.c
+++ b/board/ttcontrol/vision2/vision2.c
@@ -428,9 +428,8 @@ static void setup_gpios(void)
 	gpio_direction_output(4, 1);
 
 	gpio_direction_output(7, 0);
-	for (i = 65; i < 71; i++) {
+	for (i = 65; i < 71; i++)
 		gpio_direction_output(i, 0);
-	}
 
 	gpio_direction_output(94, 0);
 

From f9c6fac497e1ad4a2a54158eb8c3e8e1450edd5d Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Wed, 30 Nov 2011 23:56:52 +0000
Subject: [PATCH 02/34] ARM: omap3: added common configuration for Technexion
 TAM3517

The TAM3517 is a SOM module that can be used on custom boards.
The patch add a common configuration file that is included
by the boards using this module.

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tapani Utrianen <tapani@technexion.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
 include/configs/tam3517-common.h | 361 +++++++++++++++++++++++++++++++
 1 file changed, 361 insertions(+)
 create mode 100644 include/configs/tam3517-common.h

diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
new file mode 100644
index 0000000000..817d468a72
--- /dev/null
+++ b/include/configs/tam3517-common.h
@@ -0,0 +1,361 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __TAM3517_H
+#define __TAM3517_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP		/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		/* which is a 34XX */
+
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
+					2 * 1024 * 1024)
+/*
+ * DDR related
+ */
+#define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
+#define CONFIG_SERIAL1			/* UART1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/* EHCI */
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+#define CONFIG_USB_STORAGE
+
+/* #define CONFIG_EHCI_DCACHE */
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+#undef CONFIG_CMD_FLASH		/* only NAND on the SOM */
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C
+
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */
+
+/* Redundant Environment */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+						2 * CONFIG_SYS_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/*
+ * ethernet support, EMAC
+ *
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_EMAC_MDIO_PHY_NUM	0
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#define CONFIG_NET_MULTI
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_CONSOLE
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE		(45 << 10)	/* 45 K */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
+					 48, 49, 50, 51, 52, 53, 54, 55,\
+					 56, 57, 58, 59, 60, 61, 62, 63}
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
+						CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_FIT
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+
+/* Setup MTD for NAND on the SOM */
+#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
+				"512k(u-boot),128k(env1)," \
+				"128k(env2),6m(kernel),-(rootfs)"
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_TAM3517_SETTINGS						\
+	"netdev=eth0\0"							\
+	"nandargs=setenv bootargs root=${nandroot} "			\
+		"rootfstype=${nandrootfstype}\0"			\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip_sta=setenv bootargs ${bootargs} "			\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
+	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
+		"else run addip_sta;fi\0"				\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=ttyO0,${baudrate}\0"				\
+	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
+	"loadaddr=82000000\0"						\
+	"kernel_addr_r=82000000\0"					\
+	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
+	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr}\0"				\
+	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
+		"nand read ${kernel_addr_r} kernel\0"			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_self=if run net_self_load;then "				\
+		"run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
+		"else echo Images not loades;fi\0"			\
+	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0"			\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
+	"mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0"				\
+	"uboot_addr=0x80000\0"						\
+	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
+		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
+	"updatemlo=nandecc hw;nand erase 0 20000;"			\
+		"nand write ${loadaddr} 0 20000\0"			\
+	"upd=if run load;then echo Updating u-boot;if run update;"	\
+		"then echo U-Boot updated;"				\
+			"else echo Error updating u-boot !;"		\
+			"echo Board without bootloader !!;"		\
+		"fi;"							\
+		"else echo U-Boot not downloaded..exiting;fi\0"		\
+
+#endif /* __TAM3517_H */

From 92e30c07e02b84a3b63205fcb29ac57defd043f6 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Wed, 30 Nov 2011 23:56:53 +0000
Subject: [PATCH 03/34] ARM: omap3: add support to Technexion twister board

The twister board is a development board using
the TAM3517 SOM.

Support for NAND, 2 Ethernet (EMAC and SMC911),
USB (EHCI_OMAP).

Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tapani Utrianen <tapani@technexion.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Sandeep Paulraj <s-paulraj@ti.com>
---
 MAINTAINERS                        |   1 +
 board/technexion/twister/Makefile  |  38 +++
 board/technexion/twister/twister.c | 116 ++++++++
 board/technexion/twister/twister.h | 411 +++++++++++++++++++++++++++++
 boards.cfg                         |   1 +
 include/configs/twister.h          |  54 ++++
 6 files changed, 621 insertions(+)
 create mode 100644 board/technexion/twister/Makefile
 create mode 100644 board/technexion/twister/twister.c
 create mode 100644 board/technexion/twister/twister.h
 create mode 100644 include/configs/twister.h

diff --git a/MAINTAINERS b/MAINTAINERS
index a56ca10f3f..a856b4cebb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -572,6 +572,7 @@ Stefano Babic <sbabic@denx.de>
 	mx51evk		i.MX51
 	polaris		xscale/pxa
 	trizepsiv	xscale/pxa
+	twister		omap3
  	vision2		i.MX51
 
 Jason Liu <r64343@freescale.com>
diff --git a/board/technexion/twister/Makefile b/board/technexion/twister/Makefile
new file mode 100644
index 0000000000..38b7b14520
--- /dev/null
+++ b/board/technexion/twister/Makefile
@@ -0,0 +1,38 @@
+#
+# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+#
+# Based on ti/evm/Makefile
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c
new file mode 100644
index 0000000000..06fac7b583
--- /dev/null
+++ b/board/technexion/twister/twister.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include "twister.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timing definitions for Ethernet Controller */
+static const u32 gpmc_smc911[] = {
+	NET_GPMC_CONFIG1,
+	NET_GPMC_CONFIG2,
+	NET_GPMC_CONFIG3,
+	NET_GPMC_CONFIG4,
+	NET_GPMC_CONFIG5,
+	NET_GPMC_CONFIG6,
+};
+
+static const u32 gpmc_XR16L2751[] = {
+	XR16L2751_GPMC_CONFIG1,
+	XR16L2751_GPMC_CONFIG2,
+	XR16L2751_GPMC_CONFIG3,
+	XR16L2751_GPMC_CONFIG4,
+	XR16L2751_GPMC_CONFIG5,
+	XR16L2751_GPMC_CONFIG6,
+};
+
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	/* Chip select 1  and 3 are used for XR16L2751 UART controller */
+	enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[1],
+		XR16L2751_UART1_BASE, GPMC_SIZE_16M);
+
+	enable_gpmc_cs_config(gpmc_XR16L2751, &gpmc_cfg->cs[3],
+		XR16L2751_UART2_BASE, GPMC_SIZE_16M);
+
+	gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB_PHY1_RESET");
+	gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_TWISTER();
+}
+
+int board_eth_init(bd_t *bis)
+{
+	davinci_emac_initialize();
+
+	/* init cs for extern lan */
+	enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5],
+		CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
+	if (smc911x_initialize(0, CONFIG_SMC911X_BASE) <= 0)
+		printf("\nError initializing SMC911x controlleri\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_OMAP_HSMMC) && \
+	!defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0);
+}
+#endif
diff --git a/board/technexion/twister/twister.h b/board/technexion/twister/twister.h
new file mode 100644
index 0000000000..a2051c0044
--- /dev/null
+++ b/board/technexion/twister/twister.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2010 TechNexion Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _TAM3517_H_
+#define _TAM3517_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"TAM3517 TWISTER Board",
+	"NAND",
+};
+
+#define XR16L2751_GPMC_CONFIG1	0x00000000
+#define XR16L2751_GPMC_CONFIG2	0x001e1e01
+#define XR16L2751_GPMC_CONFIG3	0x00080300
+#define XR16L2751_GPMC_CONFIG4	0x1c091c09
+#define XR16L2751_GPMC_CONFIG5	0x04181f1f
+#define XR16L2751_GPMC_CONFIG6	0x00000FCF
+
+#define XR16L2751_UART1_BASE	0x21000000
+#define XR16L2751_UART2_BASE	0x23000000
+
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN	- Pull type selection is active
+ * M0	- Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_TWISTER() \
+	/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
+	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
+			 /*sdrc_strben_dly0*/\
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
+			/*sdrc_strben_dly1*/\
+	/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IEN | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTD | EN  | M2)) /*PWM9*/\
+	MUX_VAL(CP(GPMC_NCS3),		(IEN | PTU | EN | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),		(IEN | PTD | EN | M4)) \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS6),		(IDIS  | PTD | EN | M3)) /*PWM11*/ \
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS  | PTD | EN | M4)) /*GPIO_58*/ \
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M4)) \
+	/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
+	/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
+	/* MMC */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
+			/* CardDetect */\
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
+	\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTU | EN | M0)) \
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTU | DIS  | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTU | DIS  | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTU | DIS  | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | DIS  | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | DIS  | M0)) \
+	MUX_VAL(CP(MMC2_DAT4),		(IDIS  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT5),		(IDIS  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT6),		(IDIS  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT7),		(IDIS  | PTU | EN  | M4)) \
+	/* McBSP */\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN | PTD | EN | M4)) /*GPIO_116*/ \
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN | PTD | EN | M4)) \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN | PTD | EN | M4)) \
+	MUX_VAL(CP(MCBSP2_DX),		(IEN | PTD | EN | M4)) \
+	\
+	MUX_VAL(CP(MCBSP3_DX),		(IEN | PTU | EN | M4)) \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTU | EN | M4)) \
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTU | EN | M4)) \
+	\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN | PTD | DIS | M4)) /*GPIO_152*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+	MUX_VAL(CP(MCBSP4_FSX),		(IEN | PTD | DIS | M4)) /*GPIO_155*/\
+	/* UART */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),		(IEN | PTU | EN | M4)) \
+	MUX_VAL(CP(UART1_CTS),		(IEN | PTU | EN | M4)) \
+	\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS  | PTD | DIS | M4)) /*GPIO_163*/ \
+	MUX_VAL(CP(UART3_RTS_SD),	(IEN | PTD | DIS | M4)) /*GPIO_164*/\
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
+	/* I2C */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	/* McSPI */\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN | PTD | EN | M4)) /*GPIO_175*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN | PTD | EN | M4)) /*GPIO_176*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN | PTD | EN | M4)) \
+	\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M4)) \
+	/* CCDC */\
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	/* RMII */\
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
+	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
+	/* HECC */\
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
+	/* HSUSB */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
+	/* HDQ */\
+	MUX_VAL(CP(HDQ_SIO),		(IEN | PTD | EN | M4)) \
+	/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(SYS_NRESWARM),	(IDIS | PTU | DIS | M4)) \
+			/* - GPIO30 */\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+							 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
+	/* JTAG */\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),		(IDIS  | PTD | EN | M4)) /*GPIO_11*/ \
+	MUX_VAL(CP(JTAG_EMU1),		(IDIS  | PTD | EN | M4)) /*GPIO_31*/ \
+	/* ETK (ES2 onwards) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTD | DIS  | M3)) \
+					/* hsusb1_stp */ \
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M3)) \
+					/* hsusb1_clk */\
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTU | EN  | M3)) \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTU | EN  | M3)) \
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTU | EN  | M3)) \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTU | EN  | M3)) \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTU | EN  | M3)) \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTU | EN  | M3)) \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTU | EN  | M3)) \
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTU | EN  | M3)) \
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | EN  | M3)) \
+					/* hsusb1_dir */\
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN  | M3)) \
+					/* hsusb1_nxt */\
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(ETK_D11_ES2),	(IDIS | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M4)) \
+	/* Die to Die */\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+
+#endif
diff --git a/boards.cfg b/boards.cfg
index 66c27a4c23..406d64dfe0 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -210,6 +210,7 @@ omap3_evm_quick_mmc          arm         armv7       evm                 ti
 omap3_evm_quick_nand         arm         armv7       evm                 ti             omap3
 omap3_sdp3430                arm         armv7       sdp3430             ti             omap3
 devkit8000                   arm         armv7       devkit8000          timll          omap3
+twister                      arm         armv7       twister             technexion     omap3
 omap4_panda                  arm         armv7       panda               ti             omap4
 omap4_sdp4430                arm         armv7       sdp4430             ti             omap4
 omap5_evm                    arm         armv7       omap5_evm           ti		omap5
diff --git a/include/configs/twister.h b/include/configs/twister.h
new file mode 100644
index 0000000000..64a886d3a4
--- /dev/null
+++ b/include/configs/twister.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Copyright (C) 2009 TechNexion Ltd.
+ *
+ * Configuration for the Technexion twister board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tam3517-common.h"
+
+#define MACH_TYPE_TAM3517	2818
+#define CONFIG_MACH_TYPE	MACH_TYPE_TAM3517
+
+#define CONFIG_TAM3517_SW3_SETTINGS
+#define CONFIG_XR16L2751
+
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_HOSTNAME twister
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_PROMPT		"twister => "
+
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_16_BIT
+#define CONFIG_SMC911X_BASE		0x2C000000
+#define CONFIG_SMC911X_NO_EEPROM
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	CONFIG_TAM3517_SETTINGS \
+	"bootcmd=run nandboot\0"
+
+#endif /* __CONFIG_H */

From 7029a24f2cb50ce673eca07cf3982d8357d5a6ec Mon Sep 17 00:00:00 2001
From: Christian Riesch <christian.riesch@omicron.at>
Date: Fri, 9 Dec 2011 09:47:34 +0000
Subject: [PATCH 04/34] spl: display_options.o is required for SPI flash
 support in SPL

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
---
 lib/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/Makefile b/lib/Makefile
index 54708c261c..35ba7ffe47 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -50,6 +50,8 @@ COBJS-$(CONFIG_SHA1) += sha1.o
 COBJS-$(CONFIG_SHA256) += sha256.o
 COBJS-y	+= strmhz.o
 COBJS-$(CONFIG_RBTREE)	+= rbtree.o
+else
+COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += display_options.o
 endif
 
 COBJS-y += ctype.o

From 32b1127397a305ae0bc0a55ed9c4421fb570ef78 Mon Sep 17 00:00:00 2001
From: Christian Riesch <christian.riesch@omicron.at>
Date: Fri, 9 Dec 2011 09:47:35 +0000
Subject: [PATCH 05/34] sf: Add spi_boot() to allow booting from SPI flash in
 an SPL

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
---
 doc/README.SPL                 |  1 +
 drivers/mtd/spi/Makefile       |  4 +++
 drivers/mtd/spi/spi_spl_load.c | 58 ++++++++++++++++++++++++++++++++++
 include/spi_flash.h            |  3 ++
 4 files changed, 66 insertions(+)
 create mode 100644 drivers/mtd/spi/spi_spl_load.c

diff --git a/doc/README.SPL b/doc/README.SPL
index 89d24a7205..f01a8bd911 100644
--- a/doc/README.SPL
+++ b/doc/README.SPL
@@ -65,3 +65,4 @@ CONFIG_SPL_NAND_SUPPORT (drivers/mtd/nand/libnand.o)
 CONFIG_SPL_DMA_SUPPORT (drivers/dma/libdma.o)
 CONFIG_SPL_POST_MEM_SUPPORT (post/drivers/memory.o)
 CONFIG_SPL_NAND_LOAD (drivers/mtd/nand/nand_spl_load.o)
+CONFIG_SPL_SPI_LOAD (drivers/mtd/spi/spi_spl_load.o)
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 57112af66f..90f83924e2 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -25,6 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)libspi_flash.o
 
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_SPI_LOAD)	+= spi_spl_load.o
+endif
+
 COBJS-$(CONFIG_SPI_FLASH)	+= spi_flash.o
 COBJS-$(CONFIG_SPI_FLASH_ATMEL)	+= atmel.o
 COBJS-$(CONFIG_SPI_FLASH_EON)	+= eon.o
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
new file mode 100644
index 0000000000..1aa30aca7e
--- /dev/null
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * based on drivers/mtd/nand/nand_spl_load.c
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi_flash.h>
+
+/*
+ * The main entry for SPI booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from SPI into SDRAM and starts it from there.
+ */
+void spi_boot(void)
+{
+	struct spi_flash *flash;
+	void (*uboot)(void) __noreturn;
+
+	/*
+	 * Load U-Boot image from SPI flash into RAM
+	 */
+
+	flash = spi_flash_probe(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS,
+				CONFIG_SF_DEFAULT_SPEED, SPI_MODE_3);
+	if (!flash) {
+		puts("failed.\n");
+		hang();
+	}
+
+	spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+		       CONFIG_SYS_SPI_U_BOOT_SIZE,
+		       (void *) CONFIG_SYS_TEXT_BASE);
+
+	/*
+	 * Jump to U-Boot image
+	 */
+	uboot = (void *) CONFIG_SYS_TEXT_BASE;
+	(*uboot)();
+}
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 2671ab5539..9da90624f2 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -25,6 +25,7 @@
 
 #include <spi.h>
 #include <linux/types.h>
+#include <linux/compiler.h>
 
 struct spi_flash {
 	struct spi_slave *spi;
@@ -68,4 +69,6 @@ static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
 	return flash->erase(flash, offset, len);
 }
 
+void spi_boot(void) __noreturn;
+
 #endif /* _SPI_FLASH_H_ */

From 620fd27cfa4bbcbfc13ab88bd49055d5eb2ce82c Mon Sep 17 00:00:00 2001
From: Christian Riesch <christian.riesch@omicron.at>
Date: Fri, 9 Dec 2011 09:47:36 +0000
Subject: [PATCH 06/34] arm, davinci: Add SPL support for DA850 SoCs

This code adds an SPL for booting from SPI flash on DA850 SoCs.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Tom Rini <trini@ti.com>
---
 arch/arm/cpu/arm926ejs/davinci/Makefile |  3 ++-
 arch/arm/cpu/arm926ejs/davinci/spl.c    | 34 ++++++++++++++++++++++++-
 2 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile b/arch/arm/cpu/arm926ejs/davinci/Makefile
index 5ae89df5db..da7efac085 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -38,7 +38,8 @@ COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= lxt972.o dp83848.o et1011c.o ksz8873.o
 
 ifdef CONFIG_SPL_BUILD
 COBJS-y	+= spl.o
-COBJS-y	+= dm365_lowlevel.o
+COBJS-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
+COBJS-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
 endif
 
 SOBJS	= reset.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c
index d9b9398b7e..20f798e0df 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -26,6 +26,16 @@
 #include <nand.h>
 #include <asm/arch/dm365_lowlevel.h>
 #include <ns16550.h>
+#include <malloc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Define global data structure pointer to it*/
+static gd_t gdata __attribute__ ((section(".data")));
+static bd_t bdata __attribute__ ((section(".data")));
+
+#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
 
 void puts(const char *str)
 {
@@ -41,6 +51,8 @@ void putc(char c)
 	NS16550_putc((NS16550_t)(CONFIG_SYS_NS16550_COM1), c);
 }
 
+#endif /* CONFIG_SPL_LIBCOMMON_SUPPORT */
+
 inline void hang(void)
 {
 	puts("### ERROR ### Please RESET the board ###\n");
@@ -50,14 +62,34 @@ inline void hang(void)
 
 void board_init_f(ulong dummy)
 {
+#ifdef CONFIG_SOC_DM365
 	dm36x_lowlevel_init(0);
+#endif
+#ifdef CONFIG_SOC_DA8XX
+	arch_cpu_init();
+#endif
 	relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
 }
 
 void board_init_r(gd_t *id, ulong dummy)
 {
-
+#ifdef CONFIG_SOC_DM365
 	nand_init();
 	puts("Nand boot...\n");
 	nand_boot();
+#endif
+#ifdef CONFIG_SOC_DA8XX
+	mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
+			CONFIG_SYS_MALLOC_LEN);
+
+	gd = &gdata;
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();          /* serial communications setup */
+	gd->have_console = 1;
+
+	puts("SPI boot...\n");
+	spi_boot();
+#endif
 }

From 3d2c8e6c7f886d0155f95c9ac718653b1d6e7477 Mon Sep 17 00:00:00 2001
From: Christian Riesch <christian.riesch@omicron.at>
Date: Fri, 9 Dec 2011 09:47:37 +0000
Subject: [PATCH 07/34] arm, da850evm: Add an SPL for SPI boot

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
---
 board/davinci/da8xxevm/da850evm.c     |  4 +-
 board/davinci/da8xxevm/u-boot-spl.lds | 73 ++++++++++++++++++++++
 doc/README.davinci                    |  9 +++
 include/configs/da850evm.h            | 87 +++++++++++++++++++++++++++
 4 files changed, 172 insertions(+), 1 deletion(-)
 create mode 100644 board/davinci/da8xxevm/u-boot-spl.lds

diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 9c0eadea90..9bd3e7146c 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -108,7 +108,7 @@ static const struct pinmux_config gpio_pins[] = {
 #endif
 };
 
-static const struct pinmux_resource pinmuxes[] = {
+const struct pinmux_resource pinmuxes[] = {
 #ifdef CONFIG_DRIVER_TI_EMAC
 	PINMUX_ITEM(emac_pins_mdio),
 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
@@ -135,6 +135,8 @@ static const struct pinmux_resource pinmuxes[] = {
 	PINMUX_ITEM(gpio_pins),
 };
 
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
 static const struct lpsc_resource lpsc[] = {
 	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
 	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
diff --git a/board/davinci/da8xxevm/u-boot-spl.lds b/board/davinci/da8xxevm/u-boot-spl.lds
new file mode 100644
index 0000000000..6f6e065a9f
--- /dev/null
+++ b/board/davinci/da8xxevm/u-boot-spl.lds
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	__start = .;
+	  arch/arm/cpu/arm926ejs/start.o	(.text)
+	  *(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+	. = ALIGN(4);
+	.rel.dyn : {
+		__rel_dyn_start = .;
+		*(.rel*)
+		__rel_dyn_end = .;
+	} >.sram
+
+	.dynsym : {
+		__dynsym_start = .;
+		*(.dynsym)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} >.sram
+
+	__image_copy_end = .;
+	_end = .;
+}
diff --git a/doc/README.davinci b/doc/README.davinci
index 5f1bdc836c..aa7c85011a 100644
--- a/doc/README.davinci
+++ b/doc/README.davinci
@@ -95,6 +95,15 @@ into the RAM.
 The programmers and UBL are always released as part of any standard TI
 software release associated with an SOC.
 
+Alternative boot method (DA850 EVM only):
+For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL)
+is provided to load U-Boot directly from SPI flash. In this case, the
+SPL does the low level initialization that is otherwise done by the SPL.
+To build U-Boot with this SPL, do
+make da850evm_config
+make u-boot.ais
+and program the resulting u-boot.ais file to the SPI flash of the DA850 EVM.
+
 Environment Variables
 =====================
 
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 2e2aa19a45..b30696af9f 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -65,6 +65,75 @@
 #define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */
 #define CONFIG_STACKSIZE	(256*1024) /* regular stack */
 
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
+	DAVINCI_SYSCFG_SUSPSRC_I2C)
+
+/*
+ * PLL configuration
+ */
+#define CONFIG_SYS_DV_CLKMODE          0
+#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
+#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
+#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
+#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005
+
+#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
+#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
+#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
+#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002
+
+#define CONFIG_SYS_DA850_PLL0_PLLM     24
+#define CONFIG_SYS_DA850_PLL1_PLLM     21
+
+/*
+ * DDR2 memory configuration
+ */
+#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+					DV_DDR_PHY_EXT_STRBEN | \
+					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
+	(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
+	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
+	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
+	(0x2 << DV_DDR_SDCR_IBANK_SHIFT) |	\
+	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
+
+/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
+#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
+	(14 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
+	(2 << DV_DDR_SDTMR1_RP_SHIFT) |		\
+	(2 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
+	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
+	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
+	(8 << DV_DDR_SDTMR1_RC_SHIFT) |		\
+	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
+	(0 << DV_DDR_SDTMR1_WTR_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
+	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_XP_SHIFT) |		\
+	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
+	(17 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
+	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
+	(0 << DV_DDR_SDTMR2_CKE_SHIFT))
+
+#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000494
+#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+
 /*
  * Serial Driver info
  */
@@ -76,6 +145,7 @@
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2
 
 #define CONFIG_SPI
 #define CONFIG_SPI_FLASH
@@ -242,6 +312,23 @@
 #undef CONFIG_CMD_ENV
 #endif
 
+/* defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LDSCRIPT	"$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_STACK	0x8001ff00
+#define CONFIG_SPL_TEXT_BASE	0x80000000
+#define CONFIG_SPL_MAX_SIZE	32768
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x30000
+
 /* additions for new relocation code, must added to all boards */
 #define CONFIG_SYS_SDRAM_BASE		0xc0000000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \

From d1be8f922eb3ca51abc200e42af0498e81d5fa23 Mon Sep 17 00:00:00 2001
From: Christian Riesch <christian.riesch@omicron.at>
Date: Fri, 9 Dec 2011 09:47:38 +0000
Subject: [PATCH 08/34] mkimage: Fix variable length header support

Support for variable length images like AIS image was introduced
in commit f0662105b674a3874227316abf8536bebc9b5995. A parameter
"-s" was also introduced to prohibit copying of the image file
automatically in the main program. However, this parameter
was implemented incorrectly and the image file was copied
nevertheless.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
---
 tools/mkimage.c | 97 +++++++++++++++++++++++++------------------------
 1 file changed, 49 insertions(+), 48 deletions(-)

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 36e28ec923..eeb1b10668 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -383,65 +383,66 @@ NXTARG:		;
 		exit (EXIT_FAILURE);
 	}
 
-	if (!params.skipcpy &&
-		(params.type == IH_TYPE_MULTI ||
-			params.type == IH_TYPE_SCRIPT)) {
-		char *file = params.datafile;
-		uint32_t size;
+	if (!params.skipcpy) {
+		if (params.type == IH_TYPE_MULTI ||
+		    params.type == IH_TYPE_SCRIPT) {
+			char *file = params.datafile;
+			uint32_t size;
 
-		for (;;) {
-			char *sep = NULL;
+			for (;;) {
+				char *sep = NULL;
 
-			if (file) {
-				if ((sep = strchr(file, ':')) != NULL) {
-					*sep = '\0';
+				if (file) {
+					if ((sep = strchr(file, ':')) != NULL) {
+						*sep = '\0';
+					}
+
+					if (stat (file, &sbuf) < 0) {
+						fprintf (stderr, "%s: Can't stat %s: %s\n",
+							 params.cmdname, file, strerror(errno));
+						exit (EXIT_FAILURE);
+					}
+					size = cpu_to_uimage (sbuf.st_size);
+				} else {
+					size = 0;
 				}
 
-				if (stat (file, &sbuf) < 0) {
-					fprintf (stderr, "%s: Can't stat %s: %s\n",
-						params.cmdname, file, strerror(errno));
+				if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) {
+					fprintf (stderr, "%s: Write error on %s: %s\n",
+						 params.cmdname, params.imagefile,
+						 strerror(errno));
 					exit (EXIT_FAILURE);
 				}
-				size = cpu_to_uimage (sbuf.st_size);
-			} else {
-				size = 0;
+
+				if (!file) {
+					break;
+				}
+
+				if (sep) {
+					*sep = ':';
+					file = sep + 1;
+				} else {
+					file = NULL;
+				}
 			}
 
-			if (write(ifd, (char *)&size, sizeof(size)) != sizeof(size)) {
-				fprintf (stderr, "%s: Write error on %s: %s\n",
-					params.cmdname, params.imagefile,
-					strerror(errno));
-				exit (EXIT_FAILURE);
-			}
+			file = params.datafile;
 
-			if (!file) {
-				break;
-			}
-
-			if (sep) {
-				*sep = ':';
-				file = sep + 1;
-			} else {
-				file = NULL;
+			for (;;) {
+				char *sep = strchr(file, ':');
+				if (sep) {
+					*sep = '\0';
+					copy_file (ifd, file, 1);
+					*sep++ = ':';
+					file = sep;
+				} else {
+					copy_file (ifd, file, 0);
+					break;
+				}
 			}
+		} else {
+			copy_file (ifd, params.datafile, 0);
 		}
-
-		file = params.datafile;
-
-		for (;;) {
-			char *sep = strchr(file, ':');
-			if (sep) {
-				*sep = '\0';
-				copy_file (ifd, file, 1);
-				*sep++ = ':';
-				file = sep;
-			} else {
-				copy_file (ifd, file, 0);
-				break;
-			}
-		}
-	} else {
-		copy_file (ifd, params.datafile, 0);
 	}
 
 	/* We're a bit of paranoid */

From d36d8859846598f80c980f9bc916a342a0db4095 Mon Sep 17 00:00:00 2001
From: Christian Riesch <christian.riesch@omicron.at>
Date: Fri, 9 Dec 2011 09:47:39 +0000
Subject: [PATCH 09/34] arm, davinci: Add support for generating AIS images to
 the Makefile

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Mike Frysinger <vapier@gentoo.org>
---
 .gitignore |  1 +
 Makefile   | 13 +++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/.gitignore b/.gitignore
index ff4bae0081..e4e95e2d34 100644
--- a/.gitignore
+++ b/.gitignore
@@ -35,6 +35,7 @@
 /u-boot.dis
 /u-boot.lds
 /u-boot.ubl
+/u-boot.ais
 /u-boot.dtb
 /u-boot.sb
 
diff --git a/Makefile b/Makefile
index 0438f1ef8f..7e9491d3db 100644
--- a/Makefile
+++ b/Makefile
@@ -429,6 +429,18 @@ $(obj)u-boot.ubl:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
 		rm $(obj)u-boot-ubl.bin
 		rm $(obj)spl/u-boot-spl-pad.bin
 
+$(obj)u-boot.ais:       $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+		$(obj)tools/mkimage -s -n /dev/null -T aisimage \
+			-e $(CONFIG_SPL_TEXT_BASE) \
+			-d $(obj)spl/u-boot-spl.bin \
+			$(obj)spl/u-boot-spl.ais
+		$(OBJCOPY) ${OBJCFLAGS} -I binary \
+			--pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
+			$(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
+		cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.bin > \
+			$(obj)u-boot.ais
+		rm $(obj)spl/u-boot-spl{,-pad}.ais
+
 $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
 		elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
 			-o $(obj)u-boot.sb
@@ -762,6 +774,7 @@ clobber:	tidy
 	@rm -f $(obj)u-boot.kwb
 	@rm -f $(obj)u-boot.imx
 	@rm -f $(obj)u-boot.ubl
+	@rm -f $(obj)u-boot.ais
 	@rm -f $(obj)u-boot.dtb
 	@rm -f $(obj)u-boot.sb
 	@rm -f $(obj)tools/inca-swap-bytes

From 13b178edc242cb7b61b6f4264456f7061fa3cf5b Mon Sep 17 00:00:00 2001
From: Thomas Weber <weber@corscience.de>
Date: Tue, 13 Dec 2011 05:54:17 +0000
Subject: [PATCH 10/34] Devkit8000: Switch over to enable_gpmc_cs_config

Use enable_gpmc_cs_config instead of local writing
timing configuration for GPMC.

Signed-off-by: Thomas Weber <weber@corscience.de>
---
 board/timll/devkit8000/devkit8000.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c
index b06aab6176..10f189eed4 100644
--- a/board/timll/devkit8000/devkit8000.c
+++ b/board/timll/devkit8000/devkit8000.c
@@ -48,6 +48,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static u32 gpmc_net_config[GPMC_MAX_REG] = {
+	NET_GPMC_CONFIG1,
+	NET_GPMC_CONFIG2,
+	NET_GPMC_CONFIG3,
+	NET_GPMC_CONFIG4,
+	NET_GPMC_CONFIG5,
+	NET_GPMC_CONFIG6,
+	0
+};
+
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -82,13 +92,8 @@ int misc_init_r(void)
 
 #ifdef CONFIG_DRIVER_DM9000
 	/* Configure GPMC registers for DM9000 */
-	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[6].config1);
-	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[6].config2);
-	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[6].config3);
-	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[6].config4);
-	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[6].config5);
-	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[6].config6);
-	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[6].config7);
+	enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
+			CONFIG_DM9000_BASE, GPMC_SIZE_16M);
 
 	/* Use OMAP DIE_ID as MAC address */
 	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {

From 8f7431400a67c4844240f875ebd7e4bcb3332633 Mon Sep 17 00:00:00 2001
From: Christian Riesch <christian.riesch@omicron.at>
Date: Wed, 14 Dec 2011 09:54:36 +0100
Subject: [PATCH 11/34] arm, davinci: Fix build warnings for cam_enc_4xx

This patch fixes a build warning for the cam_enc_4xx board introduced by
commit d6ec0c0dfc70447cf615ae80a952da81f73f16b4:

spl.c:35:13: warning: 'gdata' defined but not used
spl.c:36:13: warning: 'bdata' defined but not used

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
---
 arch/arm/cpu/arm926ejs/davinci/spl.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c
index 20f798e0df..f475f9ba75 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -29,13 +29,14 @@
 #include <malloc.h>
 #include <spi_flash.h>
 
-DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 
+DECLARE_GLOBAL_DATA_PTR;
 /* Define global data structure pointer to it*/
 static gd_t gdata __attribute__ ((section(".data")));
 static bd_t bdata __attribute__ ((section(".data")));
 
-#ifndef CONFIG_SPL_LIBCOMMON_SUPPORT
+#else
 
 void puts(const char *str)
 {

From 6b5763e5886c0c5aaef36eab7d660fc885b60c20 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 5 Nov 2011 04:46:44 +0000
Subject: [PATCH 12/34] tegra2: Tidy UART selection

UART selection is done with a lot of #ifdefs. This cleans things up
a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/nvidia/common/board.c | 57 ++++++++++++++++++++++---------------
 1 file changed, 34 insertions(+), 23 deletions(-)

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index c806a6b3cb..5313c76990 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -35,6 +35,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+	/* UARTs which we can enable */
+	UARTA	= 1 << 0,
+	UARTD	= 1 << 3,
+};
+
 const struct tegra2_sysinfo sysinfo = {
 	CONFIG_TEGRA2_BOARD_STRING
 };
@@ -64,36 +70,32 @@ static void enable_uart(enum periph_id pid)
 
 /*
  * Routine: clock_init_uart
- * Description: init the PLL and clock for the UART(s)
+ * Description: init clock for the UART(s)
  */
-static void clock_init_uart(void)
+static void clock_init_uart(int uart_ids)
 {
-#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
-	enable_uart(PERIPH_ID_UART1);
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
-#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
-	enable_uart(PERIPH_ID_UART4);
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+	if (uart_ids & UARTA)
+		enable_uart(PERIPH_ID_UART1);
+	if (uart_ids & UARTD)
+		enable_uart(PERIPH_ID_UART4);
 }
 
 /*
  * Routine: pin_mux_uart
  * Description: setup the pin muxes/tristate values for the UART(s)
  */
-static void pin_mux_uart(void)
+static void pin_mux_uart(int uart_ids)
 {
-#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
-	pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
-	pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
-
-	pinmux_tristate_disable(PINGRP_IRRX);
-	pinmux_tristate_disable(PINGRP_IRTX);
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
-#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
-	pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
-
-	pinmux_tristate_disable(PINGRP_GMC);
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+	if (uart_ids & UARTA) {
+		pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
+		pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
+		pinmux_tristate_disable(PINGRP_IRRX);
+		pinmux_tristate_disable(PINGRP_IRTX);
+	}
+	if (uart_ids & UARTD) {
+		pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
+		pinmux_tristate_disable(PINGRP_GMC);
+	}
 }
 
 /*
@@ -114,6 +116,15 @@ int board_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
+	int uart_ids = 0;	/* bit mask of which UART ids to enable */
+
+#ifdef CONFIG_TEGRA2_ENABLE_UARTA
+	uart_ids |= UARTA;
+#endif
+#ifdef CONFIG_TEGRA2_ENABLE_UARTD
+	uart_ids |= UARTD;
+#endif
+
 	/* We didn't do this init in start.S, so do it now */
 	cpu_init_cp15();
 
@@ -121,10 +132,10 @@ int board_early_init_f(void)
 	clock_early_init();
 
 	/* Initialize UART clocks */
-	clock_init_uart();
+	clock_init_uart(uart_ids);
 
 	/* Initialize periph pinmuxes */
-	pin_mux_uart();
+	pin_mux_uart(uart_ids);
 
 	/* Initialize periph GPIOs */
 	gpio_config_uart();

From 1be0d75973eff5a7655f8eb5241661767b97ffd3 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 5 Nov 2011 04:46:45 +0000
Subject: [PATCH 13/34] tegra2: Add UARTB support

UARTB is used on some boards, so support it here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/nvidia/common/board.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 5313c76990..4c29167316 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
 enum {
 	/* UARTs which we can enable */
 	UARTA	= 1 << 0,
+	UARTB	= 1 << 1,
 	UARTD	= 1 << 3,
 };
 
@@ -76,6 +77,8 @@ static void clock_init_uart(int uart_ids)
 {
 	if (uart_ids & UARTA)
 		enable_uart(PERIPH_ID_UART1);
+	if (uart_ids & UARTB)
+		enable_uart(PERIPH_ID_UART2);
 	if (uart_ids & UARTD)
 		enable_uart(PERIPH_ID_UART4);
 }
@@ -92,6 +95,10 @@ static void pin_mux_uart(int uart_ids)
 		pinmux_tristate_disable(PINGRP_IRRX);
 		pinmux_tristate_disable(PINGRP_IRTX);
 	}
+	if (uart_ids & UARTB) {
+		pinmux_set_func(PINGRP_UAD, PMUX_FUNC_IRDA);
+		pinmux_tristate_disable(PINGRP_UAD);
+	}
 	if (uart_ids & UARTD) {
 		pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
 		pinmux_tristate_disable(PINGRP_GMC);
@@ -121,6 +128,9 @@ int board_early_init_f(void)
 #ifdef CONFIG_TEGRA2_ENABLE_UARTA
 	uart_ids |= UARTA;
 #endif
+#ifdef CONFIG_TEGRA2_ENABLE_UARTB
+	uart_ids |= UARTB;
+#endif
 #ifdef CONFIG_TEGRA2_ENABLE_UARTD
 	uart_ids |= UARTD;
 #endif

From 9112ef8d89e3e496ba6f73276f17dd5c2b93877f Mon Sep 17 00:00:00 2001
From: Tom Warren <twarren.nvidia@gmail.com>
Date: Sat, 5 Nov 2011 09:48:11 +0000
Subject: [PATCH 14/34] tegra2: spi: Add SPI driver for Tegra2 SOC

This driver supports SPI on Tegra2, running at 48MHz.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/arm/include/asm/arch-tegra2/tegra2.h     |   1 +
 arch/arm/include/asm/arch-tegra2/tegra2_spi.h |  76 +++++
 board/nvidia/common/board.c                   |   4 +
 drivers/spi/Makefile                          |   1 +
 drivers/spi/tegra2_spi.c                      | 265 ++++++++++++++++++
 5 files changed, 347 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2_spi.h
 create mode 100644 drivers/spi/tegra2_spi.c

diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
index 742a75a0da..8941443ad8 100644
--- a/arch/arm/include/asm/arch-tegra2/tegra2.h
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -38,6 +38,7 @@
 #define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
 #define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
 #define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
+#define TEGRA2_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
 #define NV_PA_PMC_BASE		0x7000E400
 #define NV_PA_CSITE_BASE	0x70040000
 
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2_spi.h b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
new file mode 100644
index 0000000000..ceec4287a3
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/tegra2_spi.h
@@ -0,0 +1,76 @@
+/*
+ * NVIDIA Tegra2 SPI-FLASH controller
+ *
+ * Copyright 2010-2011 NVIDIA Corporation
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_SPI_H_
+#define _TEGRA2_SPI_H_
+
+#include <asm/types.h>
+
+struct spi_tegra {
+	u32 command;	/* SPI_COMMAND_0 register  */
+	u32 status;	/* SPI_STATUS_0 register */
+	u32 rx_cmp;	/* SPI_RX_CMP_0 register  */
+	u32 dma_ctl;	/* SPI_DMA_CTL_0 register */
+	u32 tx_fifo;	/* SPI_TX_FIFO_0 register */
+	u32 rsvd[3];	/* offsets 0x14 to 0x1F reserved */
+	u32 rx_fifo;	/* SPI_RX_FIFO_0 register */
+};
+
+#define SPI_CMD_GO			(1 << 30)
+#define SPI_CMD_ACTIVE_SCLK_SHIFT	26
+#define SPI_CMD_ACTIVE_SCLK_MASK	(3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
+#define SPI_CMD_CK_SDA			(1 << 21)
+#define SPI_CMD_ACTIVE_SDA_SHIFT	18
+#define SPI_CMD_ACTIVE_SDA_MASK		(3 << SPI_CMD_ACTIVE_SDA_SHIFT)
+#define SPI_CMD_CS_POL			(1 << 16)
+#define SPI_CMD_TXEN			(1 << 15)
+#define SPI_CMD_RXEN			(1 << 14)
+#define SPI_CMD_CS_VAL			(1 << 13)
+#define SPI_CMD_CS_SOFT			(1 << 12)
+#define SPI_CMD_CS_DELAY		(1 << 9)
+#define SPI_CMD_CS3_EN			(1 << 8)
+#define SPI_CMD_CS2_EN			(1 << 7)
+#define SPI_CMD_CS1_EN			(1 << 6)
+#define SPI_CMD_CS0_EN			(1 << 5)
+#define SPI_CMD_BIT_LENGTH		(1 << 4)
+#define SPI_CMD_BIT_LENGTH_MASK		0x0000001F
+
+#define SPI_STAT_BSY			(1 << 31)
+#define SPI_STAT_RDY			(1 << 30)
+#define SPI_STAT_RXF_FLUSH		(1 << 29)
+#define SPI_STAT_TXF_FLUSH		(1 << 28)
+#define SPI_STAT_RXF_UNR		(1 << 27)
+#define SPI_STAT_TXF_OVF		(1 << 26)
+#define SPI_STAT_RXF_EMPTY		(1 << 25)
+#define SPI_STAT_RXF_FULL		(1 << 24)
+#define SPI_STAT_TXF_EMPTY		(1 << 23)
+#define SPI_STAT_TXF_FULL		(1 << 22)
+#define SPI_STAT_SEL_TXRX_N		(1 << 16)
+#define SPI_STAT_CUR_BLKCNT		(1 << 15)
+
+#define SPI_TIMEOUT		1000
+#define TEGRA2_SPI_MAX_FREQ	52000000
+
+
+#endif	/* _TEGRA2_SPI_H_ */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 4c29167316..6a1312c5aa 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -31,6 +31,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/uart.h>
+#include <spi.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -114,6 +115,9 @@ int board_init(void)
 	clock_init();
 	clock_verify();
 
+#ifdef CONFIG_TEGRA2_SPI
+	spi_init();
+#endif
 	/* boot param addr */
 	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 6f389f0934..c967d87834 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
 COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
 COBJS-$(CONFIG_SH_SPI) += sh_spi.o
 COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
+COBJS-$(CONFIG_TEGRA2_SPI) += tegra2_spi.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c
new file mode 100644
index 0000000000..fdcad093cf
--- /dev/null
+++ b/drivers/spi/tegra2_spi.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2010-2011 NVIDIA Corporation
+ * With help from the mpc8xxx SPI driver
+ * With more help from omap3_spi SPI driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/tegra2_spi.h>
+
+struct tegra_spi_slave {
+	struct spi_slave slave;
+	struct spi_tegra *regs;
+	unsigned int freq;
+	unsigned int mode;
+};
+
+static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
+{
+	return container_of(slave, struct tegra_spi_slave, slave);
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	/* Tegra2 SPI-Flash - only 1 device ('bus/cs') */
+	if (bus != 0 || cs != 0)
+		return 0;
+	else
+		return 1;
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+		unsigned int max_hz, unsigned int mode)
+{
+	struct tegra_spi_slave *spi;
+
+	if (!spi_cs_is_valid(bus, cs)) {
+		printf("SPI error: unsupported bus %d / chip select %d\n",
+		       bus, cs);
+		return NULL;
+	}
+
+	if (max_hz > TEGRA2_SPI_MAX_FREQ) {
+		printf("SPI error: unsupported frequency %d Hz. Max frequency"
+			" is %d Hz\n", max_hz, TEGRA2_SPI_MAX_FREQ);
+		return NULL;
+	}
+
+	spi = malloc(sizeof(struct tegra_spi_slave));
+	if (!spi) {
+		printf("SPI error: malloc of SPI structure failed\n");
+		return NULL;
+	}
+	spi->slave.bus = bus;
+	spi->slave.cs = cs;
+	spi->freq = max_hz;
+	spi->regs = (struct spi_tegra *)TEGRA2_SPI_BASE;
+	spi->mode = mode;
+
+	return &spi->slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+	free(spi);
+}
+
+void spi_init(void)
+{
+	/* do nothing */
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_tegra *regs = spi->regs;
+	u32 reg;
+
+	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
+	clock_start_periph_pll(PERIPH_ID_SPI1, CLOCK_ID_PERIPH, spi->freq);
+
+	/* Clear stale status here */
+	reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
+		SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
+	writel(reg, &regs->status);
+	debug("spi_init: STATUS = %08x\n", readl(&regs->status));
+
+	/*
+	 * Use sw-controlled CS, so we can clock in data after ReadID, etc.
+	 */
+	reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
+	if (spi->mode & 2)
+		reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
+	clrsetbits_le32(&regs->command, SPI_CMD_ACTIVE_SCLK_MASK |
+		SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
+	debug("spi_init: COMMAND = %08x\n", readl(&regs->command));
+
+	/*
+	 * SPI pins on Tegra2 are muxed - change pinmux later due to UART
+	 * issue.
+	 */
+	pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
+	pinmux_tristate_disable(PINGRP_LSPI);
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+	/*
+	 * We can't release UART_DISABLE and set pinmux to UART4 here since
+	 * some code (e,g, spi_flash_probe) uses printf() while the SPI
+	 * bus is held. That is arguably bad, but it has the advantage of
+	 * already being in the source tree.
+	 */
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+	/* CS is negated on Tegra, so drive a 1 to get a 0 */
+	setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+
+	/* CS is negated on Tegra, so drive a 0 to get a 1 */
+	clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
+		const void *data_out, void *data_in, unsigned long flags)
+{
+	struct tegra_spi_slave *spi = to_tegra_spi(slave);
+	struct spi_tegra *regs = spi->regs;
+	u32 reg, tmpdout, tmpdin = 0;
+	const u8 *dout = data_out;
+	u8 *din = data_in;
+	int num_bytes;
+	int ret;
+
+	debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
+	      slave->bus, slave->cs, *(u8 *)dout, *(u8 *)din, bitlen);
+	if (bitlen % 8)
+		return -1;
+	num_bytes = bitlen / 8;
+
+	ret = 0;
+
+	reg = readl(&regs->status);
+	writel(reg, &regs->status);	/* Clear all SPI events via R/W */
+	debug("spi_xfer entry: STATUS = %08x\n", reg);
+
+	reg = readl(&regs->command);
+	reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
+	writel(reg, &regs->command);
+	debug("spi_xfer: COMMAND = %08x\n", readl(&regs->command));
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(slave);
+
+	/* handle data in 32-bit chunks */
+	while (num_bytes > 0) {
+		int bytes;
+		int is_read = 0;
+		int tm, i;
+
+		tmpdout = 0;
+		bytes = (num_bytes > 4) ?  4 : num_bytes;
+
+		if (dout != NULL) {
+			for (i = 0; i < bytes; ++i)
+				tmpdout = (tmpdout << 8) | dout[i];
+		}
+
+		num_bytes -= bytes;
+		if (dout)
+			dout += bytes;
+
+		clrsetbits_le32(&regs->command, SPI_CMD_BIT_LENGTH_MASK,
+				bytes * 8 - 1);
+		writel(tmpdout, &regs->tx_fifo);
+		setbits_le32(&regs->command, SPI_CMD_GO);
+
+		/*
+		 * Wait for SPI transmit FIFO to empty, or to time out.
+		 * The RX FIFO status will be read and cleared last
+		 */
+		for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
+			u32 status;
+
+			status = readl(&regs->status);
+
+			/* We can exit when we've had both RX and TX activity */
+			if (is_read && (status & SPI_STAT_TXF_EMPTY))
+				break;
+
+			if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
+					SPI_STAT_RDY)
+				tm++;
+
+			else if (!(status & SPI_STAT_RXF_EMPTY)) {
+				tmpdin = readl(&regs->rx_fifo);
+				is_read = 1;
+
+				/* swap bytes read in */
+				if (din != NULL) {
+					for (i = bytes - 1; i >= 0; --i) {
+						din[i] = tmpdin & 0xff;
+						tmpdin >>= 8;
+					}
+					din += bytes;
+				}
+			}
+		}
+
+		if (tm >= SPI_TIMEOUT)
+			ret = tm;
+
+		/* clear ACK RDY, etc. bits */
+		writel(readl(&regs->status), &regs->status);
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(slave);
+
+	debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
+		tmpdin, readl(&regs->status));
+
+	if (ret) {
+		printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
+		return -1;
+	}
+
+	return 0;
+}

From bf80088ac0f0a753f986d663dbf24327680e4533 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 5 Nov 2011 04:46:47 +0000
Subject: [PATCH 15/34] tegra2: config: Enable SPI flash on Seaboard

The Seaboard includes a Winbond 4MB flash part.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/seaboard.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 7d2914472a..7e8c8cc51e 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -37,11 +37,22 @@
 #define CONFIG_TEGRA2_ENABLE_UARTD
 #define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
 
+/* On Seaboard: GPIO_PI3 = Port I = 8, bit = 3 */
+#define CONFIG_UART_DISABLE_GPIO	GPIO_PI3
+
 #define CONFIG_MACH_TYPE		MACH_TYPE_SEABOARD
 #define CONFIG_SYS_BOARD_ODMDATA	0x300d8011 /* lp1, 1GB */
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
+/* SPI */
+#define CONFIG_TEGRA2_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC

From 9dd79fdb6cfed5c62aa5adeaa7d5f758114e105c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 5 Nov 2011 04:46:48 +0000
Subject: [PATCH 16/34] tegra2: Enable SPI environment on Seaboard

This uses the SPI flash on Seaboard to store an 8KB environment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/harmony.h       | 3 +++
 include/configs/seaboard.h      | 9 +++++++++
 include/configs/tegra2-common.h | 3 +--
 3 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/include/configs/harmony.h b/include/configs/harmony.h
index 89e4911244..ce0ae9fe1f 100644
--- a/include/configs/harmony.h
+++ b/include/configs/harmony.h
@@ -58,4 +58,7 @@
 #define CONFIG_EFI_PARTITION
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
+
+/* Environment not stored */
+#define CONFIG_ENV_IS_NOWHERE
 #endif /* __CONFIG_H */
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
index 7e8c8cc51e..261f9521ad 100644
--- a/include/configs/seaboard.h
+++ b/include/configs/seaboard.h
@@ -52,6 +52,7 @@
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE		(4 << 20)
 
 /* SD/MMC */
 #define CONFIG_MMC
@@ -63,4 +64,12 @@
 #define CONFIG_EFI_PARTITION
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
+
+/* Environment in SPI */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_MAX_HZ		48000000
+#define CONFIG_ENV_SPI_MODE		SPI_MODE_0
+
+#define CONFIG_ENV_SECT_SIZE    CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET       (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
 #endif /* __CONFIG_H */
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index e233b1c83d..ffea4013eb 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -51,8 +51,7 @@
 #define CONFIG_OF_LIBFDT		/* enable passing of devicetree */
 
 /* Environment */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE			0x20000	/* Total Size Environment */
+#define CONFIG_ENV_SIZE			0x2000	/* Total Size Environment */
 
 /*
  * Size of malloc() pool

From cb93481268904df3447fbe8b0ccb2862967efc26 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 5 Nov 2011 04:46:49 +0000
Subject: [PATCH 17/34] tegra2: Implement SPI / UART GPIO switch

The Tegra2 Seaboard has the unfortunate feature that SPI and the console
UART are multiplexed on the same pins. We need to switch between one
and the other during SPI and console activity.

This new file implements a switch and keeps track of which peripheral
owns the pins. It also flips over the controlling GPIO as needed

Since we are adding a second file to board/nvidia/common, we create
a proper Makefile there and remove the direct board.o include from
board/nvidia/seaboard/Makefile

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 .../include/asm/arch-tegra2/uart-spi-switch.h |  46 ++++++
 board/nvidia/common/Makefile                  |  47 ++++++
 board/nvidia/common/uart-spi-switch.c         | 138 ++++++++++++++++++
 board/nvidia/seaboard/Makefile                |   1 -
 4 files changed, 231 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/arch-tegra2/uart-spi-switch.h
 create mode 100644 board/nvidia/common/Makefile
 create mode 100644 board/nvidia/common/uart-spi-switch.c

diff --git a/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h
new file mode 100644
index 0000000000..e4503b15b0
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/uart-spi-switch.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _UART_SPI_SWITCH_H
+#define _UART_SPI_SWITCH_H
+
+#if defined(CONFIG_SPI_UART_SWITCH)
+/*
+ * Signal that we are about to use the UART. This unfortunate hack is
+ * required by Seaboard, which cannot use its console and SPI at the same
+ * time! If the board file provides this, the board config will declare it.
+ * Let this be a lesson for others.
+ */
+void pinmux_select_uart(NS16550_t regs);
+
+/*
+ * Signal that we are about the use the SPI bus.
+ */
+void pinmux_select_spi(void);
+
+#else /* not CONFIG_SPI_UART_SWITCH */
+
+static inline void pinmux_select_uart(NS16550_t regs) {}
+static inline void pinmux_select_spi(void) {}
+
+#endif
+
+#endif
diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile
new file mode 100644
index 0000000000..3e748fdd20
--- /dev/null
+++ b/board/nvidia/common/Makefile
@@ -0,0 +1,47 @@
+# Copyright (c) 2011 The Chromium OS Authors.
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).o
+
+COBJS-y += board.o
+COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-switch.o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+all:	$(LIB)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c
new file mode 100644
index 0000000000..23aa0b9d19
--- /dev/null
+++ b/board/nvidia/common/uart-spi-switch.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/gpio.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/uart-spi-switch.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/tegra2_spi.h>
+
+
+/* position of the UART/SPI select switch */
+enum spi_uart_switch {
+	SWITCH_UNKNOWN,
+	SWITCH_SPI,
+	SWITCH_UART,
+	SWITCH_BOTH
+};
+
+/* Information about the spi/uart switch */
+struct spi_uart {
+	int gpio;                       /* GPIO to control switch */
+	NS16550_t regs;                 /* Address of UART affected */
+	u32 port;                       /* Port number of UART affected */
+};
+
+static struct spi_uart local;
+static enum spi_uart_switch switch_pos; /* Current switch position */
+
+
+static void get_config(struct spi_uart *config)
+{
+#if defined CONFIG_SPI_CORRUPTS_UART
+	config->gpio = CONFIG_UART_DISABLE_GPIO;
+	config->regs = (NS16550_t)CONFIG_SPI_CORRUPTS_UART;
+	config->port = CONFIG_SPI_CORRUPTS_UART_NR;
+#else
+	config->gpio = -1;
+#endif
+}
+
+/*
+ * Init the UART / SPI switch. This can be called before relocation so we must
+ * not access BSS.
+ */
+void gpio_early_init_uart(void)
+{
+	struct spi_uart config;
+
+	get_config(&config);
+	if (config.gpio != -1) {
+		/* Cannot provide a label prior to relocation */
+		gpio_request(config.gpio, NULL);
+		gpio_direction_output(config.gpio, 0);
+	}
+}
+
+/*
+ * Configure the UART / SPI switch.
+ */
+void gpio_config_uart(void)
+{
+	get_config(&local);
+	if (local.gpio != -1) {
+		gpio_direction_output(local.gpio, 0);
+		switch_pos = SWITCH_UART;
+	} else {
+		/*
+		 * If we're here we don't have a SPI switch; go ahead and
+		 * enable the SPI now.  We didn't in spi_init() so we wouldn't
+		 * kill the UART.
+		 */
+		pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
+		switch_pos = SWITCH_BOTH;
+	}
+}
+
+static void spi_uart_switch(struct spi_uart *config,
+			      enum spi_uart_switch new_pos)
+{
+	if (switch_pos == SWITCH_BOTH || new_pos == switch_pos)
+		return;
+
+	/* if the UART was selected, allow it to drain */
+	if (switch_pos == SWITCH_UART)
+		NS16550_drain(config->regs, config->port);
+
+	/* We need to dynamically change the pinmux, shared w/UART RXD/CTS */
+	pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ?
+				PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD);
+
+	/*
+	* On Seaboard, MOSI/MISO are shared w/UART.
+	* Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity.
+	* Enable UART later (cs_deactivate) so we can use it for U-Boot comms.
+	*/
+	gpio_direction_output(config->gpio, new_pos == SWITCH_SPI);
+	switch_pos = new_pos;
+
+	/* if the SPI was selected, clear any junk bytes in the UART */
+	if (switch_pos == SWITCH_UART) {
+		/* TODO: What if it is part-way through clocking in junk? */
+		udelay(100);
+		NS16550_clear(config->regs, config->port);
+	}
+}
+
+void pinmux_select_uart(NS16550_t regs)
+{
+	/* Also prevents calling spi_uart_switch() before relocation */
+	if (regs == local.regs)
+		spi_uart_switch(&local, SWITCH_UART);
+}
+
+void pinmux_select_spi(void)
+{
+	spi_uart_switch(&local, SWITCH_SPI);
+}
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
index f6599ded80..b6efa1c29a 100644
--- a/board/nvidia/seaboard/Makefile
+++ b/board/nvidia/seaboard/Makefile
@@ -31,7 +31,6 @@ endif
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o
-COBJS	+= ../common/board.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))

From 4560c7decc1b13121072621cee9874e042c059b7 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 5 Nov 2011 04:46:50 +0000
Subject: [PATCH 18/34] tegra2: spi: Support SPI / UART switch

Add the SPI / UART switch logic into the Tegra2 SPI driver so that it
can co-exist with the NS16550 UART.

We need the ns16550.h header for NS16550_t for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 drivers/spi/tegra2_spi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/spi/tegra2_spi.c b/drivers/spi/tegra2_spi.c
index fdcad093cf..56cb22963d 100644
--- a/drivers/spi/tegra2_spi.c
+++ b/drivers/spi/tegra2_spi.c
@@ -28,9 +28,11 @@
 #include <spi.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
+#include <ns16550.h>
 #include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/uart-spi-switch.h>
 #include <asm/arch/tegra2_spi.h>
 
 struct tegra_spi_slave {
@@ -128,6 +130,16 @@ int spi_claim_bus(struct spi_slave *slave)
 	 */
 	pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
 	pinmux_tristate_disable(PINGRP_LSPI);
+
+#ifndef CONFIG_SPI_UART_SWITCH
+	/*
+	 * NOTE:
+	 * Only set PinMux bits 3:2 to SPI here on boards that don't have the
+	 * SPI UART switch or subsequent UART data won't go out!  See
+	 * spi_uart_switch().
+	 */
+	/* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */
+#endif
 	return 0;
 }
 
@@ -145,6 +157,8 @@ void spi_cs_activate(struct spi_slave *slave)
 {
 	struct tegra_spi_slave *spi = to_tegra_spi(slave);
 
+	pinmux_select_spi();
+
 	/* CS is negated on Tegra, so drive a 1 to get a 0 */
 	setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL);
 }

From a04eba99f5a00aff54bef32cafa986830b094532 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sat, 5 Nov 2011 04:46:51 +0000
Subject: [PATCH 19/34] tegra2: Plumb in SPI/UART switch code

On Seaboard the UART and SPI interfere with each other. This causes the UART
to receive spurious zero bytes after SPI transactions and also means that
SPI can corrupt a few output characters when it starts up if they are still
in the UART buffer.

This updates the board to use the SPI/UART switch to avoid the problem.

For now this feature is turned off since it needs changes to the NS16550
UART to operate.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/nvidia/common/board.c      | 8 ++++++++
 board/nvidia/common/board.h      | 1 +
 board/nvidia/seaboard/seaboard.c | 3 +++
 3 files changed, 12 insertions(+)

diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 6a1312c5aa..c3f6796d5d 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -112,9 +112,13 @@ static void pin_mux_uart(int uart_ids)
  */
 int board_init(void)
 {
+	/* Do clocks and UART first so that printf() works */
 	clock_init();
 	clock_verify();
 
+#ifdef CONFIG_SPI_UART_SWITCH
+	gpio_config_uart();
+#endif
 #ifdef CONFIG_TEGRA2_SPI
 	spi_init();
 #endif
@@ -152,7 +156,11 @@ int board_early_init_f(void)
 	pin_mux_uart(uart_ids);
 
 	/* Initialize periph GPIOs */
+#ifdef CONFIG_SPI_UART_SWITCH
+	gpio_early_init_uart();
+#else
 	gpio_config_uart();
+#endif
 	return 0;
 }
 #endif	/* EARLY_INIT */
diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h
index 1f57086602..80fdcbe07a 100644
--- a/board/nvidia/common/board.h
+++ b/board/nvidia/common/board.h
@@ -26,5 +26,6 @@
 
 void gpio_config_uart(void);
 int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+void gpio_early_init_uart(void);
 
 #endif	/* BOARD_H */
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 7f2827b8be..0b779f6e9e 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -31,6 +31,8 @@
 #endif
 #include "../common/board.h"
 
+/* TODO: Remove this code when the SPI switch is working */
+#ifndef CONFIG_SPI_UART_SWITCH
 /*
  * Routine: gpio_config_uart_seaboard
  * Description: Force GPIO_PI3 low on Seaboard so UART4 works.
@@ -48,6 +50,7 @@ void gpio_config_uart(void)
 		return;
 	gpio_config_uart_seaboard();
 }
+#endif
 
 #ifdef CONFIG_TEGRA2_MMC
 /*

From 09743ba635be487766d959f8d86f2bdb8686ad92 Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding@avionic-design.de>
Date: Thu, 17 Nov 2011 00:04:05 +0000
Subject: [PATCH 20/34] tegra2: Always build with USE_PRIVATE_LIBGCC=yes.

The AVP on Tegra2 doesn't boot properly when U-Boot is linked against
the GCC provided libgcc. To work around this, always build and link
against a private libgcc for Tegra2-based boards.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/armv7/tegra2/config.mk | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk
index 8f9bdc9ff0..2303dba079 100644
--- a/arch/arm/cpu/armv7/tegra2/config.mk
+++ b/arch/arm/cpu/armv7/tegra2/config.mk
@@ -29,3 +29,5 @@
 ifdef CONFIG_TEGRA2
 CFLAGS_arch/arm/lib/board.o += -march=armv4t
 endif
+
+USE_PRIVATE_LIBGCC = yes

From 0350c6b924146814ab5390dd5f74665088354a21 Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding@avionic-design.de>
Date: Thu, 17 Nov 2011 00:04:06 +0000
Subject: [PATCH 21/34] tegra2: Change CONFIG_SYS_TEXT_BASE to 0x00108000.

NVIDIA's flashing tools assume that the bootloader is loaded at address
0x00108000. Instead of requiring non-standard builds of those tools
which allow a load address of 0x00E08000, this commit just switches all
Tegra2 boards to use the standard load address.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/tegra2-common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
index ffea4013eb..e6f385fac3 100644
--- a/include/configs/tegra2-common.h
+++ b/include/configs/tegra2-common.h
@@ -151,7 +151,7 @@
 #define PHYS_SDRAM_1		TEGRA2_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
 
-#define CONFIG_SYS_TEXT_BASE	0x00E08000
+#define CONFIG_SYS_TEXT_BASE	0x00108000
 #define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE

From 977a39e60036ebd5783bb8cd712014dcfdfb8617 Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding@avionic-design.de>
Date: Thu, 17 Nov 2011 00:10:23 +0000
Subject: [PATCH 22/34] tegra2: Move tegra2_mmc_init() prototype to public
 header.

tegra2_mmc_init() is implemented by the Tegra2 MMC driver. Since most of
the Tegra2-based boards will need to call it, this commit exports it in
the new public asm/arch/mmc.h header file to prevent each board from
providing its own prototype.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/include/asm/arch-tegra2/mmc.h | 27 ++++++++++++++++++++++++++
 board/nvidia/common/board.h            |  1 -
 board/nvidia/harmony/harmony.c         |  2 +-
 board/nvidia/seaboard/seaboard.c       |  2 +-
 drivers/mmc/tegra2_mmc.h               |  2 --
 5 files changed, 29 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-tegra2/mmc.h

diff --git a/arch/arm/include/asm/arch-tegra2/mmc.h b/arch/arm/include/asm/arch-tegra2/mmc.h
new file mode 100644
index 0000000000..c1f12dbe49
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/mmc.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_MMC_H_
+#define _TEGRA2_MMC_H_
+
+int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
+
+#endif /* TEGRA2_MMC_H_ */
diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h
index 80fdcbe07a..a638af2041 100644
--- a/board/nvidia/common/board.h
+++ b/board/nvidia/common/board.h
@@ -25,7 +25,6 @@
 #define _BOARD_H_
 
 void gpio_config_uart(void);
-int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
 void gpio_early_init_uart(void);
 
 #endif	/* BOARD_H */
diff --git a/board/nvidia/harmony/harmony.c b/board/nvidia/harmony/harmony.c
index 3cbe820c95..d5e147d269 100644
--- a/board/nvidia/harmony/harmony.c
+++ b/board/nvidia/harmony/harmony.c
@@ -25,11 +25,11 @@
 #include <asm/io.h>
 #include <asm/arch/tegra2.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/mmc.h>
 #include <asm/gpio.h>
 #ifdef CONFIG_TEGRA2_MMC
 #include <mmc.h>
 #endif
-#include "../common/board.h"
 
 /*
  * Routine: gpio_config_uart
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 0b779f6e9e..56acd6156f 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -25,11 +25,11 @@
 #include <asm/io.h>
 #include <asm/arch/tegra2.h>
 #include <asm/arch/pinmux.h>
+#include <asm/arch/mmc.h>
 #include <asm/gpio.h>
 #ifdef CONFIG_TEGRA2_MMC
 #include <mmc.h>
 #endif
-#include "../common/board.h"
 
 /* TODO: Remove this code when the SPI switch is working */
 #ifndef CONFIG_SPI_UART_SWITCH
diff --git a/drivers/mmc/tegra2_mmc.h b/drivers/mmc/tegra2_mmc.h
index b2f6c5baad..67c00db9de 100644
--- a/drivers/mmc/tegra2_mmc.h
+++ b/drivers/mmc/tegra2_mmc.h
@@ -127,7 +127,5 @@ struct mmc_host {
 	int cd_gpio;		/* Change Detect GPIO */
 };
 
-int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
-
 #endif	/* __ASSEMBLY__ */
 #endif	/* __TEGRA2_MMC_H_ */

From b1c0c73619d0a261a93e956b656751a7193e882f Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding@avionic-design.de>
Date: Thu, 17 Nov 2011 00:10:24 +0000
Subject: [PATCH 23/34] tegra2: Add common Avionic Design Tamonten support.

Tamonten is an NVIDIA Tegra2-based SO-DIMM processor module that is
derived from the Harmony reference design.

Changes in v3:
  * Remove unused gpio_config_uart().
  * Remove call to tegra2_start().
  * Use new tegra2_mmc_init().

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/avionic-design/common/tamonten.c | 160 +++++++++++++++++++++++++
 board/avionic-design/common/tamonten.h |  32 +++++
 2 files changed, 192 insertions(+)
 create mode 100644 board/avionic-design/common/tamonten.c
 create mode 100644 board/avionic-design/common/tamonten.h

diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
new file mode 100644
index 0000000000..98aa0f838d
--- /dev/null
+++ b/board/avionic-design/common/tamonten.c
@@ -0,0 +1,160 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011
+ *  Avionic Design GmbH <www.avionic-design.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/uart.h>
+#include <asm/arch/mmc.h>
+#include "tamonten.h"
+
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const struct tegra2_sysinfo sysinfo = {
+	CONFIG_TEGRA2_BOARD_STRING
+};
+
+/*
+ * Routine: timer_init
+ * Description: init the timestamp and lastinc value
+ */
+int timer_init(void)
+{
+	return 0;
+}
+
+static void enable_uart(enum periph_id pid)
+{
+	/* Assert UART reset and enable clock */
+	reset_set_enable(pid, 1);
+	clock_enable(pid);
+	clock_ll_set_source(pid, 0);	/* UARTx_CLK_SRC = 00, PLLP_OUT0 */
+
+	/* wait for 2us */
+	udelay(2);
+
+	/* De-assert reset to UART */
+	reset_set_enable(pid, 0);
+}
+
+/*
+ * Routine: clock_init_uart
+ * Description: init the PLL and clock for the UART(s)
+ */
+static void clock_init_uart(void)
+{
+#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
+	enable_uart(PERIPH_ID_UART4);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+/*
+ * Routine: pin_mux_uart
+ * Description: setup the pin muxes/tristate values for the UART(s)
+ */
+static void pin_mux_uart(void)
+{
+#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
+	pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
+
+	pinmux_tristate_disable(PINGRP_GMC);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+#ifdef CONFIG_TEGRA2_MMC
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the pin muxes/tristate values for the SDMMC(s)
+ */
+static void pin_mux_mmc(void)
+{
+	/* SDMMC4: config 3, x8 on 2nd set of pins */
+	pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
+	pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
+	pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
+
+	pinmux_tristate_disable(PINGRP_ATB);
+	pinmux_tristate_disable(PINGRP_GMA);
+	pinmux_tristate_disable(PINGRP_GME);
+}
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	clock_init();
+	clock_verify();
+
+	/* boot param addr */
+	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
+
+	return 0;
+}
+
+#ifdef CONFIG_TEGRA2_MMC
+/* this is a weak define that we are overriding */
+int board_mmc_init(bd_t *bd)
+{
+	debug("board_mmc_init called\n");
+	/* Enable muxes, etc. for SDMMC controllers */
+	pin_mux_mmc();
+	gpio_config_mmc();
+
+	debug("board_mmc_init: init eMMC\n");
+	/* init dev 0, eMMC chip, with 4-bit bus */
+	tegra2_mmc_init(0, 4, -1, GPIO_PH2);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+	/* Initialize essential common plls */
+	clock_early_init();
+
+	/* Initialize UART clocks */
+	clock_init_uart();
+
+	/* Initialize periph pinmuxes */
+	pin_mux_uart();
+
+	return 0;
+}
+#endif /* EARLY_INIT */
diff --git a/board/avionic-design/common/tamonten.h b/board/avionic-design/common/tamonten.h
new file mode 100644
index 0000000000..0e60b0fadc
--- /dev/null
+++ b/board/avionic-design/common/tamonten.h
@@ -0,0 +1,32 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011
+ *  Avionic Design GmbH <www.avionic-design.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TAMONTEN_H_
+#define _TAMONTEN_H_
+
+void tegra2_start(void);
+void gpio_config_mmc(void);
+
+#endif /* TAMONTEN_H */

From 4026aca6d6d2b6b4501acaae6f2f5d904a0f3ee1 Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding@avionic-design.de>
Date: Thu, 17 Nov 2011 00:10:25 +0000
Subject: [PATCH 24/34] tegra2: Add Avionic Design Plutux support.

The Plutux is a set-top box device based on the Tamonten processor
module. It can be connected to a display via an HDMI output.

Changes in v3:
  * Remove unused implementation of gpio_config_uart().
  * Implement MMC/SD card detection.
  * Drop board_mmc_getcd() which is now implemented by common Tegra2
    code.
  * Add MAINTAINERS entry.

Changes in v2:
  * No longer override the default CONFIG_SYS_TEXT_BASE setting.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 MAINTAINERS                          |  4 ++
 board/avionic-design/plutux/Makefile | 50 ++++++++++++++++++++++
 board/avionic-design/plutux/plutux.c | 45 ++++++++++++++++++++
 boards.cfg                           |  1 +
 include/configs/plutux.h             | 62 ++++++++++++++++++++++++++++
 5 files changed, 162 insertions(+)
 create mode 100644 board/avionic-design/plutux/Makefile
 create mode 100644 board/avionic-design/plutux/plutux.c
 create mode 100644 include/configs/plutux.h

diff --git a/MAINTAINERS b/MAINTAINERS
index a856b4cebb..3160ec5d41 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -783,6 +783,10 @@ Stelian Pop <stelian@popies.net>
 	at91sam9263ek	ARM926EJS (AT91SAM9263 SoC)
 	at91sam9rlek	ARM926EJS (AT91SAM9RL SoC)
 
+Thierry Reding <thierry.reding@avionic-design.de>
+
+	plutux		Tegra2 (ARM7 & A9 Dual Core)
+
 Tom Rini <trini@ti.com>
 
 	omap3_evm	ARM ARMV7 (OMAP3xx SoC)
diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile
new file mode 100644
index 0000000000..b0c318c439
--- /dev/null
+++ b/board/avionic-design/plutux/Makefile
@@ -0,0 +1,50 @@
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+#  (C) Copyright 2011
+#  Avionic Design GmbH <www.avionic-design.de>
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+COBJS	+= ../common/tamonten.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/avionic-design/plutux/plutux.c b/board/avionic-design/plutux/plutux.c
new file mode 100644
index 0000000000..42c80940c1
--- /dev/null
+++ b/board/avionic-design/plutux/plutux.c
@@ -0,0 +1,45 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011
+ *  Avionic Design GmbH <www.avionic-design.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/tegra2.h>
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
+
+#ifdef CONFIG_TEGRA2_MMC
+/*
+ * Routine: gpio_config_mmc
+ * Description: Set GPIOs for SD card
+ */
+void gpio_config_mmc(void)
+{
+	/* configure pin as input for card detect */
+	gpio_request(GPIO_PH2, "SD4 CD");
+	gpio_direction_input(GPIO_PH2);
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 406d64dfe0..e70cc863ec 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -245,6 +245,7 @@ xaeniax                      arm         pxa
 zipitz2                      arm         pxa
 colibri_pxa270               arm         pxa         -                   toradex
 jornada                      arm         sa1100
+plutux                       arm         armv7       plutux              avionic-design tegra2
 atngw100                     avr32       at32ap      -                   atmel          at32ap700x
 atstk1002                    avr32       at32ap      atstk1000           atmel          at32ap700x
 atstk1003                    avr32       at32ap      atstk1000           atmel          at32ap700x
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
new file mode 100644
index 0000000000..033eda025f
--- /dev/null
+++ b/include/configs/plutux.h
@@ -0,0 +1,62 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011
+ *  Avionic Design GmbH <www.avionic-design.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra2-common.h"
+
+/* High-level configuration options */
+#define TEGRA2_SYSMEM			"mem=384M@0M nvmem=128M@384M"
+#define V_PROMPT			"Tegra2 (Plutux) # "
+#define CONFIG_TEGRA2_BOARD_STRING	"Avionic Design Plutux"
+#define CONFIG_SYS_BOARD_ODMDATA	0x2b2d8011
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA2_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+#define CONFIG_FIT
+
+#define CONFIG_BOOTCOMMAND				\
+	"mmc rescan;"					\
+	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
+	"bootm"
+
+#endif /* __CONFIG_H */

From c91915e90551ebba7972bc4b29eb417bd3f6ea9b Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding@avionic-design.de>
Date: Thu, 17 Nov 2011 00:10:26 +0000
Subject: [PATCH 25/34] tegra2: Add Avionic Design Medcom support.

The Medcom is a 16:9 15" terminal that is used for patient infotainment
in hospitals.

Changes in v3:
  * Remove unused implementation of gpio_config_uart().
  * Implement MMC/SD card detection.
  * Drop board_mmc_getcd() which is now implemented by common Tegra2
    code.
  * Add MAINTAINERS entry.

Changes in v2:
  * No longer override the default CONFIG_SYS_TEXT_BASE setting.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 MAINTAINERS                          |  1 +
 board/avionic-design/medcom/Makefile | 50 ++++++++++++++++++++++
 board/avionic-design/medcom/medcom.c | 45 ++++++++++++++++++++
 boards.cfg                           |  1 +
 include/configs/medcom.h             | 62 ++++++++++++++++++++++++++++
 5 files changed, 159 insertions(+)
 create mode 100644 board/avionic-design/medcom/Makefile
 create mode 100644 board/avionic-design/medcom/medcom.c
 create mode 100644 include/configs/medcom.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 3160ec5d41..4bf12b5c4f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -786,6 +786,7 @@ Stelian Pop <stelian@popies.net>
 Thierry Reding <thierry.reding@avionic-design.de>
 
 	plutux		Tegra2 (ARM7 & A9 Dual Core)
+	medcom		Tegra2 (ARM7 & A9 Dual Core)
 
 Tom Rini <trini@ti.com>
 
diff --git a/board/avionic-design/medcom/Makefile b/board/avionic-design/medcom/Makefile
new file mode 100644
index 0000000000..b0c318c439
--- /dev/null
+++ b/board/avionic-design/medcom/Makefile
@@ -0,0 +1,50 @@
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+#  (C) Copyright 2011
+#  Avionic Design GmbH <www.avionic-design.de>
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+COBJS	+= ../common/tamonten.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/avionic-design/medcom/medcom.c b/board/avionic-design/medcom/medcom.c
new file mode 100644
index 0000000000..42c80940c1
--- /dev/null
+++ b/board/avionic-design/medcom/medcom.c
@@ -0,0 +1,45 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011
+ *  Avionic Design GmbH <www.avionic-design.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/tegra2.h>
+#ifdef CONFIG_TEGRA2_MMC
+#include <mmc.h>
+#endif
+
+#ifdef CONFIG_TEGRA2_MMC
+/*
+ * Routine: gpio_config_mmc
+ * Description: Set GPIOs for SD card
+ */
+void gpio_config_mmc(void)
+{
+	/* configure pin as input for card detect */
+	gpio_request(GPIO_PH2, "SD4 CD");
+	gpio_direction_input(GPIO_PH2);
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index e70cc863ec..0b325329fb 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -246,6 +246,7 @@ zipitz2                      arm         pxa
 colibri_pxa270               arm         pxa         -                   toradex
 jornada                      arm         sa1100
 plutux                       arm         armv7       plutux              avionic-design tegra2
+medcom                       arm         armv7       medcom              avionic-design tegra2
 atngw100                     avr32       at32ap      -                   atmel          at32ap700x
 atstk1002                    avr32       at32ap      atstk1000           atmel          at32ap700x
 atstk1003                    avr32       at32ap      atstk1000           atmel          at32ap700x
diff --git a/include/configs/medcom.h b/include/configs/medcom.h
new file mode 100644
index 0000000000..6a54925bd7
--- /dev/null
+++ b/include/configs/medcom.h
@@ -0,0 +1,62 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *  (C) Copyright 2011
+ *  Avionic Design GmbH <www.avionic-design.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra2-common.h"
+
+/* High-level configuration options */
+#define TEGRA2_SYSMEM			"mem=384M@0M nvmem=128M@384M"
+#define V_PROMPT			"Tegra2 (Medcom) # "
+#define CONFIG_TEGRA2_BOARD_STRING	"Avionic Design Medcom"
+#define CONFIG_SYS_BOARD_ODMDATA	0x2b0d8011
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTD	/* UARTD: debug UART */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA2_MMC
+#define CONFIG_CMD_MMC
+
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+
+#define CONFIG_FIT
+
+#define CONFIG_BOOTCOMMAND				\
+	"mmc rescan;"					\
+	"ext2load mmc 0 0x17000000 /boot/uImage;"	\
+	"bootm"
+
+#endif /* __CONFIG_H */

From a783bdb870047a837ec4928d4c3d222b1b1b506c Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 28 Nov 2011 15:04:41 +0000
Subject: [PATCH 26/34] tegra: Fix build error in plutux, medcom

We need to define CONFIG_ENV_IS_NOWHERE to avoid this error:

cmd_nvedit.c:69:3: error: #error Define one of CONFIG_ENV_IS_IN_...

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 include/configs/medcom.h | 2 ++
 include/configs/plutux.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/include/configs/medcom.h b/include/configs/medcom.h
index 6a54925bd7..2dc350762d 100644
--- a/include/configs/medcom.h
+++ b/include/configs/medcom.h
@@ -41,6 +41,8 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
+#define CONFIG_ENV_IS_NOWHERE
+
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC
diff --git a/include/configs/plutux.h b/include/configs/plutux.h
index 033eda025f..f869191f34 100644
--- a/include/configs/plutux.h
+++ b/include/configs/plutux.h
@@ -41,6 +41,8 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F
 
+#define CONFIG_ENV_IS_NOWHERE
+
 /* SD/MMC */
 #define CONFIG_MMC
 #define CONFIG_GENERIC_MMC

From 5b37bd3afdae436b8c1490e19a436a11e652e1cf Mon Sep 17 00:00:00 2001
From: Tom Warren <twarren@nvidia.com>
Date: Mon, 19 Dec 2011 15:58:06 -0700
Subject: [PATCH 27/34] arm: Tegra: Fix Harmony and Ventana builds in
 u-boot-tegra/master

Seaboard changes have removed the need for common/board.o in the
Makefile. Propagate this change to the other Tegra2 builds.

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/nvidia/harmony/Makefile | 1 -
 board/nvidia/ventana/Makefile | 3 +--
 include/configs/ventana.h     | 3 +++
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
index f6599ded80..b6efa1c29a 100644
--- a/board/nvidia/harmony/Makefile
+++ b/board/nvidia/harmony/Makefile
@@ -31,7 +31,6 @@ endif
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= $(BOARD).o
-COBJS	+= ../common/board.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile
index d5140c8135..eced3239f4 100644
--- a/board/nvidia/ventana/Makefile
+++ b/board/nvidia/ventana/Makefile
@@ -31,8 +31,7 @@ endif
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	+= ../seaboard/seaboard.o
-COBJS	+= ../common/board.o
+COBJS	= ../seaboard/seaboard.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/include/configs/ventana.h b/include/configs/ventana.h
index afd6ff610c..acc9b434bb 100644
--- a/include/configs/ventana.h
+++ b/include/configs/ventana.h
@@ -52,4 +52,7 @@
 #define CONFIG_EFI_PARTITION
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
+
+/* Environment not stored */
+#define CONFIG_ENV_IS_NOWHERE
 #endif /* __CONFIG_H */

From ccdd6eaecb6c11efa884ac14336f8e9b84d6dded Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 28 Nov 2011 15:04:35 +0000
Subject: [PATCH 28/34] tegra: Move cpu_init_cp15() to arch_cpu_init()

This call is more of an architecture requirement than a board
one, so move it there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/armv7/tegra2/board.c | 4 ++++
 board/nvidia/common/board.c       | 3 ---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
index 59dce8f8de..d0a599edc5 100644
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -80,6 +80,10 @@ int arch_cpu_init(void)
 {
 	/* Fire up the Cortex A9 */
 	tegra2_start();
+
+	/* We didn't do this init in start.S, so do it now */
+	cpu_init_cp15();
+
 	return 0;
 }
 #endif
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index c3f6796d5d..219b26aac4 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -143,9 +143,6 @@ int board_early_init_f(void)
 	uart_ids |= UARTD;
 #endif
 
-	/* We didn't do this init in start.S, so do it now */
-	cpu_init_cp15();
-
 	/* Initialize essential common plls */
 	clock_early_init();
 

From 905ed41aad2f80b64b1163a55e18ee4e5278e708 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 28 Nov 2011 15:04:36 +0000
Subject: [PATCH 29/34] tegra: Move clock_early_init() to arch_cpu_init()

The clock init is not board specific, so move it into
the cpu code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/armv7/tegra2/board.c | 3 +++
 board/nvidia/common/board.c       | 3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
index d0a599edc5..803ddc15d9 100644
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -84,6 +84,9 @@ int arch_cpu_init(void)
 	/* We didn't do this init in start.S, so do it now */
 	cpu_init_cp15();
 
+	/* Initialize essential common plls */
+	clock_early_init();
+
 	return 0;
 }
 #endif
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 219b26aac4..0ff656aeee 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -143,9 +143,6 @@ int board_early_init_f(void)
 	uart_ids |= UARTD;
 #endif
 
-	/* Initialize essential common plls */
-	clock_early_init();
-
 	/* Initialize UART clocks */
 	clock_init_uart(uart_ids);
 

From 8442fd3c6a82def9beac46ab683f2fd4bf8f8f14 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 28 Nov 2011 15:04:37 +0000
Subject: [PATCH 30/34] tegra: add clock_ll_start_uart() to enable UART prior
 to reloc

Most boards will want to enable a UART early. This function provides
that feature in Tegra architecture code so the code does not need to be
copied on every board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/armv7/tegra2/clock.c        | 14 ++++++++++++++
 arch/arm/include/asm/arch-tegra2/clock.h | 11 +++++++++++
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/tegra2/clock.c b/arch/arm/cpu/armv7/tegra2/clock.c
index 03ac1e3ed0..11d2346d83 100644
--- a/arch/arm/cpu/armv7/tegra2/clock.c
+++ b/arch/arm/cpu/armv7/tegra2/clock.c
@@ -904,6 +904,20 @@ static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
 	return 0;
 }
 
+void clock_ll_start_uart(enum periph_id periph_id)
+{
+	/* Assert UART reset and enable clock */
+	reset_set_enable(periph_id, 1);
+	clock_enable(periph_id);
+	clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
+
+	/* wait for 2us */
+	udelay(2);
+
+	/* De-assert reset to UART */
+	reset_set_enable(periph_id, 0);
+}
+
 int clock_verify(void)
 {
 	struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
diff --git a/arch/arm/include/asm/arch-tegra2/clock.h b/arch/arm/include/asm/arch-tegra2/clock.h
index 49e9904b57..080ef18e81 100644
--- a/arch/arm/include/asm/arch-tegra2/clock.h
+++ b/arch/arm/include/asm/arch-tegra2/clock.h
@@ -344,6 +344,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
  */
 unsigned clock_get_rate(enum clock_id clkid);
 
+/**
+ * Start up a UART using low-level calls
+ *
+ * Prior to relocation clock_start_periph_pll() cannot be called. This
+ * function provides a way to set up a UART using low-level calls which
+ * do not require BSS.
+ *
+ * @param periph_id	Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
+ */
+void clock_ll_start_uart(enum periph_id periph_id);
+
 /*
  * Checks that clocks are valid and prints a warning if not
  *

From b5a5b351979db29fd1aa33d8f31782d7f91731b0 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 28 Nov 2011 15:04:38 +0000
Subject: [PATCH 31/34] tegra: Add a function mux feature

funcmux permits selection of config options for particular peripherals,
such as the pins that are used for that peripheral, if there are several
options.

Add UART selection to start with.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/armv7/tegra2/Makefile         |  2 +-
 arch/arm/cpu/armv7/tegra2/funcmux.c        | 58 ++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/funcmux.h | 41 +++++++++++++++
 3 files changed, 100 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/funcmux.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/funcmux.h

diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile
index 955c3b6dc4..f668a818fb 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -33,7 +33,7 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= ap20.o board.o clock.o pinmux.o sys_info.o timer.o
+COBJS	:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/funcmux.c b/arch/arm/cpu/armv7/tegra2/funcmux.c
new file mode 100644
index 0000000000..0878f51110
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/funcmux.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra2 high-level function multiplexing */
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pinmux.h>
+
+int funcmux_select(enum periph_id id, int config)
+{
+	if (config != 0) {
+		debug("%s: invalid config %d for periph_id %d", __func__,
+		      config, id);
+		return -1;
+	}
+	switch (id) {
+	case PERIPH_ID_UART1:
+		pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
+		pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
+		pinmux_tristate_disable(PINGRP_IRRX);
+		pinmux_tristate_disable(PINGRP_IRTX);
+		break;
+
+	case PERIPH_ID_UART2:
+		pinmux_set_func(PINGRP_UAD, PMUX_FUNC_IRDA);
+		pinmux_tristate_disable(PINGRP_UAD);
+		break;
+
+	case PERIPH_ID_UART4:
+		pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
+		pinmux_tristate_disable(PINGRP_GMC);
+		break;
+
+	default:
+		debug("%s: invalid periph_id %d", __func__, id);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/include/asm/arch-tegra2/funcmux.h b/arch/arm/include/asm/arch-tegra2/funcmux.h
new file mode 100644
index 0000000000..2d724a2872
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/funcmux.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra2 high-level function multiplexing */
+
+#ifndef __FUNCMUX_H
+#define __FUNCMUX_H
+
+/**
+ * Select a config for a particular peripheral.
+ *
+ * Each peripheral can operate through a number of configurations,
+ * which are sets of pins that it uses to bring out its signals.
+ * The basic config is 0, and higher numbers indicate different
+ * pinmux settings to bring the peripheral out on other pins,
+ *
+ * @param id		Peripheral id
+ * @param config	Configuration to use (generally 0)
+ * @return 0 if ok, -1 on error (e.g. incorrect id or config)
+ */
+int funcmux_select(enum periph_id id, int config);
+
+#endif

From bb6997f8402a9074fc7a97c6fb4b892a4dcb095b Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 28 Nov 2011 15:04:39 +0000
Subject: [PATCH 32/34] tegra: Add support for UART init in cpu board.c

We add a way of initialising the selected of UARTs prior to relocation.
Boards can use the board_init_uart_f() instead of repeating this code
themselves.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 arch/arm/cpu/armv7/tegra2/board.c        | 51 ++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/board.h | 30 ++++++++++++++
 2 files changed, 81 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-tegra2/board.h

diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
index 803ddc15d9..ea06570bfa 100644
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -24,12 +24,22 @@
 #include <common.h>
 #include <asm/io.h>
 #include "ap20.h"
+#include <asm/arch/clock.h>
+#include <asm/arch/funcmux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/tegra2.h>
 #include <asm/arch/pmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+enum {
+	/* UARTs which we can enable */
+	UARTA	= 1 << 0,
+	UARTB	= 1 << 1,
+	UARTD	= 1 << 3,
+	UART_COUNT = 4,
+};
+
 /*
  * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
  * so we are using this value to identify memory size.
@@ -90,3 +100,44 @@ int arch_cpu_init(void)
 	return 0;
 }
 #endif
+
+/**
+ * Set up the specified uarts
+ *
+ * @param uarts_ids	Mask containing UARTs to init (UARTx)
+ */
+static void setup_uarts(int uart_ids)
+{
+	static enum periph_id id_for_uart[] = {
+		PERIPH_ID_UART1,
+		PERIPH_ID_UART2,
+		PERIPH_ID_UART3,
+		PERIPH_ID_UART4,
+	};
+	size_t i;
+
+	for (i = 0; i < UART_COUNT; i++) {
+		if (uart_ids & (1 << i)) {
+			enum periph_id id = id_for_uart[i];
+
+			funcmux_select(id, 0);
+			clock_ll_start_uart(id);
+		}
+	}
+}
+
+void board_init_uart_f(void)
+{
+	int uart_ids = 0;	/* bit mask of which UART ids to enable */
+
+#ifdef CONFIG_TEGRA2_ENABLE_UARTA
+	uart_ids |= UARTA;
+#endif
+#ifdef CONFIG_TEGRA2_ENABLE_UARTB
+	uart_ids |= UARTB;
+#endif
+#ifdef CONFIG_TEGRA2_ENABLE_UARTD
+	uart_ids |= UARTD;
+#endif
+	setup_uarts(uart_ids);
+}
diff --git a/arch/arm/include/asm/arch-tegra2/board.h b/arch/arm/include/asm/arch-tegra2/board.h
new file mode 100644
index 0000000000..a90d36c708
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/board.h
@@ -0,0 +1,30 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_BOARD_H_
+#define _TEGRA_BOARD_H_
+
+/* Setup UARTs for the board according to the selected config */
+void board_init_uart_f(void);
+
+#endif

From f46a945653146d62e8e8261f119642e302d704d2 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 28 Nov 2011 15:04:40 +0000
Subject: [PATCH 33/34] tegra: Move boards over to use arch-level board UART
 function

Now that we can set up the UART in common tegra code, make the boards
use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/avionic-design/common/tamonten.c | 50 +----------------
 board/nvidia/common/board.c            | 76 +-------------------------
 2 files changed, 5 insertions(+), 121 deletions(-)

diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index 98aa0f838d..97e59fb324 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -27,6 +27,7 @@
 #include <ns16550.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
+#include <asm/arch/board.h>
 #include <asm/arch/tegra2.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/clk_rst.h>
@@ -55,44 +56,6 @@ int timer_init(void)
 	return 0;
 }
 
-static void enable_uart(enum periph_id pid)
-{
-	/* Assert UART reset and enable clock */
-	reset_set_enable(pid, 1);
-	clock_enable(pid);
-	clock_ll_set_source(pid, 0);	/* UARTx_CLK_SRC = 00, PLLP_OUT0 */
-
-	/* wait for 2us */
-	udelay(2);
-
-	/* De-assert reset to UART */
-	reset_set_enable(pid, 0);
-}
-
-/*
- * Routine: clock_init_uart
- * Description: init the PLL and clock for the UART(s)
- */
-static void clock_init_uart(void)
-{
-#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
-	enable_uart(PERIPH_ID_UART4);
-#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
-}
-
-/*
- * Routine: pin_mux_uart
- * Description: setup the pin muxes/tristate values for the UART(s)
- */
-static void pin_mux_uart(void)
-{
-#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
-	pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
-
-	pinmux_tristate_disable(PINGRP_GMC);
-#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
-}
-
 #ifdef CONFIG_TEGRA2_MMC
 /*
  * Routine: pin_mux_mmc
@@ -146,15 +109,8 @@ int board_mmc_init(bd_t *bd)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	/* Initialize essential common plls */
-	clock_early_init();
-
-	/* Initialize UART clocks */
-	clock_init_uart();
-
-	/* Initialize periph pinmuxes */
-	pin_mux_uart();
-
+	/* Initialize selected UARTs */
+	board_init_uart_f();
 	return 0;
 }
 #endif /* EARLY_INIT */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 0ff656aeee..e8253a083d 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -27,6 +27,7 @@
 #include <asm/arch/tegra2.h>
 #include <asm/arch/sys_proto.h>
 
+#include <asm/arch/board.h>
 #include <asm/arch/clk_rst.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
@@ -36,13 +37,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-enum {
-	/* UARTs which we can enable */
-	UARTA	= 1 << 0,
-	UARTB	= 1 << 1,
-	UARTD	= 1 << 3,
-};
-
 const struct tegra2_sysinfo sysinfo = {
 	CONFIG_TEGRA2_BOARD_STRING
 };
@@ -56,56 +50,6 @@ int timer_init(void)
 	return 0;
 }
 
-static void enable_uart(enum periph_id pid)
-{
-	/* Assert UART reset and enable clock */
-	reset_set_enable(pid, 1);
-	clock_enable(pid);
-	clock_ll_set_source(pid, 0);	/* UARTx_CLK_SRC = 00, PLLP_OUT0 */
-
-	/* wait for 2us */
-	udelay(2);
-
-	/* De-assert reset to UART */
-	reset_set_enable(pid, 0);
-}
-
-/*
- * Routine: clock_init_uart
- * Description: init clock for the UART(s)
- */
-static void clock_init_uart(int uart_ids)
-{
-	if (uart_ids & UARTA)
-		enable_uart(PERIPH_ID_UART1);
-	if (uart_ids & UARTB)
-		enable_uart(PERIPH_ID_UART2);
-	if (uart_ids & UARTD)
-		enable_uart(PERIPH_ID_UART4);
-}
-
-/*
- * Routine: pin_mux_uart
- * Description: setup the pin muxes/tristate values for the UART(s)
- */
-static void pin_mux_uart(int uart_ids)
-{
-	if (uart_ids & UARTA) {
-		pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
-		pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
-		pinmux_tristate_disable(PINGRP_IRRX);
-		pinmux_tristate_disable(PINGRP_IRTX);
-	}
-	if (uart_ids & UARTB) {
-		pinmux_set_func(PINGRP_UAD, PMUX_FUNC_IRDA);
-		pinmux_tristate_disable(PINGRP_UAD);
-	}
-	if (uart_ids & UARTD) {
-		pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
-		pinmux_tristate_disable(PINGRP_GMC);
-	}
-}
-
 /*
  * Routine: board_init
  * Description: Early hardware init.
@@ -131,23 +75,7 @@ int board_init(void)
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-	int uart_ids = 0;	/* bit mask of which UART ids to enable */
-
-#ifdef CONFIG_TEGRA2_ENABLE_UARTA
-	uart_ids |= UARTA;
-#endif
-#ifdef CONFIG_TEGRA2_ENABLE_UARTB
-	uart_ids |= UARTB;
-#endif
-#ifdef CONFIG_TEGRA2_ENABLE_UARTD
-	uart_ids |= UARTD;
-#endif
-
-	/* Initialize UART clocks */
-	clock_init_uart(uart_ids);
-
-	/* Initialize periph pinmuxes */
-	pin_mux_uart(uart_ids);
+	board_init_uart_f();
 
 	/* Initialize periph GPIOs */
 #ifdef CONFIG_SPI_UART_SWITCH

From a747cc0a8c55d69a56a6db80a35cdb48c853447d Mon Sep 17 00:00:00 2001
From: Thierry Reding <thierry.reding@avionic-design.de>
Date: Wed, 21 Dec 2011 23:22:54 +0000
Subject: [PATCH 34/34] tegra2: Optimize out-of-tree build for Ventana.

As proposed by Mike Frysinger, mkdir can take more than one argument.
Instead of spawning two processes, create both the common and seaboard
directories in one go.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
 board/nvidia/ventana/Makefile | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile
index eced3239f4..e3b7435530 100644
--- a/board/nvidia/ventana/Makefile
+++ b/board/nvidia/ventana/Makefile
@@ -25,8 +25,7 @@
 include $(TOPDIR)/config.mk
 
 ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../seaboard)
-$(shell mkdir -p $(obj)../common)
+$(shell mkdir -p $(obj)../common $(obj)../seaboard)
 endif
 
 LIB	= $(obj)lib$(BOARD).o