eaw/u-boot
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

configs: Resync with savedefconfig

Browse Source 
Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2022-08-23 15:24:14 -04:00
parent 1d323d8306
commit 1247c35c80
814 changed files with 361 additions and 1105 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
scripts/config_whitelist.txt
View File

@@ -54,12 +54,10 @@ CONFIG_FSL_SDHC_V2_3
CONFIG_FSL_SERDES
CONFIG_FSL_SERDES1
CONFIG_FSL_SERDES2
CONFIG_FSL_SGMII_RISER
CONFIG_FTMAC100_BASE
CONFIG_FTRTC010_EXTCLK
CONFIG_FTRTC010_PCLK
CONFIG_GATEWAYIP
CONFIG_GLOBAL_TIMER
CONFIG_GMII
CONFIG_G_DNL_THOR_PRODUCT_NUM
CONFIG_G_DNL_THOR_VENDOR_NUM
@@ -404,15 +402,12 @@ CONFIG_SAR_REG
CONFIG_SCIF_A
CONFIG_SCSI_DEV_LIST
CONFIG_SC_TIMER_CLK
CONFIG_SDRAM_OFFSET_FOR_RT
CONFIG_SERIAL_BOOT
CONFIG_SERIAL_SOFTWARE_FIFO
CONFIG_SERVERIP
CONFIG_SETUP_INITRD_TAG
CONFIG_SET_DFU_ALT_BUF_LEN
CONFIG_SH73A0
CONFIG_SH_ETHER_ALIGNE_SIZE
CONFIG_SH_ETHER_BASE_ADDR
CONFIG_SH_ETHER_CACHE_INVALIDATE
CONFIG_SH_ETHER_CACHE_WRITEBACK
CONFIG_SH_ETHER_PHY_ADDR
@@ -421,7 +416,6 @@ CONFIG_SH_ETHER_SH7734_MII
CONFIG_SH_ETHER_USE_PORT
CONFIG_SH_GPIO_PFC
CONFIG_SH_QSPI_BASE
CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
CONFIG_SLIC
CONFIG_SMDK5420
CONFIG_SMP_PEN_ADDR
@@ -588,7 +582,6 @@ CONFIG_SYS_DDR_CLKSEL
CONFIG_SYS_DDR_CLK_CNTL
CONFIG_SYS_DDR_CLK_CONTROL
CONFIG_SYS_DDR_CLK_CTRL
CONFIG_SYS_DDR_CLK_CTRL_800
CONFIG_SYS_DDR_CONFIG
CONFIG_SYS_DDR_CONFIG_2
CONFIG_SYS_DDR_CONTROL
@@ -602,13 +595,10 @@ CONFIG_SYS_DDR_CS1_CONFIG_2
CONFIG_SYS_DDR_INIT_ADDR
CONFIG_SYS_DDR_INIT_EXT_ADDR
CONFIG_SYS_DDR_INTERVAL
CONFIG_SYS_DDR_INTERVAL_800
CONFIG_SYS_DDR_MODE
CONFIG_SYS_DDR_MODE2
CONFIG_SYS_DDR_MODE_1
CONFIG_SYS_DDR_MODE_1_800
CONFIG_SYS_DDR_MODE_2
CONFIG_SYS_DDR_MODE_2_800
CONFIG_SYS_DDR_MODE_CONTROL
CONFIG_SYS_DDR_RCW_1
CONFIG_SYS_DDR_RCW_2
@@ -618,13 +608,9 @@ CONFIG_SYS_DDR_SDRAM_CFG2
CONFIG_SYS_DDR_SDRAM_CLK_CNTL
CONFIG_SYS_DDR_SR_CNTR
CONFIG_SYS_DDR_TIMING_0
CONFIG_SYS_DDR_TIMING_0_800
CONFIG_SYS_DDR_TIMING_1
CONFIG_SYS_DDR_TIMING_1_800
CONFIG_SYS_DDR_TIMING_2
CONFIG_SYS_DDR_TIMING_2_800
CONFIG_SYS_DDR_TIMING_3
CONFIG_SYS_DDR_TIMING_3_800
CONFIG_SYS_DDR_TIMING_4
CONFIG_SYS_DDR_TIMING_5
CONFIG_SYS_DDR_WRLVL_CONTROL
@@ -1228,7 +1214,6 @@ CONFIG_SYS_SDRC_MR_VAL5
CONFIG_SYS_SDRC_TR_VAL
CONFIG_SYS_SDRC_TR_VAL1
CONFIG_SYS_SDRC_TR_VAL2
CONFIG_SYS_SD_VOLTAGE
CONFIG_SYS_SEC_MON_ADDR
CONFIG_SYS_SEC_MON_OFFSET
CONFIG_SYS_SERIAL0
@@ -1296,13 +1281,7 @@ CONFIG_SYS_UART_PORT
CONFIG_SYS_UBOOT_BASE
CONFIG_SYS_UBOOT_START
CONFIG_SYS_UEC
CONFIG_SYS_UEC2_ETH_TYPE
CONFIG_SYS_UEC2_INTERFACE_SPEED
CONFIG_SYS_UEC2_INTERFACE_TYPE
CONFIG_SYS_UEC2_PHY_ADDR
CONFIG_SYS_UEC2_RX_CLK
CONFIG_SYS_UEC2_TX_CLK
CONFIG_SYS_UEC2_UCC_NUM
CONFIG_SYS_USB_OHCI_REGS_BASE
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN