- R8A774A1 / Beacon EmbeddedWorks RZG2M Dev Kit support
This commit is contained in:
Tom Rini
89
include/configs/beacon-rzg2m.h
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89
include/configs/beacon-rzg2m.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Compass Electronics Group, LLC
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*/
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#ifndef __BEACON_RZG2M_H
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#define __BEACON_RZG2M_H
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#include "rcar-gen3-common.h"
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/* Ethernet RAVB */
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#define CONFIG_BITBANGMII_MULTI
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/* Environment in eMMC, at the end of 2nd "boot sector" */
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/* #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) */
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#define CONFIG_SYS_MMC_ENV_DEV 1
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#define CONFIG_SYS_MMC_ENV_PART 2
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"usb_pgood_delay=2000\0" \
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"script=boot.scr\0" \
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"image=Image\0" \
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"console=ttySC0,115200\0" \
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"fdt_addr=0x48000000\0" \
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"loadaddr=0x48080000\0" \
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"boot_fdt=try\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"initrd_addr=0x43800000\0" \
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"mmcdev=0\0" \
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"mmcpart=1\0" \
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"mmcrootpart=2\0" \
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"finduuid=part uuid mmc ${mmcdev}:${mmcrootpart} uuid\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} " \
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" root=PARTUUID=${uuid} rootwait rw ${optargs}\0" \
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"loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run finduuid; run mmcargs; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"else " \
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"echo wait for boot; " \
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"fi;\0" \
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"netargs=setenv bootargs ${jh_clk} console=${console} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"if test ${ip_dyn} = yes; then " \
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"setenv get_cmd dhcp; " \
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"else " \
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"setenv get_cmd tftp; " \
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"fi; " \
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"${get_cmd} ${loadaddr} ${image}; " \
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
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"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi; " \
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"else " \
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"booti; " \
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"fi;\0"
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#undef CONFIG_BOOTCOMMAND
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else booti ${loadaddr} - ${fdt_addr}; fi"
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#endif /* __BEACON_RZG2M_H */
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65
include/dt-bindings/clock/r8a774a1-cpg-mssr.h
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65
include/dt-bindings/clock/r8a774a1-cpg-mssr.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* r8a774a1 CPG Core Clocks */
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#define R8A774A1_CLK_Z 0
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#define R8A774A1_CLK_Z2 1
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#define R8A774A1_CLK_ZR 2
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#define R8A774A1_CLK_ZG 3
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#define R8A774A1_CLK_ZTR 4
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#define R8A774A1_CLK_ZTRD2 5
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#define R8A774A1_CLK_ZT 6
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#define R8A774A1_CLK_ZX 7
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#define R8A774A1_CLK_S0D1 8
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#define R8A774A1_CLK_S0D2 9
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#define R8A774A1_CLK_S0D3 10
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#define R8A774A1_CLK_S0D4 11
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#define R8A774A1_CLK_S0D6 12
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#define R8A774A1_CLK_S0D8 13
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#define R8A774A1_CLK_S0D12 14
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#define R8A774A1_CLK_S1D1 15
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#define R8A774A1_CLK_S1D2 16
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#define R8A774A1_CLK_S1D4 17
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#define R8A774A1_CLK_S2D1 18
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#define R8A774A1_CLK_S2D2 19
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#define R8A774A1_CLK_S2D4 20
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#define R8A774A1_CLK_S3D1 21
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#define R8A774A1_CLK_S3D2 22
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#define R8A774A1_CLK_S3D4 23
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#define R8A774A1_CLK_LB 24
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#define R8A774A1_CLK_CL 25
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#define R8A774A1_CLK_ZB3 26
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#define R8A774A1_CLK_ZB3D2 27
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#define R8A774A1_CLK_ZB3D4 28
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#define R8A774A1_CLK_CR 29
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#define R8A774A1_CLK_CRD2 30
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#define R8A774A1_CLK_SD0H 31
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#define R8A774A1_CLK_SD0 32
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#define R8A774A1_CLK_SD1H 33
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#define R8A774A1_CLK_SD1 34
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#define R8A774A1_CLK_SD2H 35
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#define R8A774A1_CLK_SD2 36
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#define R8A774A1_CLK_SD3H 37
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#define R8A774A1_CLK_SD3 38
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#define R8A774A1_CLK_SSP2 39
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#define R8A774A1_CLK_SSP1 40
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#define R8A774A1_CLK_SSPRS 41
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#define R8A774A1_CLK_RPC 42
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#define R8A774A1_CLK_RPCD2 43
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#define R8A774A1_CLK_MSO 44
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#define R8A774A1_CLK_CANFD 45
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#define R8A774A1_CLK_HDMI 46
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#define R8A774A1_CLK_CSI0 47
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#define R8A774A1_CLK_CSIREF 48
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#define R8A774A1_CLK_CP 49
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#define R8A774A1_CLK_CPEX 50
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#define R8A774A1_CLK_R 51
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#define R8A774A1_CLK_OSC 52
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#endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */
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33
include/dt-bindings/power/r8a774a1-sysc.h
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33
include/dt-bindings/power/r8a774a1-sysc.h
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A774A1_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A774A1_PD_CA57_CPU0 0
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#define R8A774A1_PD_CA57_CPU1 1
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#define R8A774A1_PD_CA53_CPU0 5
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#define R8A774A1_PD_CA53_CPU1 6
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#define R8A774A1_PD_CA53_CPU2 7
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#define R8A774A1_PD_CA53_CPU3 8
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#define R8A774A1_PD_CA57_SCU 12
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#define R8A774A1_PD_CR7 13
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#define R8A774A1_PD_A3VC 14
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#define R8A774A1_PD_3DG_A 17
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#define R8A774A1_PD_3DG_B 18
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#define R8A774A1_PD_CA53_SCU 21
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#define R8A774A1_PD_A3IR 24
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#define R8A774A1_PD_A2VC0 25
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#define R8A774A1_PD_A2VC1 26
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/* Always-on power area */
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#define R8A774A1_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A774A1_SYSC_H__ */
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