* Patch by Scott McNutt, 21 Oct 2004:
Add support for Nios-II EPCS Controller core. * Patch by Scott McNutt, 20 Oct 2004: Nios-II cleanups: - Add sysid command (Nios-II only). - Locate default exception trampoline at proper offset. - Implement I/O routines (readb, writeb, etc) - Implement do_bootm_linux
This commit is contained in:
wdenk
@@ -29,8 +29,61 @@
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extern unsigned char inb (unsigned char *port);
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extern unsigned short inw (unsigned short *port);
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extern unsigned inl (unsigned port);
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extern void outb (unsigned char val, unsigned char *port);
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extern void outw (unsigned short val, unsigned short *port);
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extern void outl (unsigned val, unsigned port);
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#define readb(addr)\
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({unsigned char val;\
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asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
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#define readw(addr)\
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({unsigned short val;\
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asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
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#define readl(addr)\
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({unsigned long val;\
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asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;})
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#define writeb(addr,val)\
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asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val))
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#define writew(addr,val)\
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asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val))
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#define writel(addr,val)\
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asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val))
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#define inb(addr) readb(addr)
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#define inw(addr) readw(addr)
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#define inl(addr) readl(addr)
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#define outb(addr,val) writeb(addr,val)
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#define outw(addr,val) writew(addr,val)
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#define outl(addr,val) writel(addr,val)
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static inline void insb (unsigned long port, void *dst, unsigned long count)
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{
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unsigned char *p = dst;
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while (count--) *p++ = inb (port);
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}
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static inline void insw (unsigned long port, void *dst, unsigned long count)
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{
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unsigned short *p = dst;
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while (count--) *p++ = inw (port);
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}
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static inline void insl (unsigned long port, void *dst, unsigned long count)
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{
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unsigned long *p = dst;
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while (count--) *p++ = inl (port);
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}
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static inline void outsb (unsigned long port, const void *src, unsigned long count)
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{
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const unsigned char *p = src;
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while (count--) outb (*p++, port);
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}
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static inline void outsw (unsigned long port, const void *src, unsigned long count)
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{
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const unsigned short *p = src;
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while (count--) outw (*p++, port);
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}
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static inline void outsl (unsigned long port, const void *src, unsigned long count)
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{
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const unsigned long *p = src;
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while (count--) outl (*p++, port);
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}
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#endif /* __ASM_NIOS2_IO_H_ */
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@@ -52,7 +52,7 @@
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#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
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#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
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#define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */
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#define CFG_SRAM_SIZE 0x00200000 /* 2 MByte */
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#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
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/*------------------------------------------------------------------------
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* MEMORY ORGANIZATION
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@@ -106,6 +106,14 @@
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#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
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/*------------------------------------------------------------------------
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* EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
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* epcs device access is enabled. The base address is the epcs
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* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
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* The register base is currently at offset 0x400 from the memory base.
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*----------------------------------------------------------------------*/
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#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */
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/*------------------------------------------------------------------------
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* DEBUG
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*----------------------------------------------------------------------*/
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@@ -172,6 +180,36 @@
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CFG_CMD_SAVES )
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#include <cmd_confdefs.h>
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/*------------------------------------------------------------------------
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* COMPACT FLASH
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*----------------------------------------------------------------------*/
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#if (CONFIG_COMMANDS & CFG_CMD_IDE)
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#define CONFIG_IDE_PREINIT /* Implement id_preinit */
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#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
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#define CFG_ATA_BASE_ADDR 0x00900800 /* ATA base addr */
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#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */
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#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */
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#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */
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#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */
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#define CFG_ATA_STRIDE 4 /* Width betwix addrs */
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#define CONFIG_DOS_PARTITION
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/* Board-specific cf regs */
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#define CFG_CF_PRESENT 0x00900880 /* CF Present PIO base */
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#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/
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#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */
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#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */
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/*------------------------------------------------------------------------
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* JFFS2
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*----------------------------------------------------------------------*/
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#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
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#define CFG_JFFS_CUSTOM_PART /* board defined part */
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#endif
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/*------------------------------------------------------------------------
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* MISC
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*----------------------------------------------------------------------*/
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@@ -185,4 +223,7 @@
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#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */
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#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif /* __CONFIG_H */
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71
include/nios2-epcs.h
Normal file
71
include/nios2-epcs.h
Normal file
@@ -0,0 +1,71 @@
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/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*************************************************************************
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* Altera Nios-II EPCS Controller Core interfaces
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************************************************************************/
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#ifndef __NIOS2_EPCS_H__
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#define __NIOS2_EPCS_H__
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typedef struct epcs_devinfo_t {
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const char *name; /* Device name */
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unsigned char id; /* Device silicon id */
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unsigned char size; /* Total size log2(bytes)*/
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unsigned char num_sects; /* Number of sectors */
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unsigned char sz_sect; /* Sector size log2(bytes) */
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unsigned char sz_page; /* Page size log2(bytes) */
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unsigned char prot_mask; /* Protection mask */
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}epcs_devinfo_t;
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/* Returns the devinfo struct if EPCS device is found;
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* NULL otherwise.
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*/
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extern epcs_devinfo_t *epcs_dev_find (void);
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/* Returns the number of bytes used by config data.
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* Negative on error.
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*/
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extern int epcs_cfgsz (void);
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/* Erase sectors 'start' to 'end' - return zero on success
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*/
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extern int epcs_erase (unsigned start, unsigned end);
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/* Read 'cnt' bytes from device offset 'off' into buf at 'addr'
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* Zero return on success
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*/
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extern int epcs_read (ulong addr, ulong off, ulong cnt);
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/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'.
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* Zero return on success
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*/
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extern int epcs_write (ulong addr, ulong off, ulong cnt);
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/* Verify 'cnt' bytes at device offset 'off' comparing with buf
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* at 'addr'. On failure, write first invalid offset to *err.
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* Zero return on success
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*/
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extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err);
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#endif /* __NIOS2_EPCS_H__ */
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@@ -136,37 +136,6 @@ typedef volatile struct nios_spi_t {
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#define NIOS_SPI_IE (1 << 8) /* exception int ena */
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#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */
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/*------------------------------------------------------------------------
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* ASMI
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*----------------------------------------------------------------------*/
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typedef volatile struct nios_asmi_t {
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unsigned rxdata; /* Rx data reg */
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unsigned txdata; /* Tx data reg */
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unsigned status; /* Status reg */
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unsigned control; /* Control reg */
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unsigned reserved;
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unsigned slavesel; /* Slave select */
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unsigned endofpacket; /* End-of-packet reg */
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}nios_asmi_t;
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/* status register */
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#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */
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#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */
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#define NIOS_ASMI_TMT (1 << 5) /* tx empty */
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#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */
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#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */
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#define NIOS_ASMI_E (1 << 8) /* exception */
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#define NIOS_ASMI_EOP (1 << 9) /* eop detected */
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/* control register */
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#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */
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#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */
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#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */
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#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */
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#define NIOS_ASMI_IE (1 << 8) /* exception int ena */
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#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */
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#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */
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/*------------------------------------------------------------------------
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* JTAG UART
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*----------------------------------------------------------------------*/
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