arm: at91: mpddr: allow multiple DDR controllers
The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller. This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10). Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [remove 'new blank line at EOF'] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Andreas Bießmann
parent
8d77576371
commit
0c01c3e876
@@ -251,5 +251,4 @@
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
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#endif
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@@ -259,8 +259,6 @@
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
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#define CONFIG_SPL_MMC_SUPPORT
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@@ -261,8 +261,6 @@
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
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#define CONFIG_SPL_MMC_SUPPORT
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@@ -193,6 +193,4 @@
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#define CONFIG_SYS_MCKR 0x1301
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#define CONFIG_SYS_MCKR_CSS 0x1302
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#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
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#endif
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