arm: at91: mpddr: allow multiple DDR controllers

The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller.
This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[remove 'new blank line at EOF']
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Erik van Luijk
2015-08-13 15:43:18 +02:00
committed by Andreas Bießmann
parent 8d77576371
commit 0c01c3e876
14 changed files with 34 additions and 36 deletions

View File

@@ -251,5 +251,4 @@
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
#endif

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@@ -259,8 +259,6 @@
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
#define CONFIG_SPL_MMC_SUPPORT

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@@ -261,8 +261,6 @@
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
#ifdef CONFIG_SYS_USE_MMC
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
#define CONFIG_SPL_MMC_SUPPORT

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@@ -193,6 +193,4 @@
#define CONFIG_SYS_MCKR 0x1301
#define CONFIG_SYS_MCKR_CSS 0x1302
#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
#endif