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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

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This commit is contained in:
Wolfgang Denk
2008-08-28 00:26:52 +02:00
parent d26b739afe 9cff4448a9
commit 0ba6bfef06
105 changed files with 5613 additions and 1628 deletions
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22
cpu/mpc85xx/Makefile
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@@ -34,14 +34,22 @@ SOBJS = $(SOBJS-y)
COBJS-$(CONFIG_MP) += mp.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
ifneq ($(CONFIG_FSL_DDR3),y)
ifneq ($(CONFIG_FSL_DDR2),y)
ifneq ($(CONFIG_FSL_DDR1),y)
COBJS-y += spd_sdram.o
endif
endif
endif
# supports ddr1
COBJS-$(CONFIG_MPC8540) += ddr-gen1.o
COBJS-$(CONFIG_MPC8560) += ddr-gen1.o
COBJS-$(CONFIG_MPC8541) += ddr-gen1.o
COBJS-$(CONFIG_MPC8555) += ddr-gen1.o
# supports ddr1/2
COBJS-$(CONFIG_MPC8548) += ddr-gen2.o
COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
# supports ddr1/2/3
COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \
$(COBJS-y)

8
cpu/mpc85xx/cpu.c
View File

@@ -36,6 +36,8 @@ DECLARE_GLOBAL_DATA_PTR;
struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(8533, 8533),
CPU_TYPE_ENTRY(8533, 8533_E),
CPU_TYPE_ENTRY(8536, 8536),
CPU_TYPE_ENTRY(8536, 8536_E),
CPU_TYPE_ENTRY(8540, 8540),
CPU_TYPE_ENTRY(8541, 8541),
CPU_TYPE_ENTRY(8541, 8541_E),
@@ -89,6 +91,9 @@ int checkcpu (void)
svr = get_svr();
ver = SVR_SOC_VER(svr);
major = SVR_MAJ(svr);
#ifdef CONFIG_MPC8536
major &= 0x7; /* the msb of this nibble is a mfg code */
#endif
minor = SVR_MIN(svr);
puts("CPU: ");
@@ -154,7 +159,8 @@ int checkcpu (void)
#endif
clkdiv = lcrr & 0x0f;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \
defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536)
/*
* Yes, the entire PQ38 family use the same
* bit-representation for twice the clock divider values.

7
cpu/mpc85xx/cpu_init.c
View File

@@ -37,6 +37,10 @@
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_MPC8536
extern void fsl_serdes_init(void);
#endif
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -240,6 +244,9 @@ void cpu_init_f (void)
/* Config QE ioports */
config_qe_ioports();
#endif
#if defined(CONFIG_MPC8536)
fsl_serdes_init();
#endif
}

120
cpu/mpc85xx/ddr-gen1.c Normal file
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@@ -0,0 +1,120 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
unsigned int i;
volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
return;
}
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i == 0) {
out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs0_config, regs->cs[i].config);
} else if (i == 1) {
out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs1_config, regs->cs[i].config);
} else if (i == 2) {
out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs2_config, regs->cs[i].config);
} else if (i == 3) {
out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs3_config, regs->cs[i].config);
}
}
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
#endif
/*
* 200 painful micro-seconds must elapse between
* the DDR clock setup and the DDR config enable.
*/
udelay(200);
asm volatile("sync;isync");
out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
asm("sync;isync;msync");
udelay(500);
}
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void dma_init(void);
extern uint dma_check(void);
extern int dma_xfer(void *dest, uint count, void *src);
/*
* Initialize all of memory for ECC, then enable errors.
*/
void
ddr_enable_ecc(unsigned int dram_size)
{
uint *p = 0;
uint i = 0;
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
dma_init();
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((unsigned int)p & 0x1f) == 0) {
ppcDcbz((unsigned long) p);
}
*p = (unsigned int)CONFIG_MEM_INIT_VALUE;
if (((unsigned int)p & 0x1c) == 0x1c) {
ppcDcbf((unsigned long) p);
}
}
dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
for (i = 1; i < dram_size / 0x800000; i++) {
dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
}
/*
* Enable errors for ECC.
*/
debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
ddr->err_disable = 0x00000000;
asm("sync;isync;msync");
debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
}
#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */

74
cpu/mpc85xx/ddr-gen2.c Normal file
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@@ -0,0 +1,74 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
unsigned int i;
volatile ccsr_ddr_t *ddr = (void *)CFG_MPC85xx_DDR_ADDR;
if (ctrl_num) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
return;
}
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i == 0) {
out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs0_config, regs->cs[i].config);
} else if (i == 1) {
out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs1_config, regs->cs[i].config);
} else if (i == 2) {
out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs2_config, regs->cs[i].config);
} else if (i == 3) {
out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs3_config, regs->cs[i].config);
}
}
out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
out_be32(&ddr->init_addr, regs->ddr_init_addr);
out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
/*
* 200 painful micro-seconds must elapse between
* the DDR clock setup and the DDR config enable.
*/
udelay(200);
asm volatile("sync;isync");
out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
udelay(10000); /* throttle polling rate */
}
}

105
cpu/mpc85xx/ddr-gen3.c Normal file
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@@ -0,0 +1,105 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_ddr_sdram.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
#endif
void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
unsigned int i;
volatile ccsr_ddr_t *ddr;
switch (ctrl_num) {
case 0:
ddr = (void *)CFG_MPC85xx_DDR_ADDR;
break;
case 1:
ddr = (void *)CFG_MPC85xx_DDR2_ADDR;
break;
default:
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
return;
}
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i == 0) {
out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs0_config, regs->cs[i].config);
out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
} else if (i == 1) {
out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs1_config, regs->cs[i].config);
out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
} else if (i == 2) {
out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs2_config, regs->cs[i].config);
out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
} else if (i == 3) {
out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
out_be32(&ddr->cs3_config, regs->cs[i].config);
out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
}
}
out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
out_be32(&ddr->init_addr, regs->ddr_init_addr);
out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl);
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
/*
* 32-bit workaround for DDR2
* 32_BE
*/
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
&& in_be32(&ddr->sdram_cfg_2) & 0x80000) {
/* set DEBUG_1[31] */
u32 temp = in_be32(&ddr->debug_1);
out_be32(&ddr->debug_1, temp | 1);
}
/*
* 200 painful micro-seconds must elapse between
* the DDR clock setup and the DDR config enable.
*/
udelay(200);
asm volatile("sync;isync");
out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
udelay(10000); /* throttle polling rate */
}
}

109
cpu/mpc85xx/interrupts.c
View File

@@ -31,64 +31,20 @@
#include <watchdog.h>
#include <command.h>
#include <asm/processor.h>
#include <ppc_asm.tmpl>
unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
static __inline__ unsigned long get_msr(void)
{
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr;
}
static __inline__ void set_msr(unsigned long msr)
{
asm volatile("mtmsr %0" : : "r" (msr));
asm volatile("isync");
}
static __inline__ unsigned long get_dec (void)
{
unsigned long val;
asm volatile ("mfdec %0":"=r" (val):);
return val;
}
static __inline__ void set_dec (unsigned long val)
{
if (val)
asm volatile ("mtdec %0"::"r" (val));
}
void enable_interrupts (void)
{
set_msr (get_msr() | MSR_EE);
}
/* returns flag if MSR_EE was set before */
int disable_interrupts (void)
{
ulong msr = get_msr();
set_msr (msr & ~MSR_EE);
return ((msr & MSR_EE) != 0);
}
int interrupt_init (void)
int interrupt_init_cpu(unsigned long *decrementer_count)
{
volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR);
pic->gcr = MPC85xx_PICGCR_RST;
while (pic->gcr & MPC85xx_PICGCR_RST);
while (pic->gcr & MPC85xx_PICGCR_RST)
;
pic->gcr = MPC85xx_PICGCR_M;
decrementer_count = get_tbclk() / CFG_HZ;
*decrementer_count = get_tbclk() / CFG_HZ;
/* PIE is same as DIE, dec interrupt enable */
mtspr(SPRN_TCR, TCR_PIE);
set_dec (decrementer_count);
set_msr (get_msr () | MSR_EE);
#ifdef CONFIG_INTERRUPTS
pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */
@@ -123,9 +79,7 @@ int interrupt_init (void)
return (0);
}
/*
* Install and free a interrupt handler. Not implemented yet.
*/
/* Install and free a interrupt handler. Not implemented yet. */
void
irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
@@ -139,55 +93,16 @@ irq_free_handler(int vec)
return;
}
/****************************************************************************/
volatile ulong timestamp = 0;
/*
* timer_interrupt - gets called when the decrementer overflows,
* with interrupts disabled.
* Trivial implementation - no need to be really accurate.
*/
void timer_interrupt(struct pt_regs *regs)
void timer_interrupt_cpu(struct pt_regs *regs)
{
timestamp++;
set_dec (decrementer_count);
/* PIS is same as DIS, dec interrupt status */
mtspr(SPRN_TSR, TSR_PIS);
#if defined(CONFIG_WATCHDOG)
if ((timestamp % 1000) == 0)
reset_85xx_watchdog();
#endif /* CONFIG_WATCHDOG */
}
void reset_timer (void)
{
timestamp = 0;
}
ulong get_timer (ulong base)
{
return (timestamp - base);
}
void set_timer (ulong t)
{
timestamp = t;
}
#if defined(CONFIG_CMD_IRQ)
/*******************************************************************************
*
* irqinfo - print information about PCI devices,not implemented.
*
*/
int
do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* irqinfo - print information about PCI devices,not implemented. */
int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
printf ("\nInterrupt-unsupported:\n");
return 0;
}
#endif

180
cpu/mpc85xx/mpc8536_serdes.c Normal file
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@@ -0,0 +1,180 @@
/*
* Copyright (C) 2008 Freescale Semicondutor, Inc. All rights reserved.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
/* PORDEVSR register */
#define GUTS_PORDEVSR_OFFS 0xc
#define GUTS_PORDEVSR_SERDES2_IO_SEL 0x38000000
#define GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT 27
/* SerDes CR0 register */
#define FSL_SRDSCR0_OFFS 0x0
#define FSL_SRDSCR0_TXEQA_MASK 0x00007000
#define FSL_SRDSCR0_TXEQA_SGMII 0x00004000
#define FSL_SRDSCR0_TXEQA_SATA 0x00001000
#define FSL_SRDSCR0_TXEQE_MASK 0x00000700
#define FSL_SRDSCR0_TXEQE_SGMII 0x00000400
#define FSL_SRDSCR0_TXEQE_SATA 0x00000100
/* SerDes CR1 register */
#define FSL_SRDSCR1_OFFS 0x4
#define FSL_SRDSCR1_LANEA_MASK 0x80200000
#define FSL_SRDSCR1_LANEA_OFF 0x80200000
#define FSL_SRDSCR1_LANEE_MASK 0x08020000
#define FSL_SRDSCR1_LANEE_OFF 0x08020000
/* SerDes CR2 register */
#define FSL_SRDSCR2_OFFS 0x8
#define FSL_SRDSCR2_EICA_MASK 0x00001f00
#define FSL_SRDSCR2_EICA_SGMII 0x00000400
#define FSL_SRDSCR2_EICA_SATA 0x00001400
#define FSL_SRDSCR2_EICE_MASK 0x0000001f
#define FSL_SRDSCR2_EICE_SGMII 0x00000004
#define FSL_SRDSCR2_EICE_SATA 0x00000014
/* SerDes CR3 register */
#define FSL_SRDSCR3_OFFS 0xc
#define FSL_SRDSCR3_LANEA_MASK 0x3f000700
#define FSL_SRDSCR3_LANEA_SGMII 0x00000000
#define FSL_SRDSCR3_LANEA_SATA 0x15000500
#define FSL_SRDSCR3_LANEE_MASK 0x003f0007
#define FSL_SRDSCR3_LANEE_SGMII 0x00000000
#define FSL_SRDSCR3_LANEE_SATA 0x00150005
void fsl_serdes_init(void)
{
void *guts = (void *)(CFG_MPC85xx_GUTS_ADDR);
void *sd = (void *)CFG_MPC85xx_SERDES2_ADDR;
u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
u32 srds2_io_sel;
u32 tmp;
/* parse the SRDS2_IO_SEL of PORDEVSR */
srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
>> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
switch (srds2_io_sel) {
case 1: /* Lane A - SATA1, Lane E - SATA2 */
/* CR 0 */
tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
tmp |= FSL_SRDSCR0_TXEQA_SATA;
tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
tmp |= FSL_SRDSCR0_TXEQE_SATA;
out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
/* CR 1 */
tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
tmp &= ~FSL_SRDSCR1_LANEA_MASK;
tmp &= ~FSL_SRDSCR1_LANEE_MASK;
out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
/* CR 2 */
tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_EICA_MASK;
tmp |= FSL_SRDSCR2_EICA_SATA;
tmp &= ~FSL_SRDSCR2_EICE_MASK;
tmp |= FSL_SRDSCR2_EICE_SATA;
out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
/* CR 3 */
tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
tmp &= ~FSL_SRDSCR3_LANEA_MASK;
tmp |= FSL_SRDSCR3_LANEA_SATA;
tmp &= ~FSL_SRDSCR3_LANEE_MASK;
tmp |= FSL_SRDSCR3_LANEE_SATA;
out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
break;
case 3: /* Lane A - SATA1, Lane E - disabled */
/* CR 0 */
tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
tmp |= FSL_SRDSCR0_TXEQA_SATA;
out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
/* CR 1 */
tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
tmp &= ~FSL_SRDSCR1_LANEE_MASK;
tmp |= FSL_SRDSCR1_LANEE_OFF;
out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
/* CR 2 */
tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_EICA_MASK;
tmp |= FSL_SRDSCR2_EICA_SATA;
out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
/* CR 3 */
tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
tmp &= ~FSL_SRDSCR3_LANEA_MASK;
tmp |= FSL_SRDSCR3_LANEA_SATA;
out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
break;
case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */
/* CR 0 */
tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
tmp |= FSL_SRDSCR0_TXEQA_SGMII;
tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
tmp |= FSL_SRDSCR0_TXEQE_SGMII;
out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
/* CR 1 */
tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
tmp &= ~FSL_SRDSCR1_LANEA_MASK;
tmp &= ~FSL_SRDSCR1_LANEE_MASK;
out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
/* CR 2 */
tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_EICA_MASK;
tmp |= FSL_SRDSCR2_EICA_SGMII;
tmp &= ~FSL_SRDSCR2_EICE_MASK;
tmp |= FSL_SRDSCR2_EICE_SGMII;
out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
/* CR 3 */
tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
tmp &= ~FSL_SRDSCR3_LANEA_MASK;
tmp |= FSL_SRDSCR3_LANEA_SGMII;
tmp &= ~FSL_SRDSCR3_LANEE_MASK;
tmp |= FSL_SRDSCR3_LANEE_SGMII;
out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
break;
case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */
/* CR 0 */
tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
tmp |= FSL_SRDSCR0_TXEQA_SGMII;
out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
/* CR 1 */
tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
tmp &= ~FSL_SRDSCR1_LANEE_MASK;
tmp |= FSL_SRDSCR1_LANEE_OFF;
out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
/* CR 2 */
tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
tmp &= ~FSL_SRDSCR2_EICA_MASK;
tmp |= FSL_SRDSCR2_EICA_SGMII;
out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
/* CR 3 */
tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
tmp &= ~FSL_SRDSCR3_LANEA_MASK;
tmp |= FSL_SRDSCR3_LANEA_SGMII;
out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
break;
case 7: /* Lane A - disabled, Lane E - disabled */
/* CR 1 */
tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
tmp &= ~FSL_SRDSCR1_LANEA_MASK;
tmp |= FSL_SRDSCR1_LANEA_OFF;
tmp &= ~FSL_SRDSCR1_LANEE_MASK;
tmp |= FSL_SRDSCR1_LANEE_OFF;
out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
break;
default:
break;
}
}

2
cpu/mpc85xx/pci.c
View File

@@ -29,7 +29,7 @@
#include <asm/cpm_85xx.h>
#include <pci.h>
#if defined(CONFIG_PCI)
#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
static struct pci_controller *pci_hose;

1154
cpu/mpc85xx/spd_sdram.c
View File

File diff suppressed because it is too large Load Diff

4
cpu/mpc85xx/speed.c
View File

@@ -110,6 +110,10 @@ int get_clocks (void)
#endif
gd->i2c2_clk = gd->i2c1_clk;
#if defined(CONFIG_MPC8536)
gd->sdhc_clk = gd->bus_clk / 2;
#endif
#if defined(CONFIG_CPM2)
gd->vco_out = 2*sys_info.freqSystemBus;
gd->cpm_clk = gd->vco_out / 2;

64
cpu/mpc85xx/tlb.c
View File

@@ -90,3 +90,67 @@ void init_tlbs(void)
return ;
}
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
unsigned int tlb_size;
unsigned int ram_tlb_index;
unsigned int ram_tlb_address;
/*
* Determine size of each TLB1 entry.
*/
switch (memsize_in_meg) {
case 16:
case 32:
tlb_size = BOOKE_PAGESZ_16M;
break;
case 64:
case 128:
tlb_size = BOOKE_PAGESZ_64M;
break;
case 256:
case 512:
tlb_size = BOOKE_PAGESZ_256M;
break;
case 1024:
case 2048:
if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
tlb_size = BOOKE_PAGESZ_1G;
else
tlb_size = BOOKE_PAGESZ_256M;
break;
default:
puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
" and 2G are supported.\n");
/*
* The memory was not able to be mapped.
* Default to a small size.
*/
tlb_size = BOOKE_PAGESZ_64M;
memsize_in_meg = 64;
break;
}
/*
* Configure DDR TLB1 entries.
* Starting at TLB1 8, use no more than 8 TLB1 entries.
*/
ram_tlb_index = 8;
ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
&& ram_tlb_index < 16) {
set_tlb(1, ram_tlb_address, ram_tlb_address,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, ram_tlb_index, tlb_size, 1);
ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
ram_tlb_index++;
}
/*
* Confirm that the requested amount of memory was mapped.
*/
return memsize_in_meg;
}