Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
75
include/asm-ppc/ppc4xx-isram.h
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75
include/asm-ppc/ppc4xx-isram.h
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/*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _PPC4xx_ISRAM_H_
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#define _PPC4xx_ISRAM_H_
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/*
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* Internal SRAM
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*/
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define ISRAM0_DCR_BASE 0x380
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#else
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#define ISRAM0_DCR_BASE 0x020
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#endif
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#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
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#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
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#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
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#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
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#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
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#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
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#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
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#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
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#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
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#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
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#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define ISRAM1_DCR_BASE 0x0B0
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#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
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#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
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#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */
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#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */
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#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */
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#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */
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#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */
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#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
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#endif /* CONFIG_460EX || CONFIG_460GT */
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/*
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* L2 Cache
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*/
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#if defined (CONFIG_440GX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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#define L2_CACHE_BASE 0x030
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#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
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#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
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#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
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#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
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#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */
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#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
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#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
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#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
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#endif /* CONFIG_440GX */
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#endif /* _PPC4xx_ISRAM_H_ */
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@@ -60,39 +60,24 @@
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#define CONFIG_PREBOOT /* enable preboot variable */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_ITEST
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#undef CONFIG_CMD_LOADB
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_EEPROM
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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@@ -102,7 +87,6 @@
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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@@ -166,15 +150,9 @@
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#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
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#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
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#if 0 /* test-only */
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#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
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#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
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#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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#else
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#define CONFIG_SYS_PCI_PTM2LA 0xef600000 /* point to internal regs */
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#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
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#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
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#endif
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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@@ -215,22 +193,10 @@
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#if 0 /* Use NVRAM for environment variables */
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/*-----------------------------------------------------------------------
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* NVRAM organization
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*/
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#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
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#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
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#else /* Use EEPROM for environment variables */
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#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
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#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars*/
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/* total size of a CAT24WC08 is 1024 bytes */
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#endif
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
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#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
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@@ -327,14 +293,6 @@
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in data cache)
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*/
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#if 0 /* test-only */
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#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
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#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#else
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/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
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#define CONFIG_SYS_TEMP_STACK_OCM 1
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/* On Chip Memory location */
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@@ -346,7 +304,6 @@
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#endif
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/*
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* Internal Definitions
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@@ -102,7 +102,7 @@
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#define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
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(u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
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#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 16k */
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#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
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#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
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#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
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@@ -53,6 +53,13 @@
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#define CONFIG_HOSTNAME katmai
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#include "amcc-common.h"
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/*
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* For booting 256K-paged Linux we should have 16MB of memory
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* for Linux initial memory map
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*/
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#undef CONFIG_SYS_BOOTMAPSZ
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#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#undef CONFIG_SHOW_BOOT_PROGRESS
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@@ -189,6 +196,7 @@
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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@@ -169,18 +169,9 @@
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#define sdr_ecid1 0x0081
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#define sdr_ecid2 0x0082
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#define sdr_jtag 0x00c0
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#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
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#define sdr_ddrdl 0x00e0
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#else
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#define sdr_cfg 0x00e0
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#define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/
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#define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */
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#define SDR_CFG_32BITS 0x00000000 /* 32 bits */
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#define SDR_CFG_64BITS 0x01000000 /* 64 bits */
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#define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
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#define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */
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#define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */
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#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define SDR0_DDRCFG 0x00e0
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#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
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#define sdr_ebc 0x0100
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#define sdr_uart0 0x0120 /* UART0 Config */
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#define sdr_uart1 0x0121 /* UART1 Config */
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@@ -616,45 +607,6 @@
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#endif /* 440EP || 440GR || 440EPX || 440GRX */
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/*-----------------------------------------------------------------------------
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| L2 Cache
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+----------------------------------------------------------------------------*/
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#if defined (CONFIG_440GX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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#define L2_CACHE_BASE 0x030
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#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
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#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
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#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
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#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
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#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
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#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
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#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
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#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
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#endif /* CONFIG_440GX */
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/*-----------------------------------------------------------------------------
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| Internal SRAM
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+----------------------------------------------------------------------------*/
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define ISRAM0_DCR_BASE 0x380
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#else
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#define ISRAM0_DCR_BASE 0x020
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#endif
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#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
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#define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
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#define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
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#define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
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#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
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#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
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#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
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#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
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#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
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#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
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#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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