eaw/u-boot
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge git://git.denx.de/u-boot-marvell

Browse Source 
- Misc dts files sync'ed with Linux version (Chris)
- Orion watchdog fix (Chris)
- kwbimage changed to also support Marvell bin_hdr binary (Chris)
- Add DM support to enable CONFIG_BLK for sata_mv (Stefan)
- Enable BLK on multiple platforms (Stefan)
- Misc minor fixes to AXP theadorable board (Stefan)
- Correct logic for DM_SCSI + unconverted drivers check (stefan)
- Misc changes to kirkwood to enable DM_USB here (Chris)
- Change ahci_mvebu to enable usage on A38x (Baruch)
- Update the kirkwood entry in git-mailrc (Baruch)
- Misc minor improvements (turris, documentation) (Baruch)
- Enhance sata_mv to support Kirkwood as well (Michael)
- Add wdt command (Michael)
- Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG
  board support (Chris)
This commit is contained in:
Tom Rini
2019-04-12 12:34:44 -04:00
parent 40a9546c7b 937cb9d0a6
commit 066cc7c6cf
83 changed files with 2102 additions and 1010 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/dts/Makefile
View File

@@ -138,7 +138,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-388-clearfog.dtb \
armada-388-gp.dtb \
armada-388-helios4.dtb \
armada-385-amc.dtb \
armada-385-db-88f6820-amc.dtb \
armada-385-turris-omnia.dtb \
armada-7040-db.dtb \
armada-7040-db-nand.dtb \
@@ -151,7 +151,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-xp-theadorable.dtb \
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb
armada-385-atl-x530DP.dtb \
armada-xp-db-xc3-24g4xg.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \

133
arch/arm/dts/armada-370-xp.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
*
@@ -8,50 +9,10 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* This file contains the definitions that are common to the Armada
* 370 and Armada XP SoC.
*/
/include/ "skeleton64.dtsi"
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
@@ -86,7 +47,7 @@
pcie-mem-aperture = <0xf8000000 0x7e00000>;
pcie-io-aperture = <0xffe00000 0x100000>;
devbus-bootcs {
devbus_bootcs: devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
@@ -96,7 +57,7 @@
status = "disabled";
};
devbus-cs0 {
devbus_cs0: devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
@@ -106,7 +67,7 @@
status = "disabled";
};
devbus-cs1 {
devbus_cs1: devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
@@ -116,7 +77,7 @@
status = "disabled";
};
devbus-cs2 {
devbus_cs2: devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
@@ -126,7 +87,7 @@
status = "disabled";
};
devbus-cs3 {
devbus_cs3: devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
@@ -141,34 +102,13 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
u-boot,dm-pre-reloc;
rtc@10300 {
rtc: rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <50>;
};
spi0: spi@10600 {
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
#address-cells = <1>;
@@ -235,33 +175,38 @@
msi-controller;
};
coherency-fabric@20200 {
coherencyfab: coherency-fabric@20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21010 0x1c>;
};
timer@20300 {
timer: timer@20300 {
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
};
watchdog@20300 {
watchdog: watchdog@20300 {
reg = <0x20300 0x34>, <0x20704 0x4>;
};
pmsu@22000 {
cpurst: cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x8>;
};
pmsu: pmsu@22000 {
compatible = "marvell,armada-370-pmsu";
reg = <0x22000 0x1000>;
};
usb@50000 {
usb0: usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
usb@51000 {
usb1: usb@51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
@@ -275,7 +220,7 @@
status = "disabled";
};
mdio: mdio {
mdio: mdio@72004 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
@@ -290,7 +235,7 @@
status = "disabled";
};
sata@a0000 {
sata: sata@a0000 {
compatible = "marvell,armada-370-sata";
reg = <0xa0000 0x5000>;
interrupts = <55>;
@@ -309,7 +254,7 @@
status = "disabled";
};
mvsdio@d4000 {
sdio: mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <54>;
@@ -321,6 +266,42 @@
status = "disabled";
};
};
spi0: spi@10600 {
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
<MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
<MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
<MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
<MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
<MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
<MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
<MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
<MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
<MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
<MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
<MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
<MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
<MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
<MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
<MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
<MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
};
clocks {

166
arch/arm/dts/armada-385-amc.dts
View File

@@ -1,166 +0,0 @@
/*
* Device Tree file for Marvell Armada 385 development board
* (DB-88F6820-AMC)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 385 AMC";
compatible = "marvell,a385-amc", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
ethernet1 = &eth2;
i2c0 = &i2c0;
spi1 = &spi1;
};
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
i2c@11000 {
clock-frequency = <100000>;
u-boot,i2c-slave-addr = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
serial@12000 {
/*
* Exported on the micro USB connector CON16
* through an FTDI
*/
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
u-boot,dm-pre-reloc;
};
ethernet@34000 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
usb@58000 {
status = "okay";
};
ethernet@70000 {
pinctrl-names = "default";
/*
* The Reference Clock 0 is used to provide a
* clock to the PHY
*/
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
mdio@72004 {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
};
flash@d0000 {
status = "okay";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
};
pcie {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
};
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
};
};
&refclk {
clock-frequency = <20000000>;
};

4
arch/arm/dts/armada-385-atl-x530-u-boot.dtsi
View File

@@ -11,3 +11,7 @@
&uart0 {
u-boot,dm-pre-reloc;
};
&watchdog {
u-boot,dm-pre-reloc;
};

146
arch/arm/dts/armada-385-db-88f6820-amc.dts Normal file
View File

@@ -0,0 +1,146 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Marvell Armada 385 AMC board
* (DB-88F6820-AMC)
*
* Copyright (C) 2017 Allied Telesis Labs
*/
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 385 AMC";
compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth0;
ethernet1 = &eth2;
i2c0 = &i2c0;
spi1 = &spi1;
};
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
};
};
&i2c0 {
u-boot,i2c-slave-addr = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&uart0 {
/*
* Exported on the micro USB connector CON3
* through an FTDI
*/
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
u-boot,dm-pre-reloc;
};
&eth0 {
pinctrl-names = "default";
/*
* The Reference Clock 0 is used to provide a
* clock to the PHY
*/
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
&eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
&usb0 {
status = "okay";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@1 {
reg = <1>;
};
phy1: ethernet-phy@0 {
reg = <0>;
};
};
&nand_controller {
status = "okay";
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
&pciec {
status = "okay";
};
&pcie1 {
/* Port 0, Lane 0 */
status = "okay";
};
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 0x00100000>;
label = "u-boot";
};
partition@100000 {
reg = <0x00100000 0x00040000>;
label = "u-boot-env";
};
};
};
};
&refclk {
clock-frequency = <20000000>;
};

343
arch/arm/dts/armada-xp-98dx3236.dtsi Normal file
View File

@@ -0,0 +1,343 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell 98dx3236 family SoC
*
* Copyright (C) 2016 Allied Telesis Labs
*
* Contains definitions specific to the 98dx3236 SoC that are not
* common to all Armada XP SoCs.
*/
#include "armada-370-xp.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Marvell 98DX3236 SoC";
compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "marvell,98dx3236-smp";
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
clock-latency = <1000000>;
};
};
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
/*
* 98DX3236 has 1 x1 PCIe unit Gen2.0
*/
pciec: pcie@82000000 {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&mpic>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
};
internal-regs {
sdramc: sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
L2: l2-cache@8000 {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
cache-level = <2>;
cache-unified;
wt-override;
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
/* does not exist */
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
status = "disabled";
};
gpio2: gpio@18180 { /* rework some properties */
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <1>; /* only gpio #32 */
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>;
};
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,mv98dx3236-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
cpuclk: clock-complex@18700 {
#clock-cells = <1>;
compatible = "marvell,mv98dx3236-cpu-clock";
reg = <0x18700 0x24>, <0x1c054 0x10>;
clocks = <&coreclk 1>;
};
corediv-clock@18740 {
status = "disabled";
};
cpu-config@21000 {
compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
};
ethernet@70000 {
compatible = "marvell,armada-xp-neta";
};
ethernet@74000 {
compatible = "marvell,armada-xp-neta";
};
xor1: xor@f0800 {
compatible = "marvell,orion-xor";
reg = <0xf0800 0x100
0xf0a00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor10 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
nand_controller: nand@d0000 {
clocks = <&dfx_coredivclk 0>;
};
xor0: xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
0xF0B00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor00 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
};
dfx: dfx-server@ac000000 {
compatible = "marvell,dfx-server", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
thermal: thermal@f8078 {
compatible = "marvell,armada380-thermal";
reg = <0xf8078 0x4>, <0xf8074 0x4>;
status = "okay";
};
coreclk: mvebu-sar@f8204 {
compatible = "marvell,mv98dx3236-core-clock";
reg = <0xf8204 0x4>;
#clock-cells = <1>;
};
dfx_coredivclk: corediv-clock@f8268 {
compatible = "marvell,mv98dx3236-corediv-clock";
reg = <0xf8268 0xc>;
#clock-cells = <1>;
clocks = <&mainpll>;
clock-output-names = "nand";
};
};
switch: switch@a8000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
pp0: packet-processor@0 {
compatible = "marvell,prestera-98dx3236", "marvell,prestera";
reg = <0 0x4000000>;
interrupts = <33>, <34>, <35>;
dfx = <&dfx>;
};
};
};
clocks {
/* 25 MHz reference crystal */
refclk: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
};
&i2c0 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
&mpic {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
&rtc {
status = "disabled";
};
&timer {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&watchdog {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&cpurst {
reg = <0x20800 0x20>;
};
&usb0 {
clocks = <&gateclk 18>;
};
&usb1 {
clocks = <&gateclk 19>;
};
&pinctrl {
compatible = "marvell,98dx3236-pinctrl";
nand_pins: nand-pins {
marvell,pins = "mpp20", "mpp21", "mpp22",
"mpp23", "mpp24", "mpp25",
"mpp26", "mpp27", "mpp28",
"mpp29", "mpp30";
marvell,function = "dev";
};
nand_rb: nand-rb {
marvell,pins = "mpp19";
marvell,function = "nand";
};
spi0_pins: spi0-pins {
marvell,pins = "mpp0", "mpp1",
"mpp2", "mpp3";
marvell,function = "spi0";
};
};
&spi0 {
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
};
&sdio {
status = "disabled";
};

39
arch/arm/dts/armada-xp-98dx3336.dtsi Normal file
View File

@@ -0,0 +1,39 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell 98dx3336 family SoC
*
* Copyright (C) 2016 Allied Telesis Labs
*
* Contains definitions specific to the 98dx3236 SoC that are not
* common to all Armada XP SoCs.
*/
#include "armada-xp-98dx3236.dtsi"
/ {
model = "Marvell 98DX3336 SoC";
compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
cpus {
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
clock-latency = <1000000>;
};
};
soc {
internal-regs {
resume@20980 {
compatible = "marvell,98dx3336-resume-ctrl";
reg = <0x20980 0x10>;
};
};
};
};
&pp0 {
compatible = "marvell,prestera-98dx3336", "marvell,prestera";
};

54
arch/arm/dts/armada-xp-98dx4251.dtsi Normal file
View File

@@ -0,0 +1,54 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell 98dx4521 family SoC
*
* Copyright (C) 2016 Allied Telesis Labs
*
* Contains definitions specific to the 98dx4521 SoC that are not
* common to all Armada XP SoCs.
*/
#include "armada-xp-98dx3236.dtsi"
/ {
model = "Marvell 98DX4251 SoC";
compatible = "marvell,armadaxp-98dx4251", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
cpus {
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
clock-latency = <1000000>;
};
};
soc {
internal-regs {
resume@20980 {
compatible = "marvell,98dx3336-resume-ctrl";
reg = <0x20980 0x10>;
};
};
};
};
&sdio {
status = "okay";
};
&pinctrl {
compatible = "marvell,98dx4251-pinctrl";
sdio_pins: sdio-pins {
marvell,pins = "mpp5", "mpp6", "mpp7",
"mpp8", "mpp9", "mpp10";
marvell,function = "sd0";
};
};
&pp0 {
compatible = "marvell,prestera-98dx4251", "marvell,prestera";
interrupts = <33>, <34>, <35>, <36>;
};

24
arch/arm/dts/armada-xp-db-xc3-24g4xg-u-boot.dtsi Normal file
View File

@@ -0,0 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
&uart0 {
u-boot,dm-pre-reloc;
};
&nand_controller {
compatible="marvell,mvebu-pxa3xx-nand";
status = "okay";
label = "pxa3xx_nand-0";
nand-rb = <0>;
marvell,nand-keep-config;
nand-on-flash-bbt;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
&spi0 {
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
};
};

110
arch/arm/dts/armada-xp-db-xc3-24g4xg.dts Normal file
View File

@@ -0,0 +1,110 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for DB-XC3-24G4XG board
*
* Copyright (C) 2016 Allied Telesis Labs
*
* Based on armada-xp-db.dts
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
* boards were delivered with an older version of the bootloader that
* left internal registers mapped at 0xd0000000. If you are in this
* situation, you should either update your bootloader (preferred
* solution) or the below Device Tree should be adjusted.
*/
/dts-v1/;
#include "armada-xp-98dx3336.dtsi"
#include "armada-xp-db-xc3-24g4xg-u-boot.dtsi"
/ {
model = "DB-XC3-24G4XG";
compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
chosen {
stdout-path = "serial0:115200n8";
bootargs = "console=ttyS0,115200 earlyprintk";
};
aliases {
spi0 = &spi0;
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1 GB */
};
};
&L2 {
arm,parity-enable;
marvell,ecc-enable;
};
&devbus_bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <16>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&i2c0 {
clock-frequency = <100000>;
status = "okay";
};
&usb0 {
status = "okay";
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
m25p,fast-read;
partition@u-boot {
reg = <0x00000000 0x00100000>;
label = "u-boot";
};
partition@u-boot-env {
reg = <0x00100000 0x00040000>;
label = "u-boot-env";
};
partition@unused {
reg = <0x00140000 0x00ec0000>;
label = "unused";
};
};
};

167
arch/arm/dts/armada-xp-gp.dts
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Marvell Armada XP development board
* (DB-MV784MP-GP)
@@ -8,44 +9,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the default
* 0xd0000000). The 0xf1000000 is the default used by the recent,
@@ -68,11 +31,7 @@
stdout-path = "serial0:115200n8";
};
aliases {
spi0 = &spi0;
};
memory {
memory@0 {
device_type = "memory";
/*
* 8 GB of plug-in RAM modules by default.The amount
@@ -98,7 +57,10 @@
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
devbus-bootcs {
status = "okay";
@@ -128,31 +90,9 @@
};
};
pcie-controller {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
status = "okay";
u-boot,dm-pre-reloc;
};
serial@12100 {
status = "okay";
@@ -177,43 +117,33 @@
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <16>;
};
phy1: ethernet-phy@1 {
reg = <17>;
};
phy2: ethernet-phy@2 {
reg = <18>;
};
phy3: ethernet-phy@3 {
reg = <19>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "qsgmii";
buffer-manager = <&bm>;
bm,pool-long = <0>;
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "qsgmii";
buffer-manager = <&bm>;
bm,pool-long = <1>;
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "qsgmii";
buffer-manager = <&bm>;
bm,pool-long = <2>;
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "qsgmii";
buffer-manager = <&bm>;
bm,pool-long = <3>;
};
/* Front-side USB slot */
@@ -226,27 +156,72 @@
status = "okay";
};
spi0: spi@10600 {
bm@c0000 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
nand@d0000 {
status = "okay";
label = "pxa3xx_nand-0";
num-cs = <1>;
marvell,nand-keep-config;
marvell,nand-enable-arbiter;
nand-on-flash-bbt;
};
};
bm-bppi {
status = "okay";
};
};
};
&pciec {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@a,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 {
reg = <16>;
};
phy1: ethernet-phy@1 {
reg = <17>;
};
phy2: ethernet-phy@2 {
reg = <18>;
};
phy3: ethernet-phy@3 {
reg = <19>;
};
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};

24
arch/arm/dts/armada-xp-maxbcm.dts
View File

@@ -225,18 +225,6 @@
status = "okay";
};
spi0: spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
nand@d0000 {
status = "okay";
num-cs = <1>;
@@ -247,3 +235,15 @@
};
};
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};

55
arch/arm/dts/armada-xp-mv78230.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Contains definitions specific to the Armada XP MV78230 SoC that are not
* common to all Armada XP SoCs.
*/
@@ -207,25 +170,33 @@
internal-regs {
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18100 0x40>, <0x181c0 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>;
clocks = <&coreclk 0>;
};
};
};

58
arch/arm/dts/armada-xp-mv78260.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Contains definitions specific to the Armada XP MV78260 SoC that are not
* common to all Armada XP SoCs.
*/
@@ -294,29 +257,38 @@
internal-regs {
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18100 0x40>, <0x181c0 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;

58
arch/arm/dts/armada-xp-mv78460.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -5,44 +6,6 @@
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Contains definitions specific to the Armada XP MV78460 SoC that are not
* common to all Armada XP SoCs.
*/
@@ -333,29 +296,38 @@
internal-regs {
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18100 0x40>, <0x181c0 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
clocks = <&coreclk 0>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18140 0x40>, <0x181c8 0x08>;
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
clocks = <&coreclk 0>;
};
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
compatible = "marvell,armada-370-gpio",
"marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;

199
arch/arm/dts/armada-xp-synology-ds414.dts
View File

@@ -1,13 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree file for Synology DS414
*
* Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Note: this Device Tree assumes that the bootloader has remapped the
* internal registers to 0xf1000000 (instead of the old 0xd0000000).
* The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
@@ -42,36 +38,16 @@
spi0 = &spi0;
};
memory {
memory@0 {
device_type = "memory";
reg = <0 0x00000000 0 0x40000000>; /* 1GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/*
* Connected to Marvell 88SX7042 SATA-II controller
* handling the four disks.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/*
* Connected to EtronTech EJ168A XHCI controller
* providing the two rear USB 3.0 ports.
*/
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
internal-regs {
@@ -80,64 +56,6 @@
status = "disabled";
};
spi0: spi@10600 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
/*
* Warning!
*
* Synology u-boot uses its compiled-in environment
* and it seems Synology did not care to change u-boot
* default configuration in order to allow saving a
* modified environment at a sensible location. So,
* if you do a 'saveenv' under u-boot, your modified
* environment will be saved at 1MB after the start
* of the flash, i.e. in the middle of the uImage.
* For that reason, it is strongly advised not to
* change the default environment, unless you know
* what you are doing.
*/
partition@00000000 { /* u-boot */
label = "RedBoot";
reg = <0x00000000 0x000d0000>; /* 832KB */
};
partition@000c0000 { /* uImage */
label = "zImage";
reg = <0x000d0000 0x002d0000>; /* 2880KB */
};
partition@003a0000 { /* uInitramfs */
label = "rd.gz";
reg = <0x003a0000 0x00430000>; /* 4250KB */
};
partition@007d0000 { /* MAC address and serial number */
label = "vendor";
reg = <0x007d0000 0x00010000>; /* 64KB */
};
partition@007e0000 {
label = "RedBoot config";
reg = <0x007e0000 0x00010000>; /* 64KB */
};
partition@007f0000 {
label = "FIS directory";
reg = <0x007f0000 0x00010000>; /* 64KB */
};
};
};
i2c@11000 {
clock-frequency = <400000>;
status = "okay";
@@ -179,16 +97,6 @@
status = "okay";
};
mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
pinctrl-0 = <&ge0_rgmii_pins>;
@@ -215,7 +123,7 @@
&sata3_pwr_pin &sata4_pwr_pin>;
pinctrl-names = "default";
sata1_regulator: sata1-regulator {
sata1_regulator: sata1-regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "SATA1 Power";
@@ -228,7 +136,7 @@
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
sata2_regulator: sata2-regulator {
sata2_regulator: sata2-regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "SATA2 Power";
@@ -241,7 +149,7 @@
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
sata3_regulator: sata3-regulator {
sata3_regulator: sata3-regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "SATA3 Power";
@@ -254,7 +162,7 @@
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
sata4_regulator: sata4-regulator {
sata4_regulator: sata4-regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "SATA4 Power";
@@ -269,6 +177,39 @@
};
};
&pciec {
status = "okay";
/*
* Connected to Marvell 88SX7042 SATA-II controller
* handling the four disks.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/*
* Connected to EtronTech EJ168A XHCI controller
* providing the two rear USB 3.0 ports.
*/
pcie@5,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
&mdio {
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
reg = <0>;
};
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
reg = <1>;
};
};
&pinctrl {
sata1_pwr_pin: sata1-pwr-pin {
marvell,pins = "mpp42";
@@ -335,3 +276,59 @@
marvell,function = "gpio";
};
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q064", "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
/*
* Warning!
*
* Synology u-boot uses its compiled-in environment
* and it seems Synology did not care to change u-boot
* default configuration in order to allow saving a
* modified environment at a sensible location. So,
* if you do a 'saveenv' under u-boot, your modified
* environment will be saved at 1MB after the start
* of the flash, i.e. in the middle of the uImage.
* For that reason, it is strongly advised not to
* change the default environment, unless you know
* what you are doing.
*/
partition@0 { /* u-boot */
label = "RedBoot";
reg = <0x00000000 0x000d0000>; /* 832KB */
};
partition@c0000 { /* uImage */
label = "zImage";
reg = <0x000d0000 0x002d0000>; /* 2880KB */
};
partition@3a0000 { /* uInitramfs */
label = "rd.gz";
reg = <0x003a0000 0x00430000>; /* 4250KB */
};
partition@7d0000 { /* MAC address and serial number */
label = "vendor";
reg = <0x007d0000 0x00010000>; /* 64KB */
};
partition@7e0000 {
label = "RedBoot config";
reg = <0x007e0000 0x00010000>; /* 64KB */
};
partition@7f0000 {
label = "FIS directory";
reg = <0x007f0000 0x00010000>; /* 64KB */
};
};
};

69
arch/arm/dts/armada-xp-theadorable.dts
View File

@@ -126,40 +126,6 @@
status = "okay";
};
spi0: spi@10600 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
fpga@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
reg = <1>; /* Chip select 1 */
spi-max-frequency = <27777777>;
};
};
spi1: spi@10680 {
status = "okay";
fpga@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
};
/* The LCD controller is only used on this board */
lcd0: lcd-controller@e0000 {
compatible = "marvell,armada-xp-lcd";
@@ -188,6 +154,41 @@
};
};
&spi0 {
status = "okay";
u-boot,dm-pre-reloc;
spi-flash@0 {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13", "jedec,spi-nor", "spi-flash";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
fpga@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
reg = <1>; /* Chip select 1 */
spi-max-frequency = <27777777>;
};
};
&spi1 {
status = "okay";
fpga@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-generic-device";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <27777777>;
};
};
&pciec {
status = "okay";

214
arch/arm/dts/armada-xp.dtsi
View File

@@ -1,3 +1,4 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Device Tree Include file for Marvell Armada XP family SoC
*
@@ -8,44 +9,6 @@
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Ben Dooks <ben.dooks@codethink.co.uk>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Contains definitions specific to the Armada XP SoC that are not
* common to all Armada SoCs.
*/
@@ -53,6 +16,9 @@
#include "armada-370-xp.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
@@ -71,12 +37,12 @@
};
internal-regs {
sdramc@1400 {
sdramc: sdramc@1400 {
compatible = "marvell,armada-xp-sdram-controller";
reg = <0x1400 0x500>;
};
L2: l2-cache {
L2: l2-cache@8000 {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
@@ -85,29 +51,6 @@
wt-override;
};
spi0: spi@10600 {
compatible = "marvell,armada-xp-spi",
"marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
};
spi1: spi@10680 {
compatible = "marvell,armada-xp-spi",
"marvell,orion-spi";
};
i2c0: i2c@11000 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
i2c1: i2c@11100 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
uart2: serial@12200 {
compatible = "snps,dw-apb-uart";
pinctrl-0 = <&uart2_pins>;
@@ -132,7 +75,7 @@
status = "disabled";
};
system-controller@18200 {
systemc: system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>;
};
@@ -150,7 +93,7 @@
#clock-cells = <1>;
};
thermal@182b0 {
thermal: thermal@182b0 {
compatible = "marvell,armadaxp-thermal";
reg = <0x182b0 0x4
0x184d0 0x4>;
@@ -164,25 +107,9 @@
clocks = <&coreclk 1>;
};
interrupt-controller@20a00 {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
timer@20300 {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
watchdog@20300 {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
cpurst@20800 {
compatible = "marvell,armada-370-cpu-reset";
reg = <0x20800 0x20>;
cpu-config@21000 {
compatible = "marvell,armada-xp-cpu-config";
reg = <0x21000 0x8>;
};
eth2: ethernet@30000 {
@@ -193,15 +120,7 @@
status = "disabled";
};
usb@50000 {
clocks = <&gateclk 18>;
};
usb@51000 {
clocks = <&gateclk 19>;
};
usb@52000 {
usb2: usb@52000 {
compatible = "marvell,orion-ehci";
reg = <0x52000 0x500>;
interrupts = <47>;
@@ -209,7 +128,7 @@
status = "disabled";
};
xor@60900 {
xor1: xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
@@ -237,7 +156,27 @@
compatible = "marvell,armada-xp-neta";
};
xor@f0900 {
cesa: crypto@90000 {
compatible = "marvell,armada-xp-crypto";
reg = <0x90000 0x10000>;
reg-names = "regs";
interrupts = <48>, <49>;
clocks = <&gateclk 23>, <&gateclk 23>;
clock-names = "cesa0", "cesa1";
marvell,crypto-srams = <&crypto_sram0>,
<&crypto_sram1>;
marvell,crypto-sram-size = <0x800>;
};
bm: bm@c0000 {
compatible = "marvell,armada-380-neta-bm";
reg = <0xc0000 0xac>;
clocks = <&gateclk 13>;
internal-mem = <&bm_bppi>;
status = "disabled";
};
xor0: xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
0xF0B00 0x100>;
@@ -257,6 +196,35 @@
};
};
};
crypto_sram0: sa-sram0 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
};
crypto_sram1: sa-sram1 {
compatible = "mmio-sram";
reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
clocks = <&gateclk 23>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
bm_bppi: bm-bppi {
compatible = "mmio-sram";
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&gateclk 13>;
no-memory-wc;
status = "disabled";
};
};
clocks {
@@ -269,6 +237,44 @@
};
};
&i2c0 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11000 0x100>;
};
&i2c1 {
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
reg = <0x11100 0x100>;
};
&mpic {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
&timer {
compatible = "marvell,armada-xp-timer";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&watchdog {
compatible = "marvell,armada-xp-wdt";
clocks = <&coreclk 2>, <&refclk>;
clock-names = "nbclk", "fixed";
};
&cpurst {
reg = <0x20800 0x20>;
};
&usb0 {
clocks = <&gateclk 18>;
};
&usb1 {
clocks = <&gateclk 19>;
};
&pinctrl {
ge0_gmii_pins: ge0-gmii-pins {
marvell,pins =
@@ -309,6 +315,12 @@
marvell,function = "spi0";
};
spi1_pins: spi1-pins {
marvell,pins = "mpp13", "mpp14",
"mpp16", "mpp17";
marvell,function = "spi1";
};
uart2_pins: uart2-pins {
marvell,pins = "mpp42", "mpp43";
marvell,function = "uart2";
@@ -319,3 +331,15 @@
marvell,function = "uart3";
};
};
&spi0 {
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
};
&spi1 {
compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
pinctrl-0 = <&spi1_pins>;
pinctrl-names = "default";
};

74
arch/arm/mach-kirkwood/cpu.c
View File

@@ -46,69 +46,31 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval)
return (0x0000ffff & j);
}
/*
* kw_config_adr_windows - Configure address Windows
*
* There are 8 address windows supported by Kirkwood Soc to addess different
* devices. Each window can be configured for size, BAR and remap addr
* Below configuration is standard for most of the cases
*
* If remap function not used, remap_lo must be set as base
*
* Reference Documentation:
* Mbus-L to Mbus Bridge Registers Configuration.
* (Sec 25.1 and 25.3 of Datasheet)
*/
int kw_config_adr_windows(void)
{
struct kwwin_registers *winregs =
(struct kwwin_registers *)KW_CPU_WIN_BASE;
static struct mbus_win windows[] = {
/* Window 0: PCIE MEM address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
writel(0x0, &winregs[0].remap_hi);
{ KW_DEFADR_PCI_MEM, 1024 * 1024 * 256,
KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM },
/* Window 1: PCIE IO address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
writel(KW_DEFADR_PCI_IO, &winregs[1].base);
writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
writel(0x0, &winregs[1].remap_hi);
{ KW_DEFADR_PCI_IO, 1024 * 64,
KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO },
/* Window 2: NAND Flash address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
writel(KW_DEFADR_NANDF, &winregs[2].base);
writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
writel(0x0, &winregs[2].remap_hi);
{ KW_DEFADR_NANDF, 1024 * 1024 * 128,
KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH },
/* Window 3: SPI Flash address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
writel(KW_DEFADR_SPIF, &winregs[3].base);
writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
writel(0x0, &winregs[3].remap_hi);
{ KW_DEFADR_SPIF, 1024 * 1024 * 128,
KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH },
/* Window 4: BOOT Memory address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
writel(KW_DEFADR_BOOTROM, &winregs[4].base);
{ KW_DEFADR_BOOTROM, 1024 * 1024 * 128,
KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM },
/* Window 5: Security SRAM address space */
writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
writel(KW_DEFADR_SASRAM, &winregs[5].base);
/* Window 6-7: Disabled */
writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
return 0;
}
{ KW_DEFADR_SASRAM, 1024 * 64,
KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM },
};
/*
* SYSRSTn Duration Counter Support
@@ -221,15 +183,13 @@ int arch_cpu_init(void)
struct kwcpu_registers *cpureg =
(struct kwcpu_registers *)KW_CPU_REG_BASE;
/* Linux expects` the internal registers to be at 0xf1000000 */
/* Linux expects the internal registers to be at 0xf1000000 */
writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
/* Enable and invalidate L2 cache in write through mode */
writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
invalidate_l2_cache();
kw_config_adr_windows();
#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
/*
* Configures the I/O voltage of the pads connected to Egigabit
@@ -291,11 +251,13 @@ int arch_misc_init(void)
temp |= (1 << 22);
writefr_extra_feature_reg(temp);
icache_enable();
/* Change reset vector to address 0x0 */
temp = get_cr();
set_cr(temp & ~CR_V);
/* Configure mbus windows */
mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
/* checks and execute resset to factory event */
kw_sysrst_check();

13
arch/arm/mach-kirkwood/include/mach/cpu.h
View File

@@ -63,12 +63,18 @@ enum kwcpu_attrib {
*/
#define KW_DEFADR_PCI_MEM 0x90000000
#define KW_DEFADR_PCI_IO 0xC0000000
#define KW_DEFADR_PCI_IO_REMAP 0xC0000000
#define KW_DEFADR_SASRAM 0xC8010000
#define KW_DEFADR_NANDF 0xD8000000
#define KW_DEFADR_SPIF 0xE8000000
#define KW_DEFADR_BOOTROM 0xF8000000
struct mbus_win {
u32 base;
u32 size;
u8 target;
u8 attr;
};
/*
* read feroceon/sheeva core extra feature register
* using co-proc instruction
@@ -135,13 +141,16 @@ struct kwgpio_registers {
u32 irq_level;
};
/* Needed for dynamic (board-specific) mbus configuration */
extern struct mvebu_mbus_state mbus_state;
/*
* functions
*/
unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
int kw_config_adr_windows(void);
int mvebu_mbus_probe(struct mbus_win windows[], int count);
void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,

2
arch/arm/mach-kirkwood/include/mach/soc.h
View File

@@ -31,7 +31,7 @@
#define KW_RTC_BASE (KW_REGISTER(0x10300))
#define KW_NANDF_BASE (KW_REGISTER(0x10418))
#define MVEBU_SPI_BASE (KW_REGISTER(0x10600))
#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000))
#define MVEBU_CPU_WIN_BASE (KW_REGISTER(0x20000))
#define KW_CPU_REG_BASE (KW_REGISTER(0x20100))
#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300))
#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))

34
arch/arm/mach-mvebu/Kconfig
View File

@@ -9,10 +9,10 @@ config ARMADA_32BIT
select ARCH_MISC_INIT
select BOARD_EARLY_INIT_F
select CPU_V7A
select SPL_DM
select SPL_DM_SEQ_ALIAS
select SPL_OF_CONTROL
select SPL_SIMPLE_BUS
select SPL_DM if SPL
select SPL_DM_SEQ_ALIAS if SPL
select SPL_OF_CONTROL if SPL
select SPL_SIMPLE_BUS if SPL
select SUPPORT_SPL
config ARMADA_64BIT
@@ -46,7 +46,7 @@ config ARMADA_8K
# Armada PLL frequency (used for NAND clock generation)
config SYS_MVEBU_PLL_CLOCK
int
default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K
default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K || ARMADA_MSYS
default "1000000000" if ARMADA_38X || ARMADA_375
# Armada XP/38x SoC types...
@@ -63,6 +63,22 @@ config MV78460
bool
select ARMADA_XP
config ARMADA_MSYS
bool
select ARMADA_32BIT
config 98DX4251
bool
select ARMADA_MSYS
config 98DX3336
bool
select ARMADA_MSYS
config 98DX3236
bool
select ARMADA_MSYS
config 88F6820
bool
select ARMADA_38X
@@ -136,6 +152,10 @@ config TARGET_X530
bool "Support Allied Telesis x530"
select 88F6820
config TARGET_DB_XC3_24G4XG
bool "Support DB-XC3-24G4XG"
select 98DX3336
endchoice
config SYS_BOARD
@@ -154,6 +174,7 @@ config SYS_BOARD
default "theadorable" if TARGET_THEADORABLE
default "a38x" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
@@ -171,6 +192,7 @@ config SYS_CONFIG_NAME
default "turris_mox" if TARGET_TURRIS_MOX
default "controlcenterdc" if TARGET_CONTROLCENTERDC
default "x530" if TARGET_X530
default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
@@ -179,6 +201,8 @@ config SYS_VENDOR
default "Marvell" if TARGET_DB_88F6820_GP
default "Marvell" if TARGET_DB_88F6820_AMC
default "Marvell" if TARGET_MVEBU_ARMADA_8K
default "Marvell" if TARGET_DB_XC3_24G4XG
default "Marvell" if TARGET_MVEBU_DB_88F7040
default "solidrun" if TARGET_CLEARFOG
default "kobol" if TARGET_HELIOS4
default "Synology" if TARGET_DS414

2
arch/arm/mach-mvebu/Makefile
View File

@@ -14,6 +14,7 @@ ifdef CONFIG_KIRKWOOD
obj-y = dram.o
obj-y += gpio.o
obj-y += mbus.o
obj-y += timer.o
else # CONFIG_KIRKWOOD
@@ -24,6 +25,7 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_MVEBU_EFUSE) += efuse.o
extra-y += kwbimage.cfg

46
arch/arm/mach-mvebu/cpu.c
View File

@@ -23,6 +23,11 @@ static struct mbus_win windows[] = {
/* NOR */
{ MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
#ifdef CONFIG_ARMADA_MSYS
/* DFX */
{ MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 },
#endif
};
void lowlevel_init(void)
@@ -121,6 +126,14 @@ static const struct sar_freq_modes sar_freq_tab[] = {
{ 0x13, 0x0, 2000, 1000, 933 },
{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
};
#elif defined(CONFIG_ARMADA_MSYS)
static const struct sar_freq_modes sar_freq_tab[] = {
{ 0x0, 0x0, 400, 400, 400 },
{ 0x2, 0x0, 667, 333, 667 },
{ 0x3, 0x0, 800, 400, 800 },
{ 0x5, 0x0, 800, 400, 800 },
{ 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */
};
#else
/* SAR frequency values for Armada XP */
static const struct sar_freq_modes sar_freq_tab[] = {
@@ -144,7 +157,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
u32 freq;
int i;
#if defined(CONFIG_ARMADA_375)
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS)
val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */
#else
val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
@@ -160,7 +173,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq)
#endif
for (i = 0; sar_freq_tab[i].val != 0xff; i++) {
if (sar_freq_tab[i].val == freq) {
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X)
#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
*sar_freq = sar_freq_tab[i];
return;
#else
@@ -270,6 +283,20 @@ int print_cpuinfo(void)
}
}
if (mvebu_soc_family() == MVEBU_SOC_MSYS) {
switch (revid) {
case 3:
puts("A0");
break;
case 4:
puts("A1");
break;
default:
printf("?? (%x)", revid);
break;
}
}
get_sar_freq(&sar_freq);
printf(" at %d MHz\n", sar_freq.p_clk);
@@ -472,6 +499,8 @@ u32 mvebu_get_nand_clock(void)
if (mvebu_soc_family() == MVEBU_SOC_A38X)
reg = MVEBU_DFX_DIV_CLK_CTRL(1);
else if (mvebu_soc_family() == MVEBU_SOC_MSYS)
reg = MVEBU_DFX_DIV_CLK_CTRL(8);
else
reg = MVEBU_CORE_DIV_CLK_CTRL(1);
@@ -501,7 +530,6 @@ int board_mmc_init(bd_t *bis)
}
#endif
#ifdef CONFIG_SCSI_AHCI_PLAT
#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
@@ -545,11 +573,19 @@ static void ahci_mvebu_regret_option(void __iomem *base)
writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
}
int board_ahci_enable(void)
{
ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
return 0;
}
#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
printf("MVEBU SATA INIT\n");
ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
board_ahci_enable();
ahci_init((void __iomem *)MVEBU_SATA0_BASE);
}
#endif

2
arch/arm/mach-mvebu/include/mach/config.h
View File

@@ -17,7 +17,7 @@
#include <asm/arch/soc.h>
#if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \
|| defined(CONFIG_ARMADA_38X)
|| defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS)
/*
* Set this for the common xor register definitions needed in dram.c
* for A38x as well here.

3
arch/arm/mach-mvebu/include/mach/cpu.h
View File

@@ -34,6 +34,7 @@ enum cpu_target {
CPU_TARGET_PCIE02 = 0x4,
CPU_TARGET_ETH01 = 0x7,
CPU_TARGET_PCIE13 = 0x8,
CPU_TARGET_DFX = 0x8,
CPU_TARGET_SASRAM = 0x9,
CPU_TARGET_SATA01 = 0xa, /* A38X */
CPU_TARGET_NAND = 0xd,
@@ -79,6 +80,8 @@ enum {
#define MBUS_PCI_IO_SIZE (64 << 10)
#define MBUS_SPI_BASE 0xF4000000
#define MBUS_SPI_SIZE (8 << 20)
#define MBUS_DFX_BASE 0xF6000000
#define MBUS_DFX_SIZE (1 << 20)
#define MBUS_BOOTROM_BASE 0xF8000000
#define MBUS_BOOTROM_SIZE (8 << 20)

31
arch/arm/mach-mvebu/include/mach/soc.h
View File

@@ -76,7 +76,11 @@
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
#ifdef CONFIG_ARMADA_MSYS
#define MVEBU_DFX_BASE (MBUS_DFX_BASE)
#else
#define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000))
#endif
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN (1 << 8)
@@ -96,9 +100,20 @@
#define SPI_PUP_EN BIT(5)
#define MVEBU_CORE_DIV_CLK_CTRL(i) (MVEBU_CLOCK_BASE + ((i) * 0x8))
#ifdef CONFIG_ARMADA_MSYS
#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0xf8000 + 0x250 + ((i) * 0x4))
#define NAND_ECC_DIVCKL_RATIO_OFFS 6
#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
#else
#define MVEBU_DFX_DIV_CLK_CTRL(i) (MVEBU_DFX_BASE + 0x250 + ((i) * 0x4))
#endif
#ifdef CONFIG_ARMADA_MSYS
#define NAND_ECC_DIVCKL_RATIO_OFFS 6
#define NAND_ECC_DIVCKL_RATIO_MASK (0xF << NAND_ECC_DIVCKL_RATIO_OFFS)
#else
#define NAND_ECC_DIVCKL_RATIO_OFFS 8
#define NAND_ECC_DIVCKL_RATIO_MASK (0x3F << NAND_ECC_DIVCKL_RATIO_OFFS)
#endif
#define SDRAM_MAX_CS 4
#define SDRAM_ADDR_MASK 0xFF000000
@@ -149,6 +164,22 @@
#define BOOT_FROM_SPI 0x32
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204)
#define SAR_CPU_FREQ_OFFS 18
#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
#define SAR_BOOT_DEVICE_OFFS 11
#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS)
#define BOOT_DEV_SEL_OFFS 11
#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS)
#define BOOT_FROM_NAND 0x1
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
#else
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))

9
arch/arm/mach-mvebu/mbus.c
View File

@@ -344,6 +344,11 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
}
}
mbus_dram_info.num_cs = cs;
#if defined(CONFIG_ARMADA_MSYS)
/* Disable MBUS Err Prop - in order to avoid data aborts */
clrbits_le32(mbus->mbuswins_base + 0x200, BIT(8));
#endif
}
static const struct mvebu_mbus_soc_data
@@ -405,6 +410,7 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size)
return 0;
}
#ifndef CONFIG_KIRKWOOD
static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus,
phys_addr_t *base)
{
@@ -451,6 +457,7 @@ static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus)
val = (size / (64 << 10)) - 1;
writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG);
}
#endif
int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
u32 base, u32 size, u8 target, u8 attr)
@@ -471,12 +478,14 @@ int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
return -ENOMEM;
}
#ifndef CONFIG_KIRKWOOD
/*
* Re-configure the mbus bridge registers each time this function
* is called. Since it may get called from the board code in
* later boot stages as well.
*/
mvebu_config_mbus_bridge(mbus);
#endif
return 0;
}

8
arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
View File

@@ -35,7 +35,7 @@ int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
#define ETM_MODULE_DETECT 2
#define PEX_MODE_GET(satr) ((satr & 0x6) >> 1)
#define PEX_CAPABILITY_GET(satr) (satr & 1)
#define PEX_CAPABILITY_GET(satr, port) ((satr >> port) & 1)
#define MV_PEX_UNIT_TO_IF(pex_unit) ((pex_unit < 3) ? (pex_unit * 4) : 9)
/* Static parametes */
@@ -176,7 +176,7 @@ u8 board_cpu_freq_get(void)
return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
}
__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
{
u32 board_id;
u32 serdes_cfg_val = 0; /* default */
@@ -352,7 +352,7 @@ int serdes_phy_config(void)
DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
}
info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
info = board_serdes_cfg_get();
if (info == NULL) {
DEBUG_INIT_S("Hight speed PHY Error #1\n");
@@ -675,7 +675,7 @@ int serdes_phy_config(void)
tmp |= (0x1 << 4);
if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
tmp |= (0x4 << 4);
if (0 == PEX_CAPABILITY_GET(satr11))
if (0 == PEX_CAPABILITY_GET(satr11, pex_unit))
tmp |= 0x1;
else
tmp |= 0x2;