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Merge git://www.denx.de/git/u-boot

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This commit is contained in:
Kim Phillips
2007-07-06 19:39:48 -05:00
parent 30d5c04c93 e80955f07d
commit 0459e7d3a0
168 changed files with 7638 additions and 1220 deletions
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1
include/74xx_7xx.h
View File

@@ -34,6 +34,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*----------------------------------------------------------------
* l2cr values

8
include/asm-ppc/gpio.h
View File

@@ -45,12 +45,14 @@ typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t;
typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t;
typedef struct {
unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
unsigned long add; /* gpio core base address */
gpio_driver_t in_out; /* Driver Setting */
gpio_select_t alt_nb; /* Selected Alternate */
gpio_out_t out_val;/* Default Output Value */
} gpio_param_s;
#endif
void gpio_config(int pin, int in_out, int gpio_alt, int out_val);
void gpio_write_bit(int pin, int val);
int gpio_read_out_bit(int pin);
void gpio_set_chip_configuration(void);

61
include/asm-ppc/processor.h
View File

@@ -35,18 +35,18 @@
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IS (1<<5) /* Book E Instruction space */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DS (1<<4) /* Book E Data space */
#define MSR_PE (1<<3) /* Protection Enable */
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
#define MSR_LE (1<<0) /* Little Endian */
#ifdef CONFIG_APUS_FAST_EXCEPT
#define MSR_ MSR_ME|MSR_IP|MSR_RI
@@ -123,9 +123,9 @@
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
#define DBCR_RST(x) (((x) & 0x3) << 28)
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_SYSTEM 3
#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
@@ -266,7 +266,7 @@
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
@@ -308,7 +308,7 @@
#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
#ifdef CONFIG_BOOKE
#define SPRN_SVR 0x3FF /* System Version Register */
#else
@@ -451,6 +451,17 @@
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
#ifdef CONFIG_440
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
#define MCSR_DRB 0x20000000 /* Data Read PLB Error */
#define MCSR_DWB 0x10000000 /* Data Write PLB Error */
#define MCSR_TLBP 0x08000000 /* TLB Parity Error */
#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
#endif
#define ESR_ST 0x00800000 /* Store Operation */
#if defined(CONFIG_MPC86xx)
@@ -484,17 +495,17 @@
#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
#define DBSR SPRN_DBSR /* Debug Status Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
#define EAR SPRN_EAR /* External Address Register */
#define EAR SPRN_EAR /* External Address Register */
#define ESR SPRN_ESR /* Exception Syndrome Register */
#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
@@ -511,13 +522,13 @@
#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_MPC86xx)
@@ -529,7 +540,7 @@
#define SVR SPRN_SVR /* System-On-Chip Version Register */
#define PVR SPRN_PVR /* Processor Version */
#define RPA SPRN_RPA /* Required Physical Address Register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
#define SPR1 SPRN_SPRG1
#define SPR2 SPRN_SPRG2
@@ -544,6 +555,8 @@
#define SPRG7 SPRN_SPRG7
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
#define SVR SPRN_SVR /* System Version Register */
#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
@@ -598,7 +611,7 @@
#define IVOR35 SPRN_IVOR35
#define MCSRR0 SPRN_MCSRR0
#define MCSRR1 SPRN_MCSRR1
#define L1CSR0 SPRN_L1CSR0
#define L1CSR0 SPRN_L1CSR0
#define L1CSR1 SPRN_L1CSR1
#define MCSR SPRN_MCSR
#define MMUCSR0 SPRN_MMUCSR0
@@ -607,7 +620,7 @@
#define PID1 SPRN_PID1
#define PID2 SPRN_PID2
#define MAS0 SPRN_MAS0
#define MAS1 SPRN_MAS1
#define MAS1 SPRN_MAS1
#define MAS2 SPRN_MAS2
#define MAS3 SPRN_MAS3
#define MAS4 SPRN_MAS4
@@ -619,7 +632,7 @@
#define DCRN_BEAR 0x090 /* Bus Error Address Register */
#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DMES 0x40000000 /* DMA Error Status */
#define BESR_RWS 0x20000000 /* Read/Write Status */
#define BESR_ETMASK 0x1C000000 /* Error Type */
@@ -676,8 +689,8 @@
#define IOCR_E3LP 0x01000000
#define IOCR_E4TE 0x00800000
#define IOCR_E4LP 0x00400000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDO 0x00008000
#define IOCR_2XC 0x00004000
#define IOCR_ATC 0x00002000
@@ -802,7 +815,7 @@
#define PVR_823 PVR_821
#define PVR_850 PVR_821
#define PVR_860 PVR_821
#define PVR_7400 0x000C0000
#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
/*

60
include/ata.h
View File

@@ -83,6 +83,66 @@
#define ATA_DEVICE(x) ((x & 1)<<4)
#define ATA_LBA 0xE0
enum {
ATA_MAX_DEVICES = 1, /* per bus/port */
ATA_MAX_PRD = 256, /* we could make these 256/256 */
ATA_SECT_SIZE = 256, /*256 words per sector */
/* bits in ATA command block registers */
ATA_HOB = (1 << 7), /* LBA48 selector */
ATA_NIEN = (1 << 1), /* disable-irq flag */
/*ATA_LBA = (1 << 6), */ /* LBA28 selector */
ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */
ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */
ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */
ATA_BUSY = (1 << 7), /* BSY status bit */
ATA_DRDY = (1 << 6), /* device ready */
ATA_DF = (1 << 5), /* device fault */
ATA_DRQ = (1 << 3), /* data request i/o */
ATA_ERR = (1 << 0), /* have an error */
ATA_SRST = (1 << 2), /* software reset */
ATA_ABORTED = (1 << 2), /* command aborted */
/* ATA command block registers */
ATA_REG_DATA = 0x00,
ATA_REG_ERR = 0x01,
ATA_REG_NSECT = 0x02,
ATA_REG_LBAL = 0x03,
ATA_REG_LBAM = 0x04,
ATA_REG_LBAH = 0x05,
ATA_REG_DEVICE = 0x06,
ATA_REG_STATUS = 0x07,
ATA_PCI_CTL_OFS = 0x02,
/* and their aliases */
ATA_REG_FEATURE = ATA_REG_ERR,
ATA_REG_CMD = ATA_REG_STATUS,
ATA_REG_BYTEL = ATA_REG_LBAM,
ATA_REG_BYTEH = ATA_REG_LBAH,
ATA_REG_DEVSEL = ATA_REG_DEVICE,
ATA_REG_IRQ = ATA_REG_NSECT,
/* SETFEATURES stuff */
SETFEATURES_XFER = 0x03,
XFER_UDMA_7 = 0x47,
XFER_UDMA_6 = 0x46,
XFER_UDMA_5 = 0x45,
XFER_UDMA_4 = 0x44,
XFER_UDMA_3 = 0x43,
XFER_UDMA_2 = 0x42,
XFER_UDMA_1 = 0x41,
XFER_UDMA_0 = 0x40,
XFER_MW_DMA_2 = 0x22,
XFER_MW_DMA_1 = 0x21,
XFER_MW_DMA_0 = 0x20,
XFER_PIO_4 = 0x0C,
XFER_PIO_3 = 0x0B,
XFER_PIO_2 = 0x0A,
XFER_PIO_1 = 0x09,
XFER_PIO_0 = 0x08,
XFER_SW_DMA_2 = 0x12,
XFER_SW_DMA_1 = 0x11,
XFER_SW_DMA_0 = 0x10,
XFER_PIO_SLOW = 0x00
};
/*
* ATA Commands (only mandatory commands listed here)
*/

9
include/common.h
View File

@@ -38,7 +38,7 @@ typedef volatile unsigned char vu_char;
#include <linux/string.h>
#include <asm/ptrace.h>
#include <stdarg.h>
#if defined(CONFIG_PCI) && defined(CONFIG_440)
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
#include <pci.h>
#endif
#if defined(CONFIG_8xx)
@@ -248,10 +248,11 @@ void pci_init (void);
void pci_init_board(void);
void pciinfo (int, int);
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
int pci_pre_init (struct pci_controller * );
# endif
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif

4
include/configs/CPCI405.h
View File

@@ -55,6 +55,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_DNS | \

5
include/configs/CPCI4052.h
View File

@@ -37,6 +37,7 @@
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
@@ -56,6 +57,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */

4
include/configs/CPCI405AB.h
View File

@@ -57,6 +57,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */

4
include/configs/CPCI405DT.h
View File

@@ -56,6 +56,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */

1
include/configs/CPCI440.h
View File

@@ -33,6 +33,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_CPCI440 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */

1
include/configs/JSE.h
View File

@@ -49,6 +49,7 @@
/* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
#define CONFIG_SYSTEMACE 1
#define CFG_SYSTEMACE_BASE 0xf0000000
#define CFG_SYSTEMACE_WIDTH 8
#define CONFIG_DOS_PARTITION 1
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */

2
include/configs/KAREF.h
View File

@@ -38,6 +38,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
@@ -262,7 +263,6 @@
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */

2
include/configs/METROBOX.h
View File

@@ -104,6 +104,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_METROBOX 1 /* Board is Metrobox */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */
@@ -331,7 +332,6 @@
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */

8
include/configs/MPC8313ERDB.h
View File

@@ -303,11 +303,11 @@
#endif
#define CONFIG_GMII 1 /* MII PHY management */
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0x1c
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0

8
include/configs/MPC8349EMDS.h
View File

@@ -432,10 +432,10 @@
#endif
#define CONFIG_GMII 1 /* MII PHY management */
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

14
include/configs/MPC8349ITX.h
View File

@@ -375,18 +375,18 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_MII
#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
#define CONFIG_MPC83XX_TSEC1
#define CONFIG_TSEC1
#ifdef CONFIG_MPC83XX_TSEC1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#ifdef CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX 0
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC2_NAME "TSEC1"
#define CFG_TSEC2_OFFSET 0x25000
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
#define TSEC2_PHY_ADDR 4
@@ -637,11 +637,11 @@ boards, we say we have two, but don't display a message if we find only one. */
*/
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_MPC83XX_TSEC1
#ifdef CONFIG_TSEC1
#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
#endif

8
include/configs/MPC8540ADS.h
View File

@@ -366,10 +366,10 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

8
include/configs/MPC8540EVAL.h
View File

@@ -212,10 +212,10 @@
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define TSEC1_PHY_ADDR 7

8
include/configs/MPC8541CDS.h
View File

@@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

8
include/configs/MPC8544DS.h
View File

@@ -359,10 +359,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0

16
include/configs/MPC8548CDS.h
View File

@@ -391,14 +391,14 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
#undef CONFIG_MPC85XX_TSEC4
#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC2"
#undef CONFIG_TSEC4
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0

8
include/configs/MPC8555CDS.h
View File

@@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

8
include/configs/MPC8560ADS.h
View File

@@ -356,10 +356,10 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

12
include/configs/MPC8568MDS.h
View File

@@ -353,12 +353,12 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
#undef CONFIG_MPC85XX_TSEC3
#undef CONFIG_MPC85XX_TSEC4
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
#undef CONFIG_TSEC3
#undef CONFIG_TSEC4
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 2

16
include/configs/MPC8641HPCN.h
View File

@@ -359,14 +359,14 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC86XX_TSEC1 1
#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1"
#define CONFIG_MPC86XX_TSEC2 1
#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2"
#define CONFIG_MPC86XX_TSEC3 1
#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3"
#define CONFIG_MPC86XX_TSEC4 1
#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define CONFIG_TSEC4 1
#define CONFIG_TSEC4_NAME "eTSEC4"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

8
include/configs/PM854.h
View File

@@ -262,10 +262,10 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

8
include/configs/PM856.h
View File

@@ -258,10 +258,10 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

4
include/configs/TQM5200.h
View File

@@ -44,7 +44,7 @@
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
@@ -238,7 +238,7 @@
"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
#else
#define CUSTOM_ENV_SETTINGS \
#define CUSTOM_ENV_SETTINGS \
"bootfile=cam5200/uImage\0" \
"u-boot=cam5200/u-boot.bin\0" \
"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"

8
include/configs/TQM834x.h
View File

@@ -248,10 +248,10 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_NET_MULTI
#endif
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

8
include/configs/TQM85xx.h
View File

@@ -258,10 +258,10 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

1
include/configs/XPEDITE1K.h
View File

@@ -238,7 +238,6 @@ extern void out32(unsigned int, unsigned long);
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */

4
include/configs/acadia.h
View File

@@ -75,7 +75,7 @@
#define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_ADDR 0xf8000000
#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
@@ -159,7 +159,7 @@
*/
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)

6
include/configs/alpr.h
View File

@@ -29,6 +29,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_ALPR 1 /* Board is ebony */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
@@ -94,7 +95,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -256,7 +257,7 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
@@ -274,7 +275,6 @@
#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_MASTER_INIT

16
include/configs/bamboo.h
View File

@@ -32,6 +32,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_BAMBOO 1 /* Board is BAMBOO */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@@ -73,9 +74,9 @@
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@@ -114,8 +115,8 @@
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
@@ -125,11 +126,11 @@
#define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned char
#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -388,7 +389,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

4
include/configs/ebony.h
View File

@@ -32,6 +32,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_EBONY 1 /* Board is ebony */
#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
@@ -121,7 +122,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
@@ -269,7 +270,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */

1
include/configs/katmai.h
View File

@@ -314,7 +314,6 @@
#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#undef CFG_PCI_MASTER_INIT

1
include/configs/luan.h
View File

@@ -273,7 +273,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#undef CFG_PCI_MASTER_INIT

449
include/configs/lwmon5.h Normal file
View File

@@ -0,0 +1,449 @@
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
* lwmon5.h - configuration for lwmon5 board
***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
#define CONFIG_LWMON5 1 /* Board is lwmon5 */
#define CONFIG_440EPX 1 /* Specific PPC440EPx */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
#define CFG_BOOT_BASE_ADDR 0xf0000000
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_LIME_BASE_0 0xc0000000
#define CFG_LIME_BASE_1 0xc1000000
#define CFG_LIME_BASE_2 0xc2000000
#define CFG_LIME_BASE_3 0xc3000000
#define CFG_FPGA_BASE_0 0xc4000000
#define CFG_FPGA_BASE_1 0xc4200000
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
/* Don't change either of these */
#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
#define CFG_USB2D0_BASE 0xe0000100
#define CFG_USB_DEVICE 0xe0000000
#define CFG_USB_HOST 0xe0000400
/*-----------------------------------------------------------------------
* Initial RAM & stack pointer
*----------------------------------------------------------------------*/
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Serial Port
*----------------------------------------------------------------------*/
#undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SERIAL_MULTI 1
/* define this if you want console on UART1 */
#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*-----------------------------------------------------------------------
* Environment
*----------------------------------------------------------------------*/
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_FLASH_CFI /* The flash is CFI compatible */
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM (256) /* 256MB */
#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
#if 0 /* test-only: disable ECC for now */
#define CONFIG_DDR_ECC 1 /* enable ECC */
#endif
/*-----------------------------------------------------------------------
* I2C
*----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=lwmon5\0" \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
"rootpath=/opt/eldk/ppc_4xxFP\0" \
"bootfile=/tftpboot/lwmon5/uImage\0" \
"kernel_addr=FC000000\0" \
"ramdisk_addr=FC180000\0" \
"load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
"update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
"cp.b 200000 FFF80000 80000\0" \
"upd=run load;run update\0" \
""
#define CONFIG_BOOTCOMMAND "run flash_self"
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_IBM_EMAC4_V4 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NET_MULTI 1
#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
#define CONFIG_PHY1_ADDR 1
/* USB */
#ifdef CONFIG_440EPX
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
#define CMD_USB CFG_CMD_USB
#else
#define CMD_USB 0 /* no USB on 440GRx */
#endif /* CONFIG_440EPX */
/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_FAT | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
CFG_CMD_NET | \
CFG_CMD_NFS | \
CFG_CMD_PCI | \
CFG_CMD_PING | \
CFG_CMD_REGINFO | \
CFG_CMD_SDRAM | \
CMD_USB)
#define CONFIG_SUPPORT_VFAT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/*-----------------------------------------------------------------------
* Miscellaneous configurable options
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI /* include pci support */
#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*----------------------------------------------------------------------*/
#define CFG_FLASH CFG_FLASH_BASE
/* Memory Bank 0 (NOR-FLASH) initialization */
#define CFG_EBC_PB0AP 0x03050200
#define CFG_EBC_PB0CR (CFG_FLASH | 0xdc000)
/* Memory Bank 1 (Lime) initialization */
#define CFG_EBC_PB1AP 0x01004380
#define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000)
/* Memory Bank 2 (FPGA) initialization */
#define CFG_EBC_PB2AP 0x01004400
#define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000)
/* Memory Bank 3 (FPGA2) initialization */
#define CFG_EBC_PB3AP 0x01004400
#define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000)
#define CFG_EBC_CFG 0xb8400000
/*-----------------------------------------------------------------------
* Graphics (Fujitsu Lime)
*----------------------------------------------------------------------*/
/* SDRAM Clock frequency adjustment register */
#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000
/* Lime Clock frequency is to set 133MHz */
#define CFG_LIME_CLOCK_133MHZ 0x10000
/* SDRAM Parameter register */
#define CFG_LIME_MMR 0xC1FCFFFC
/* SDRAM parameter value */
#define CFG_LIME_MMR_VALUE 0x414FB7F2
/*-----------------------------------------------------------------------
* GPIO Setup
*----------------------------------------------------------------------*/
#define CFG_GPIO_PHY1_RST 12
#define CFG_GPIO_FLASH_WP 14
#define CFG_GPIO_PHY0_RST 22
#define CFG_GPIO_WATCHDOG 58
#define CFG_GPIO_LIME_S 59
#define CFG_GPIO_LIME_RST 60
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
}, \
{ \
/* GPIO Core 1 */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
} \
}
/*-----------------------------------------------------------------------
* Cache Configuration
*----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
#endif /* __CONFIG_H */

4
include/configs/ocotea.h
View File

@@ -41,6 +41,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_OCOTEA 1 /* Board is ebony */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
@@ -136,7 +137,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
@@ -293,7 +294,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */

4
include/configs/p3p440.h
View File

@@ -35,6 +35,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_P3P440 1 /* Board is P3P440 */
#define CONFIG_440GP 1 /* Specifc GP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
@@ -226,7 +227,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
@@ -285,7 +285,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */

134
include/configs/pcs440ep.h
View File

@@ -32,6 +32,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
#define CONFIG_440EP 1 /* Specific PPC440EP support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@@ -103,7 +104,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -266,7 +267,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@@ -315,76 +315,76 @@
/*-----------------------------------------------------------------------
* PPC440 GPIO Configuration
*/
#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \
#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
{ \
/* GPIO Core 0 */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6 EBC_CS_N(1) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7 EBC_CS_N(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8 EBC_CS_N(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9 EBC_CS_N(4) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO10 EBC_CS_N(5) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO11 EBC_BUS_ERR */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO12 ZII_p0Rxd(0) */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO13 ZII_p0Rxd(1) */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO14 ZII_p0Rxd(2) */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO15 ZII_p0Rxd(3) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16 ZII_p0Txd(0) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17 ZII_p0Txd(1) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18 ZII_p0Txd(2) */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19 ZII_p0Txd(3) */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO20 ZII_p0Rx_er */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO21 ZII_p0Rx_dv */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO22 ZII_p0RxCrs */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23 ZII_p0Tx_er */ \
{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24 ZII_p0Tx_en */ \
{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO25 ZII_p0Col */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO26 USB2D_RXVALID */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO28 USB2D_TXVALID */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \
{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
}, \
{ \
/* GPIO Core 1 */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO32 USB2D_OPMODE0 */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO33 USB2D_OPMODE1 */ \
{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT3 }, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37 UART0_RTS_N */ \
{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT2 }, /* GPIO39 UART0_RI_N UART1_SIN */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO40 UIC_IRQ(0) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO41 UIC_IRQ(1) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO42 UIC_IRQ(2) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO43 UIC_IRQ(3) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
{ GPIO1_BASE, GPIO_BI, GPIO_SEL }, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO49 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO50 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO51 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO52 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO53 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO54 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO55 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO56 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO57 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO58 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO59 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO60 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO61 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO62 Unselect via TraceSelect Bit */ \
{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO63 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \
{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \
{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \
} \
}

8
include/configs/sbc8349.h
View File

@@ -401,10 +401,10 @@
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_PHY_BCM5421S 1
#define TSEC1_PHY_ADDR 0x19
#define TSEC2_PHY_ADDR 0x1a

9
include/configs/sc520_cdp.h
View File

@@ -181,6 +181,15 @@
#undef CONFIG_IDE_RESET /* reset for ide unsupported... */
#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
/************************************************************
*SATA/Native Stuff
************************************************************/
#define CFG_SATA_SUPPORTED 1
#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */
#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */
#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */
/************************************************************
* ATAPI support (experimental)
************************************************************/

23
include/configs/sequoia.h
View File

@@ -37,6 +37,7 @@
#else
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
/* Detect Sequoia PLL input clock automatically via CPLD bit */
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
@@ -58,6 +59,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
@@ -80,7 +82,7 @@
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
@@ -125,7 +127,7 @@
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -327,6 +329,22 @@
CFG_CMD_SDRAM | \
CMD_USB)
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_UART | \
CFG_POST_I2C | \
CFG_POST_CACHE | \
CFG_POST_FPU | \
CFG_POST_ETHER | \
CFG_POST_SPR)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CONFIG_LOGBUFFER
#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_SUPPORT_VFAT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -370,7 +388,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

8
include/configs/stxgp3.h
View File

@@ -230,10 +230,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2

134
include/configs/stxssa.h
View File

@@ -42,20 +42,20 @@
#define CONFIG_CPM2 1 /* has CPM2 */
#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
#undef CONFIG_PCI /* pci ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_PCI /* PCI ethernet support */
#define CONFIG_TSEC_ENET /* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
#undef CONFIG_DDR_DLL /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
/* sysclk for MPC85xx
*/
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
/* Blinkin' LEDs for Robert :-)
*/
@@ -64,23 +64,23 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
/* Localbus connector. There are many options that can be
/* Localbus connector. There are many options that can be
* connected here, including sdram or lots of flash.
* This address, however, is used to configure a 256M local bus
* window that includes the Config latch below.
*/
#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
/* There are various flash options used, we configure for the largest,
@@ -88,16 +88,16 @@
* sizes.
*/
#ifdef CONFIG_STXSSA_4M
#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
#else
#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
#endif
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
@@ -110,22 +110,22 @@
*/
#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#undef CFG_RAMBOOT
#endif
#ifdef CFG_RAMBOOT
#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
#else
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#endif
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -140,14 +140,14 @@
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
#undef CONFIG_CLOCKS_IN_MHZ
/* local bus definitions */
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
#define CFG_OR2_PRELIM 0xfc006901
#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
#define CFG_LBC_LBCR 0x00000000
#define CFG_LBC_LSRT 0x20000000
#define CFG_LBC_MRTPR 0x20000000
@@ -158,52 +158,52 @@
#define CFG_LBC_LSDMR_5 0x4061b723
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
#ifdef CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
/* I2C */
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#if 0
#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
#else
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CFG_I2C_NOPROBES
#endif
#define CFG_I2C_OFFSET 0x3000
/* I2C EEPROM. AT24C32, we keep our environment in here.
/* I2C EEPROM. AT24C32, we keep our environment in here.
*/
#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
#define CFG_I2C_EEPROM_ADDR_LEN 2
@@ -232,35 +232,35 @@
#if defined(CONFIG_PCI) /* PCI Ethernet card */
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_EEPRO100
#define CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif
#undef CONFIG_PCI_SCAN_SHOW
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CONFIG_PCI_SCAN_SHOW
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#undef CONFIG_MPS85XX_FEC
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 4
@@ -270,9 +270,9 @@
#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
#undef CONFIG_ETHER_NONE /* define if ether on something else */
#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
#if (CONFIG_ETHER_INDEX == 2)
/*
@@ -281,19 +281,19 @@
* - Select bus for bd/buffers
* - Full duplex
*/
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
#define CFG_CPMFCR_RAMTYPE 0
#if 0
#define CFG_FCC_PSMR (FCC_PSMR_FDE)
#define CFG_FCC_PSMR (FCC_PSMR_FDE)
#else
#define CFG_FCC_PSMR 0
#define CFG_FCC_PSMR 0
#endif
#define FETH2_RST 0x01
#elif (CONFIG_ETHER_INDEX == 3)
/* need more definitions here for FE3 */
#define FETH3_RST 0x80
#endif /* CONFIG_ETHER_INDEX */
#endif /* CONFIG_ETHER_INDEX */
/* MDIO is done through the TSEC0 control.
*/
@@ -415,13 +415,13 @@
*/
#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
#define CONFIG_BAUDRATE 38400
#define CONFIG_BAUDRATE 38400
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
#define CONFIG_SERVERIP 192.168.85.1
#define CONFIG_IPADDR 192.168.85.60
#define CONFIG_IPADDR 192.168.85.60
#define CONFIG_GATEWAYIP 192.168.85.1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_HOSTNAME STX_SSA
@@ -431,7 +431,7 @@
#else /* ENV IS IN FLASH -- use a full-blown envionment */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */

6
include/configs/taishan.h
View File

@@ -30,6 +30,7 @@
*----------------------------------------------------------------------*/
#define CONFIG_TAISHAN 1 /* Board is taishan */
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
@@ -217,8 +218,8 @@
#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x1
#define CONFIG_PHY3_ADDR 0x3
#define CONFIG_ET1011C_PHY 1
@@ -297,7 +298,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */

4
include/configs/yosemite.h
View File

@@ -38,6 +38,7 @@
#define CONFIG_440GR 1 /* Specific PPC440GR support */
#define CONFIG_HOSTNAME yellowstone
#endif
#define CONFIG_440 1 /* ... PPC440 family */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
@@ -122,7 +123,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@@ -311,7 +312,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

1
include/configs/yucca.h
View File

@@ -289,7 +289,6 @@
#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#undef CFG_PCI_MASTER_INIT

26
include/logbuff.h
View File

@@ -1,5 +1,5 @@
/*
* (C) Copyright 2002
* (C) Copyright 2002-2007
* Detlev Zundel, dzu@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -25,6 +25,7 @@
#ifdef CONFIG_LOGBUFFER
#define LOGBUFF_MAGIC 0xc0de4ced /* Forced by code, eh! */
#define LOGBUFF_LEN (16384) /* Must be 16k right now */
#define LOGBUFF_MASK (LOGBUFF_LEN-1)
#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
@@ -32,6 +33,29 @@
#define LOGBUFF_INITIALIZED (1<<31)
/* The mapping used here has to be the same as in setup_ext_logbuff ()
in linux/kernel/printk */
typedef struct {
union {
struct {
unsigned long tag;
unsigned long start;
unsigned long con;
unsigned long end;
unsigned long chars;
} v2;
struct {
unsigned long dummy;
unsigned long tag;
unsigned long start;
unsigned long size;
unsigned long chars;
} v1;
};
unsigned char buf[0];
} logbuff_t;
int drv_logbuff_init (void);
void logbuff_init_ptrs (void);
void logbuff_log(char *msg);

43
include/mpc5xx.h
View File

@@ -36,6 +36,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* ISB bit in IMMR to set internal memory map
@@ -75,10 +76,10 @@
#define SIUMCR_DBPC01 0x00080000 /* - " - */
#define SIUMCR_DBPC10 0x00100000 /* - " - */
#define SIUMCR_DBPC11 0x00180000 /* - " - */
#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
#define SIUMCR_GPC00 0x00000000 /* General Pins Config */
#define SIUMCR_GPC01 0x00020000 /* General Pins Config */
#define SIUMCR_GPC10 0x00040000 /* General Pins Config */
#define SIUMCR_GPC11 0x00060000 /* General Pins Config */
#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
#define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
#define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
@@ -89,7 +90,7 @@
#define SIUMCR_MLRC01 0x00000400 /* - " - */
#define SIUMCR_MLRC10 0x00000800 /* - " - */
#define SIUMCR_MLRC11 0x00000c00 /* - " - */
#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
#define SIUMCR_MTSC 0x00000100 /* Memory transfer */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control Register
@@ -122,13 +123,13 @@
* SCCR - System Clock and reset Control Register
*/
#define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
#define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
#define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
#define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
#define SCCR_EBDF11 0x00060000 /* reserved */
#define SCCR_TBS 0x02000000 /* Time Base Source */
#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
@@ -137,11 +138,11 @@
/*-----------------------------------------------------------------------
* MC - Memory Controller
*/
#define BR_V 0x00000001 /* Bank valid */
#define BR_BI 0x00000002 /* Burst inhibit */
#define BR_PS_8 0x00000400 /* 8 bit port size */
#define BR_PS_16 0x00000800 /* 16 bit port size */
#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_V 0x00000001 /* Bank valid */
#define BR_BI 0x00000002 /* Burst inhibit */
#define BR_PS_8 0x00000400 /* 8 bit port size */
#define BR_PS_16 0x00000800 /* 16 bit port size */
#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_LBDIR 0x00000008 /* Late burst data in progess */
#define BR_SETA 0x00000004 /* External Data Acknowledge */
#define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
@@ -158,8 +159,8 @@
/*-----------------------------------------------------------------------
* UMCR - UIMB Module Configuration Register
*/
#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
#define UMCR_HSPEED 0x10000000 /* Half speed */
#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
#define UMCR_HSPEED 0x10000000 /* Half speed */
/*-----------------------------------------------------------------------
* ICTRL - I-Bus Support Control Register
@@ -173,16 +174,16 @@
* SCI - Serial communication interface
*/
#define SCI_TDRE 0x0100 /* Transmit data register empty */
#define SCI_TE 0x0008 /* Transmitter enabled */
#define SCI_TDRE 0x0100 /* Transmit data register empty */
#define SCI_TE 0x0008 /* Transmitter enabled */
#define SCI_RE 0x0004 /* Receiver enabled */
#define SCI_RDRF 0x0040 /* Receive data register full */
#define SCI_PE 0x0400 /* Parity enable */
#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
#define SCI_SCXDR_MK 0x00ff /* Data register mask */
#define SCI_RDRF 0x0040 /* Receive data register full */
#define SCI_PE 0x0400 /* Parity enable */
#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */
#define SCI_SCXDR_MK 0x00ff /* Data register mask */
#define SCI_M_11 0x0200 /* Frame size is 11 bit */
#define SCI_M_10 0x0000 /* Frame size is 10 bit */
#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */
#define SCI_PORT_2 ((int)2)
#endif /* __MPC5XX_H__ */

1
include/mpc5xxx.h
View File

@@ -39,6 +39,7 @@
/* Exception offsets (PowerPC standard) */
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET
/* useful macros for manipulating CSx_START/STOP */
#if defined(CONFIG_MGT5100)

1
include/mpc8220.h
View File

@@ -35,6 +35,7 @@
/* Exception offsets (PowerPC standard) */
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET
/* Internal memory map */
/* MPC8220 Internal Register MMAP */

8
include/mpc824x.h
View File

@@ -88,7 +88,7 @@
#define PREP_PCI_MEMORY_BUS 0x80000000
#define PREP_PCI_MEMORY_SIZE 0x80000000
#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */
#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */
#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */
#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */
@@ -98,8 +98,8 @@
#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */
#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */
#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */
#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */
#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */
#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */
@@ -142,6 +142,8 @@
#define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/
#define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */
#define _START_OFFSET EXC_OFF_SYS_RESET
#define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */
#define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */
#define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */

18
include/mpc8260.h
View File

@@ -53,7 +53,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* BCR - Bus Configuration Register 4-25
@@ -664,7 +664,7 @@
#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */
/*-----------------------------------------------------------------------
* LSDMR - Local Bus SDRAM Mode Register 10-24
* LSDMR - Local Bus SDRAM Mode Register 10-24
*/
/*
@@ -707,23 +707,23 @@
/*-----------------------------------------------------------------------
* TMR1-TMR4 - Timer Mode Registers 17-6
*/
#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/
#define TMRx_OM 0x0020 /* Output Mode */
#define TMRx_OM 0x0020 /* Output Mode */
#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/
#define TMRx_FRR 0x0008 /* Free Run/Restart */
#define TMRx_FRR 0x0008 /* Free Run/Restart */
#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
#define TMRx_GE 0x0001 /* Gate Enable */
#define TMRx_GE 0x0001 /* Gate Enable */
#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/
#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/
#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/
#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
/*-----------------------------------------------------------------------

11
include/mpc83xx.h
View File

@@ -25,6 +25,7 @@
/* System reset offset (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET
/* IMMRBAR - Internal Memory Register Base Address
*/
@@ -438,9 +439,9 @@
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_MPC831X)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
#define HRCWH_RL_EXT_LEGACY 0x00000000
@@ -1217,7 +1218,7 @@
#define FCR_CMD1 0x00FF0000
#define FCR_CMD1_SHIFT 16
#define FCR_CMD2 0x0000FF00
#define FCR_CMD2_SHIFT 8
#define FCR_CMD2_SHIFT 8
#define FCR_CMD3 0x000000FF
#define FCR_CMD3_SHIFT 0
@@ -1241,8 +1242,8 @@
/* LTESR - Transfer Error Status Register
*/
#define LTESR_BM 0x80000000
#define LTESR_FCT 0x40000000
#define LTESR_PAR 0x20000000
#define LTESR_FCT 0x40000000
#define LTESR_PAR 0x20000000
#define LTESR_WP 0x04000000
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000

1
include/mpc85xx.h
View File

@@ -8,6 +8,7 @@
#define __MPC85xx_H__
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET EXC_OFF_SYS_RESET
#if defined(CONFIG_E500)
#include <e500.h>

2
include/mpc86xx.h
View File

@@ -8,7 +8,7 @@
#define __MPC86xx_H__
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*
* platform register addresses

14
include/mpc8xx.h
View File

@@ -35,7 +35,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control Register 11-9
@@ -208,12 +208,12 @@
#define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */
#define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
#define SCCR_DFNL001 0x00000100 /* Division by 4 */
#define SCCR_DFNL010 0x00000200 /* Division by 8 */
#define SCCR_DFNL011 0x00000300 /* Division by 16 */
#define SCCR_DFNL100 0x00000400 /* Division by 32 */
#define SCCR_DFNL101 0x00000500 /* Division by 64 */
#define SCCR_DFNL110 0x00000600 /* Division by 128 */
#define SCCR_DFNL001 0x00000100 /* Division by 4 */
#define SCCR_DFNL010 0x00000200 /* Division by 8 */
#define SCCR_DFNL011 0x00000300 /* Division by 16 */
#define SCCR_DFNL100 0x00000400 /* Division by 32 */
#define SCCR_DFNL101 0x00000500 /* Division by 64 */
#define SCCR_DFNL110 0x00000600 /* Division by 128 */
#define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */
#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */

1
include/post.h
View File

@@ -91,6 +91,7 @@ extern int post_hotkeys_pressed(void);
#define CFG_POST_SYSMON 0x00000800
#define CFG_POST_DSP 0x00001000
#define CFG_POST_CODEC 0x00002000
#define CFG_POST_FPU 0x00004000
#endif /* CONFIG_POST */

23
include/ppc405.h
View File

@@ -27,6 +27,15 @@
/*--------------------------------------------------------------------- */
#define srr2 0x3de /* save/restore register 2 */
#define srr3 0x3df /* save/restore register 3 */
/*
* 405 does not really have CSRR0/1 but SRR2/3 are used during critical
* exception for the exact same purposes - let's alias them and have a
* common handling in crit_return() and CRIT_EXCEPTION
*/
#define csrr0 srr2
#define csrr1 srr3
#define dbsr 0x3f0 /* debug status register */
#define dbcr0 0x3f2 /* debug control register 0 */
#define dbcr1 0x3bd /* debug control register 1 */
@@ -134,12 +143,12 @@
#define UIC_USBH1 0x00040000 /* USB Host 1 */
#define UIC_USBH2 0x00020000 /* USB Host 2 */
#define UIC_USBDEV 0x00010000 /* USB Device */
#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
#define UIC_ENET1 0x00008000 /* dummy define */
#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
#define UIC_ENET1 0x00008000 /* dummy define */
#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
@@ -877,7 +886,7 @@
#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
#define ecr (0xaa) /* edge conditioner register (405gpr) */
@@ -1110,13 +1119,13 @@
| UART Register Offsets
'----------------------------------------------------------------------------*/
#define DATA_REG 0x00
#define DL_LSB 0x00
#define DL_MSB 0x01
#define DL_LSB 0x00
#define DL_MSB 0x01
#define INT_ENABLE 0x01
#define FIFO_CONTROL 0x02
#define LINE_CONTROL 0x03
#define MODEM_CONTROL 0x04
#define LINE_STATUS 0x05
#define LINE_STATUS 0x05
#define MODEM_STATUS 0x06
#define SCRATCH 0x07

72
include/ppc440.h
View File

@@ -82,10 +82,7 @@
#define ivor13 0x19d /* interrupt vector offset register 13 */
#define ivor14 0x19e /* interrupt vector offset register 14 */
#define ivor15 0x19f /* interrupt vector offset register 15 */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#if defined(CONFIG_440)
#define mcsrr0 0x23a /* machine check save/restore register 0 */
#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
#define mcsr 0x23c /* machine check status register */
@@ -115,7 +112,7 @@
#define icdbtrh 0x39f /* instruction cache debug tag register high */
#define mmucr 0x3b2 /* mmu control register */
#define ccr0 0x3b3 /* core configuration register 0 */
#define ccr1 0x378 /* core configuration for 440x5 only */
#define ccr1 0x378 /* core configuration for 440x5 only */
#define icdbdr 0x3d3 /* instruction cache debug data register */
#define dbdr 0x3f3 /* debug data register */
@@ -139,7 +136,7 @@
#define clk_opbd 0x00c0
#define clk_perd 0x00e0
#define clk_mald 0x0100
#define clk_spcid 0x0120
#define clk_spcid 0x0120
#define clk_icfg 0x0140
/* 440gx sdr register definations */
@@ -285,6 +282,30 @@
#define sdr_sdstp3 0x4003
#endif /* CONFIG_440GX */
/*----------------------------------------------------------------------------+
| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
+----------------------------------------------------------------------------*/
#define CCR0_PRE 0x40000000
#define CCR0_CRPE 0x08000000
#define CCR0_DSTG 0x00200000
#define CCR0_DAPUIB 0x00100000
#define CCR0_DTB 0x00008000
#define CCR0_GICBT 0x00004000
#define CCR0_GDCBT 0x00002000
#define CCR0_FLSTA 0x00000100
#define CCR0_ICSLC_MASK 0x0000000C
#define CCR0_ICSLT_MASK 0x00000003
#define CCR1_TCS_MASK 0x00000080
#define CCR1_TCS_INTCLK 0x00000000
#define CCR1_TCS_EXTCLK 0x00000080
#define MMUCR_SWOA 0x01000000
#define MMUCR_U1TE 0x00400000
#define MMUCR_U2SWOAE 0x00200000
#define MMUCR_DULXE 0x00800000
#define MMUCR_IULXE 0x00400000
#define MMUCR_STS 0x00100000
#define MMUCR_STID_MASK 0x000000FF
#ifdef CONFIG_440SPE
#undef sdr_sdstp2
#define sdr_sdstp2 0x0022
@@ -310,30 +331,6 @@
#define sdr_sdstp6 0x4005
#define sdr_sdstp7 0x4007
/*----------------------------------------------------------------------------+
| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
+----------------------------------------------------------------------------*/
#define CCR0_PRE 0x40000000
#define CCR0_CRPE 0x08000000
#define CCR0_DSTG 0x00200000
#define CCR0_DAPUIB 0x00100000
#define CCR0_DTB 0x00008000
#define CCR0_GICBT 0x00004000
#define CCR0_GDCBT 0x00002000
#define CCR0_FLSTA 0x00000100
#define CCR0_ICSLC_MASK 0x0000000C
#define CCR0_ICSLT_MASK 0x00000003
#define CCR1_TCS_MASK 0x00000080
#define CCR1_TCS_INTCLK 0x00000000
#define CCR1_TCS_EXTCLK 0x00000080
#define MMUCR_SEOA 0x01000000
#define MMUCR_U1TE 0x00400000
#define MMUCR_U2SWOAE 0x00200000
#define MMUCR_DULXE 0x00800000
#define MMUCR_IULXE 0x00400000
#define MMUCR_STS 0x00100000
#define MMUCR_STID_MASK 0x000000FF
#define SDR0_CFGADDR 0x00E
#define SDR0_CFGDATA 0x00F
@@ -687,8 +684,8 @@
#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
#define SDRAM_CODT_IO_HIZ 0x00000000
#define SDRAM_CODT_IO_NMODE 0x00000001
#define SDRAM_CODT_IO_HIZ 0x00000000
#define SDRAM_CODT_IO_NMODE 0x00000001
/*-----------------------------------------------------------------------------+
| SDRAM Mode Register
@@ -956,7 +953,8 @@
#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* Pin Function Control Register 1 */
#define SDR0_PFC1 0x4101
#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
@@ -1025,7 +1023,7 @@
#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR_USB2D0CR 0x0320
#define SDR0_USB2D0CR 0x0320
#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
@@ -1103,6 +1101,8 @@
#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
#define SDR0_PFC4 0x4104
/* USB2PHY0 Control Register */
#define SDR0_USB2PHY0CR 0x4103
#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
@@ -1421,7 +1421,7 @@
#define uicvr uic0vr
#define uicvcr uic0vcr
#if defined(CONFIG_440SPE)
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
/*----------------------------------------------------------------------------+
| Clock / Power-on-reset DCR's.
+----------------------------------------------------------------------------*/
@@ -1490,9 +1490,11 @@
#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
#define CPR0_PERD 0xE0
#if !defined(CONFIG_440EPX)
#define CPR0_PERD_PERDV0_MASK 0x03000000
#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
#endif
#define CPR0_MALD 0x100
#define CPR0_MALD_MALDV0_MASK 0x03000000

2
include/ppc4xx.h
View File

@@ -22,6 +22,8 @@
#ifndef __PPC4XX_H__
#define __PPC4XX_H__
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
#if defined(CONFIG_440)
#include <ppc440.h>

102
include/ppc_asm.tmpl
View File

@@ -113,11 +113,11 @@
#if defined(CONFIG_5xx)
/* Some special purpose registers */
#define DER 149 /* Debug Enable Register */
#define COUNTA 150 /* Breakpoint Counter */
#define COUNTB 151 /* Breakpoint Counter */
#define LCTRL1 156 /* Load/Store Support */
#define LCTRL2 157 /* Load/Store Support */
#define DER 149 /* Debug Enable Register */
#define COUNTA 150 /* Breakpoint Counter */
#define COUNTB 151 /* Breakpoint Counter */
#define LCTRL1 156 /* Load/Store Support */
#define LCTRL2 157 /* Load/Store Support */
#define ICTRL 158 /* I-Bus Support Control Register */
#define EID 81
#endif /* CONFIG_5xx */
@@ -217,7 +217,7 @@
* We assume sprg3 has the physical address of the current
* task's thread_struct.
*/
#define EXCEPTION_PROLOG \
#define EXCEPTION_PROLOG(reg1, reg2) \
mtspr SPRG0,r20; \
mtspr SPRG1,r21; \
mfcr r20; \
@@ -235,8 +235,10 @@
stw r22,_CTR(r21); \
mfspr r20,XER; \
stw r20,_XER(r21); \
mfspr r22,SRR0; \
mfspr r23,SRR1; \
mfspr r20,DEAR; \
stw r20,_DAR(r21); \
mfspr r22,reg1; \
mfspr r23,reg2; \
stw r0,GPR0(r21); \
stw r1,GPR1(r21); \
stw r2,GPR2(r21); \
@@ -248,41 +250,6 @@
* r21, r22 (SRR0), and r23 (SRR1).
*/
/*
* Critical exception entry code. This is just like the other exception
* code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1.
*/
#define CRITICAL_EXCEPTION_PROLOG \
mtspr SPRG0,r20; \
mtspr SPRG1,r21; \
mfcr r20; \
subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
stw r20,_CCR(r21); /* save registers */ \
stw r22,GPR22(r21); \
stw r23,GPR23(r21); \
mfspr r20,SPRG0; \
stw r20,GPR20(r21); \
mfspr r22,SPRG1; \
stw r22,GPR21(r21); \
mflr r20; \
stw r20,_LINK(r21); \
mfctr r22; \
stw r22,_CTR(r21); \
mfspr r20,XER; \
stw r20,_XER(r21); \
mfspr r22,990; /* SRR2 */ \
mfspr r23,991; /* SRR3 */ \
stw r0,GPR0(r21); \
stw r1,GPR1(r21); \
stw r2,GPR2(r21); \
stw r1,0(r21); \
mr r1,r21; /* set new kernel sp */ \
SAVE_4GPRS(3, r21);
/*
* Note: code which follows this uses cr0.eq (set if from kernel),
* r21, r22 (SRR2), and r23 (SRR3).
*/
/*
* Exception vectors.
*
@@ -293,30 +260,45 @@
#define STD_EXCEPTION(n, label, hdlr) \
. = n; \
label: \
EXCEPTION_PROLOG; \
EXCEPTION_PROLOG(SRR0, SRR1); \
lwz r3,GOT(transfer_to_handler); \
mtlr r3; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
li r20,MSR_KERNEL; \
rlwimi r20,r23,0,25,25; \
blrl ; \
blrl; \
.L_ ## label : \
.long hdlr - _start + EXC_OFF_SYS_RESET; \
.long int_return - _start + EXC_OFF_SYS_RESET
.long hdlr - _start + _START_OFFSET; \
.long int_return - _start + _START_OFFSET
#define CRIT_EXCEPTION(n, label, hdlr) \
. = n; \
label: \
EXCEPTION_PROLOG(CSRR0, CSRR1); \
lwz r3,GOT(transfer_to_handler); \
mtlr r3; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
rlwimi r20,r23,0,25,25; \
blrl; \
.L_ ## label : \
.long hdlr - _start + _START_OFFSET; \
.long crit_return - _start + _START_OFFSET
#define CRIT_EXCEPTION(n, label, hdlr) \
. = n; \
label: \
CRITICAL_EXCEPTION_PROLOG; \
lwz r3,GOT(transfer_to_handler); \
mtlr r3; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
rlwimi r20,r23,0,25,25; \
blrl ; \
.L_ ## label : \
.long hdlr - _start + EXC_OFF_SYS_RESET; \
.long crit_return - _start + EXC_OFF_SYS_RESET
#ifdef CONFIG_440
#define MCK_EXCEPTION(n, label, hdlr) \
. = n; \
label: \
EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
lwz r3,GOT(transfer_to_handler); \
mtlr r3; \
addi r3,r1,STACK_FRAME_OVERHEAD; \
li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
rlwimi r20,r23,0,25,25; \
blrl; \
.L_ ## label : \
.long hdlr - _start + _START_OFFSET; \
.long mck_return - _start + _START_OFFSET
#endif /* CONFIG_440 */
#endif /* __PPC_ASM_TMPL__ */

108
include/sata.h Normal file
View File

@@ -0,0 +1,108 @@
#if (DEBUG_SATA)
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
struct sata_ioports {
unsigned long cmd_addr;
unsigned long data_addr;
unsigned long error_addr;
unsigned long feature_addr;
unsigned long nsect_addr;
unsigned long lbal_addr;
unsigned long lbam_addr;
unsigned long lbah_addr;
unsigned long device_addr;
unsigned long status_addr;
unsigned long command_addr;
unsigned long altstatus_addr;
unsigned long ctl_addr;
unsigned long bmdma_addr;
unsigned long scr_addr;
};
struct sata_port {
unsigned char port_no; /* primary=0, secondary=1 */
struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
unsigned char ctl_reg;
unsigned char last_ctl;
unsigned char port_state; /* 1-port is available and */
/* 0-port is not available */
unsigned char dev_mask;
};
/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
#ifdef SATA_DECL /*SATA library specific declarations */
#define ata_id_has_lba48(id) ((id)[83] & (1 << 10))
#define ata_id_has_lba(id) ((id)[49] & (1 << 9))
#define ata_id_has_dma(id) ((id)[49] & (1 << 8))
#define ata_id_u32(id,n) \
(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
#define ata_id_u64(id,n) \
(((u64) (id)[(n) + 3] << 48) | \
((u64) (id)[(n) + 2] << 32) | \
((u64) (id)[(n) + 1] << 16) | \
((u64) (id)[(n) + 0]) )
#endif
#ifdef SATA_DECL /*SATA library specific declarations */
static inline void
ata_dump_id (u16 * id)
{
PRINTF ("49==0x%04x "
"53==0x%04x "
"63==0x%04x "
"64==0x%04x "
"75==0x%04x \n", id[49], id[53], id[63], id[64], id[75]);
PRINTF ("80==0x%04x "
"81==0x%04x "
"82==0x%04x "
"83==0x%04x "
"84==0x%04x \n", id[80], id[81], id[82], id[83], id[84]);
PRINTF ("88==0x%04x " "93==0x%04x\n", id[88], id[93]);
}
#endif
#ifdef SATA_DECL /*SATA library specific declarations */
int sata_bus_softreset (int num);
void sata_identify (int num, int dev);
void sata_port (struct sata_ioports *ioport);
void set_Feature_cmd (int num, int dev);
int sata_devchk (struct sata_ioports *ioaddr, int dev);
void dev_select (struct sata_ioports *ioaddr, int dev);
u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max);
u8 sata_chk_status (struct sata_ioports *ioaddr);
ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer);
ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer);
void msleep (int count);
#else
extern int sata_bus_softreset (int num);
extern void sata_identify (int num, int dev);
extern void sata_port (struct sata_ioports *ioport);
extern void set_Feature_cmd (int num, int dev);
extern ulong sata_read (int device, ulong blknr,
lbaint_t blkcnt, void * buffer);
extern ulong sata_write (int device, ulong blknr,
lbaint_t blkcnt, void * buffer);
extern void msleep (int count);
#endif
/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/
#ifdef DRV_DECL /*Driver specific declaration */
int init_sata (void);
#else
extern int init_sata (void);
#endif
#ifdef DRV_DECL /*Defines Driver Specific variables */
struct sata_port port[CFG_SATA_MAXBUS];
block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
int curr_dev = -1;
#else
extern struct sata_port port[CFG_SATA_MAXBUS];
extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES];
extern int curr_dev;
#endif