Merge branch 'for-wd-master' of git://git.denx.de/u-boot-pxa
This commit is contained in:
Wolfgang Denk
@@ -38,6 +38,7 @@
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#define CONFIG_CERF250 1 /* on Cerf PXA Board */
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#define BOARD_LATE_INIT 1
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_SYS_TEXT_BASE 0x0
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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@@ -140,15 +141,9 @@
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
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@@ -187,6 +182,9 @@
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#define CONFIG_SYS_PSSR_VAL 0x20
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#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
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#define CONFIG_SYS_CKEN 0x0
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/*
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* Memory settings
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*/
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@@ -196,6 +194,8 @@
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#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
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#define CONFIG_SYS_MDREFR_VAL 0x03CDC017
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#define CONFIG_SYS_MDMRS_VAL 0x00000000
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#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
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#define CONFIG_SYS_SXCNFG_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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@@ -39,7 +39,7 @@
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#define CONFIG_ENV_SIZE 0x4000
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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#define CONFIG_SYS_TEXT_BASE 0x0
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#define CONFIG_ENV_OVERWRITE /* override default environment */
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#define CONFIG_BOOTCOMMAND \
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@@ -39,7 +39,7 @@
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_TEXT_BASE 0x0
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/*
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* Size of malloc() pool
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*/
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@@ -126,15 +126,9 @@
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
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@@ -289,9 +283,9 @@
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* Clocks, power control and interrupts
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*/
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#define CONFIG_SYS_PSSR_VAL 0x00000020
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#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
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#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
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#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
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#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */
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#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */
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#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
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/* FIXME
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*
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@@ -319,6 +313,8 @@
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#define CONFIG_SYS_MDMRS_VAL 0x00000000
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#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */
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#endif
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#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
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#define CONFIG_SYS_SXCNFG_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
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@@ -45,7 +45,7 @@
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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#define CONFIG_SYS_TEXT_BASE 0x0
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/*
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* Hardware drivers
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*/
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@@ -458,6 +458,9 @@
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#define CONFIG_SYS_PSSR_VAL 0x20
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#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
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#define CONFIG_SYS_CKEN 0x0
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/*
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* Memory settings
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*/
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@@ -468,6 +471,8 @@
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#define CONFIG_SYS_MDCNFG_VAL 0x09a909a9
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#define CONFIG_SYS_MDREFR_VAL 0x038ff030
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#define CONFIG_SYS_MDMRS_VAL 0x00220022
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#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
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#define CONFIG_SYS_SXCNFG_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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@@ -1,267 +0,0 @@
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/*
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* Configuation settings for the Delta board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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||||
*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */
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#define CONFIG_CPU_PXA320
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#define CONFIG_DELTA 1 /* Delta board */
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/* #define CONFIG_LCD 1 */
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#ifdef CONFIG_LCD
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#define CONFIG_SHARP_LM8V31
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#endif
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#define BOARD_LATE_INIT 1
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#undef CONFIG_SKIP_RELOCATE_UBOOT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_NO_DCACHE
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/*
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||||
* Size of malloc() pool
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||||
*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
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#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* Hardware drivers
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*/
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#undef TURN_ON_ETHERNET
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#ifdef TURN_ON_ETHERNET
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# define CONFIG_DRIVER_SMC91111 1
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# define CONFIG_SMC91111_BASE 0x14000300
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# define CONFIG_SMC91111_EXT_PHY
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# define CONFIG_SMC_USE_32_BIT
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# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
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#endif
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#define CONFIG_HARD_I2C 1 /* required for DA9030 access */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
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#define CONFIG_SYS_I2C_SLAVE 1 /* I2C controllers address */
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#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */
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#define CONFIG_SYS_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */
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#define CONFIG_SYS_I2C_INIT_BOARD 1
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/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */
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#define DELTA_CHECK_KEYBD 1 /* check for keys pressed during boot */
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#define CONFIG_PREBOOT "\0"
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#ifdef DELTA_CHECK_KEYBD
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# define KEYBD_DATALEN 4 /* we have four keys */
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# define KEYBD_KP_DKIN0 0x1 /* vol+ */
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# define KEYBD_KP_DKIN1 0x2 /* vol- */
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# define KEYBD_KP_DKIN2 0x3 /* multi */
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# define KEYBD_KP_DKIN5 0x4 /* SWKEY_GN */
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#endif /* DELTA_CHECK_KEYBD */
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/*
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* select serial console configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#ifdef TURN_ON_ETHERNET
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#define CONFIG_CMD_PING
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#else
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_I2C
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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#endif
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/* USB */
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_USB_STORAGE 1
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#define CONFIG_DOS_PARTITION 1
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#include <asm/arch/pxa-regs.h> /* for OHCI_REGS_BASE */
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#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_SYS_USB_OHCI_REGS_BASE OHCI_REGS_BASE
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
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#define CONFIG_BOOTDELAY -1
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#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
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#define CONFIG_NETMASK 255.255.0.0
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#define CONFIG_IPADDR 192.168.0.21
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#define CONFIG_SERVERIP 192.168.0.250
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#define CONFIG_BOOTCOMMAND "bootm 80000"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_TIMESTAMP
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
|
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* Miscellaneous configurable options
|
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
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#else
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#endif
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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#define CONFIG_SYS_MEMTEST_START 0x80400000 /* memtest works on */
|
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#define CONFIG_SYS_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
|
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|
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#define CONFIG_SYS_HZ 1000
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|
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/* Monahans Core Frequency */
|
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#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */
|
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#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */
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|
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/* valid baudrates */
|
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
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|
||||
#ifdef CONFIG_MMC
|
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#define CONFIG_PXA_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_SYS_MMC_BASE 0xF0000000
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
|
||||
#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */
|
||||
#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */
|
||||
#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */
|
||||
#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
|
||||
|
||||
#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */
|
||||
#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */
|
||||
|
||||
#undef CONFIG_SYS_SKIP_DRAM_SCRUB
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
|
||||
|
||||
/*
|
||||
* NAND Flash
|
||||
*/
|
||||
#define CONFIG_SYS_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */
|
||||
#undef CONFIG_SYS_NAND1_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
|
||||
|
||||
/* nand timeout values */
|
||||
#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000
|
||||
#define CONFIG_SYS_NAND_OTHER_TO 100
|
||||
#define CONFIG_SYS_NAND_SENDCMD_RETRY 3
|
||||
#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */
|
||||
|
||||
/* NAND Timing Parameters (in ns) */
|
||||
#define NAND_TIMING_tCH 10
|
||||
#define NAND_TIMING_tCS 0
|
||||
#define NAND_TIMING_tWH 20
|
||||
#define NAND_TIMING_tWP 40
|
||||
|
||||
#define NAND_TIMING_tRH 20
|
||||
#define NAND_TIMING_tRP 40
|
||||
|
||||
#define NAND_TIMING_tR 11123
|
||||
#define NAND_TIMING_tWHR 100
|
||||
#define NAND_TIMING_tAR 10
|
||||
|
||||
/* NAND debugging */
|
||||
#define CONFIG_SYS_DFC_DEBUG1 /* usefull */
|
||||
#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */
|
||||
#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */
|
||||
|
||||
#define CONFIG_MTD_DEBUG
|
||||
#define CONFIG_MTD_DEBUG_VERBOSE 1
|
||||
|
||||
#define CONFIG_SYS_NO_FLASH 1
|
||||
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_OFFSET 0x40000
|
||||
#define CONFIG_ENV_OFFSET_REDUND 0x44000
|
||||
#define CONFIG_ENV_SIZE 0x4000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -40,6 +40,8 @@
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
/* for timer/console/ethernet */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
/* we will never enable dcache, because we have to setup MMU first */
|
||||
#define CONFIG_SYS_NO_DCACHE
|
||||
|
||||
@@ -347,6 +349,9 @@
|
||||
*/
|
||||
#define CONFIG_SYS_PSSR_VAL 0x37
|
||||
|
||||
#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
|
||||
#define CONFIG_SYS_CKEN 0x0
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*
|
||||
@@ -480,6 +485,9 @@
|
||||
#define CONFIG_SYS_MCIO0_VAL 0x00000000
|
||||
#define CONFIG_SYS_MCIO1_VAL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
|
||||
|
||||
/*
|
||||
#define CSB226_USER_LED0 0x00000008
|
||||
#define CSB226_USER_LED1 0x00000010
|
||||
|
||||
@@ -43,7 +43,7 @@
|
||||
#define CONFIG_MMC
|
||||
#define BOARD_LATE_INIT 1
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
/* we will never enable dcache, because we have to setup MMU first */
|
||||
@@ -202,6 +202,9 @@
|
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x20
|
||||
|
||||
#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
|
||||
#define CONFIG_SYS_CKEN 0x0
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*/
|
||||
@@ -212,6 +215,9 @@
|
||||
#define CONFIG_SYS_MDREFR_VAL 0x00018018
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
*/
|
||||
|
||||
@@ -34,6 +34,7 @@
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_MALLOC_LEN (128*1024)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \
|
||||
|
||||
@@ -36,6 +36,7 @@
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_MALLOC_LEN (128*1024)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \
|
||||
|
||||
@@ -39,6 +39,7 @@
|
||||
#undef CONFIG_LCD
|
||||
#undef CONFIG_MMC
|
||||
#define BOARD_LATE_INIT 1
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
@@ -155,15 +156,9 @@
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
|
||||
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
|
||||
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
|
||||
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
|
||||
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
|
||||
@@ -213,9 +208,9 @@
|
||||
#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x20
|
||||
#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
|
||||
#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
|
||||
#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
|
||||
#define CONFIG_SYS_CCCR 0x00000141 /* 100 MHz memory, 200 MHz CPU */
|
||||
#define CONFIG_SYS_CKEN 0x00000060 /* FFUART and STUART enabled */
|
||||
#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
@@ -231,6 +226,9 @@
|
||||
/* bits set in lowlevel_init.S */
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
*/
|
||||
|
||||
@@ -43,6 +43,7 @@
|
||||
*/
|
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
|
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
/*
|
||||
* define the following to enable debug blinks. A debug blink function
|
||||
@@ -271,7 +272,7 @@
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
|
||||
@@ -317,6 +318,9 @@
|
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x20
|
||||
|
||||
#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
|
||||
#define CONFIG_SYS_CKEN 0x0
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*/
|
||||
@@ -326,6 +330,8 @@
|
||||
#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
|
||||
#define CONFIG_SYS_MDREFR_VAL 0x0085C017
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00220022
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
|
||||
@@ -44,6 +44,7 @@
|
||||
|
||||
#define CONFIG_MMC 1
|
||||
#define BOARD_LATE_INIT 1
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
|
||||
@@ -27,6 +27,7 @@
|
||||
*/
|
||||
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
|
||||
#define CONFIG_VPAC270 1 /* Voipac PXA270 board */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
|
||||
@@ -1,199 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2003 ETC s.r.o.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Written by Peter Figuli <peposh@etc.sk>, 2003.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_PXA250 1 /* this is an PXA250 CPU */
|
||||
#define CONFIG_WEPEP250 1 /* config for wepep250 board */
|
||||
#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
|
||||
|
||||
/* we will never enable dcache, because we have to setup MMU first */
|
||||
#define CONFIG_SYS_NO_DCACHE
|
||||
|
||||
/*
|
||||
* Select serial console configuration
|
||||
*/
|
||||
#define CONFIG_PXA_SERIAL
|
||||
#define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_CONSOLE
|
||||
#undef CONFIG_CMD_LOADS
|
||||
#undef CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_SOURCE
|
||||
|
||||
|
||||
/*
|
||||
* Boot options. Setting delay to -1 stops autostart count down.
|
||||
* NOTE: Sending parameters to kernel depends on kernel version and
|
||||
* 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
|
||||
* parameters at all! Do not get confused by them so.
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY -1
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=32m console=ttyS01,115200n8"
|
||||
#define CONFIG_BOOTCOMMAND "bootm 40000"
|
||||
|
||||
|
||||
/*
|
||||
* General options for u-boot. Modify to save memory foot print
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef saves memory */
|
||||
#define CONFIG_SYS_PROMPT "WEP> " /* prompt string */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest test area */
|
||||
#define CONFIG_SYS_MEMTEST_END 0xa0800000
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Definitions related to passing arguments to kernel.
|
||||
*/
|
||||
#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
|
||||
#undef CONFIG_INITRD_TAG /* do not send initrd params */
|
||||
#undef CONFIG_VFD /* do not send framebuffer setup */
|
||||
|
||||
|
||||
/*
|
||||
* Malloc pool need to host env + 128 Kb reserve for other allocations.
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
#define CONFIG_STACKSIZE (120<<10) /* stack size */
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SDRAM Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
|
||||
#define WEP_SDRAM_1 0xa0000000 /* SDRAM bank #1 */
|
||||
#define WEP_SDRAM_1_SIZE 0x02000000 /* 32 MB ( 2 chip ) */
|
||||
#define WEP_SDRAM_2 0xa2000000 /* SDRAM bank #2 */
|
||||
#define WEP_SDRAM_2_SIZE 0x00000000 /* 0 MB */
|
||||
#define WEP_SDRAM_3 0xa8000000 /* SDRAM bank #3 */
|
||||
#define WEP_SDRAM_3_SIZE 0x00000000 /* 0 MB */
|
||||
#define WEP_SDRAM_4 0xac000000 /* SDRAM bank #4 */
|
||||
#define WEP_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
||||
|
||||
#define CONFIG_SYS_DRAM_BASE 0xa0000000
|
||||
#define CONFIG_SYS_DRAM_SIZE 0x02000000
|
||||
|
||||
/* Uncomment used SDRAM chip */
|
||||
#define WEP_SDRAM_K4S281633
|
||||
/*#define WEP_SDRAM_K4S561633*/
|
||||
|
||||
|
||||
/*
|
||||
* Configuration for FLASH memory
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
|
||||
#define WEP_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
|
||||
#define WEP_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
|
||||
#define WEP_FLASH_BANK_SIZE 0x2000000 /* size of one flash bank*/
|
||||
#define WEP_FLASH_SECT_SIZE 0x0040000 /* size of erase sector */
|
||||
#define WEP_FLASH_BASE 0x0000000 /* location of flash memory */
|
||||
#define WEP_FLASH_UNLOCK 1 /* perform hw unlock first */
|
||||
|
||||
|
||||
/* This should be defined if CFI FLASH device is present. Actually benefit
|
||||
is not so clear to me. In other words we can provide more informations
|
||||
to user, but this expects more complex flash handling we do not provide
|
||||
now.*/
|
||||
#undef CONFIG_SYS_FLASH_CFI
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE WEP_FLASH_BASE
|
||||
|
||||
/*
|
||||
* This is setting for JFFS2 support in u-boot.
|
||||
* Right now there is no gain for user, but later on booting kernel might be
|
||||
* possible. Consider using XIP kernel running from flash to save RAM
|
||||
* footprint.
|
||||
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
|
||||
*/
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0
|
||||
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
/*
|
||||
* Environment setup. Definitions of monitor location and size with
|
||||
* definition of environment setup ends up in 2 possibilities.
|
||||
* 1. Embeded environment - in u-boot code is space for environment
|
||||
* 2. Environment is read from predefined sector of flash
|
||||
* Right now we support 2. possiblity, but expecting no env placed
|
||||
* on mentioned address right now. This also needs to provide whole
|
||||
* sector for it - for us 256Kb is really waste of memory. U-boot uses
|
||||
* default env. and until kernel parameters could be sent to kernel
|
||||
* env. has no sense to us.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128kb ( 1 flash sector ) */
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR 0x20000 /* absolute address for now */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
|
||||
#define PHYS_SDRAM_1 WEP_SDRAM_1
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
|
||||
|
||||
#undef CONFIG_ENV_OVERWRITE /* env is not writable now */
|
||||
|
||||
/*
|
||||
* Well this has to be defined, but on the other hand it is used differently
|
||||
* one may expect. For instance loadb command do not cares :-)
|
||||
* So advice is - do not relay on this...
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x40000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -42,6 +42,7 @@
|
||||
*/
|
||||
#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
|
||||
#define CONFIG_XAENIAX 1 /* on a xaeniax board */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
|
||||
#define BOARD_LATE_INIT 1
|
||||
@@ -437,8 +438,9 @@
|
||||
*/
|
||||
#define CONFIG_SYS_PSSR_VAL 0x00000030
|
||||
|
||||
#define CONFIG_SYS_CKEN_VAL 0x00000080 /* */
|
||||
#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
|
||||
#define CONFIG_SYS_CKEN 0x00000080 /* */
|
||||
#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
|
||||
#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
|
||||
|
||||
|
||||
/*
|
||||
@@ -562,6 +564,9 @@
|
||||
*/
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00320032
|
||||
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
*/
|
||||
|
||||
@@ -35,6 +35,7 @@
|
||||
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
|
||||
#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
/* we will never enable dcache, because we have to setup MMU first */
|
||||
#define CONFIG_SYS_NO_DCACHE
|
||||
@@ -322,9 +323,9 @@
|
||||
* Clocks, power control and interrupts
|
||||
*/
|
||||
#define CONFIG_SYS_PSSR_VAL 0x00000030
|
||||
#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
|
||||
#define CONFIG_SYS_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */
|
||||
#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
|
||||
#define CONFIG_SYS_CCCR 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
|
||||
#define CONFIG_SYS_CKEN 0x000141ec /* FFUART and STUART enabled */
|
||||
#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
|
||||
|
||||
/* FIXME
|
||||
*
|
||||
@@ -343,6 +344,8 @@
|
||||
#define CONFIG_SYS_MDCNFG_VAL 0x000009c9
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00220022
|
||||
#define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
|
||||
|
||||
@@ -1,216 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002
|
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
|
||||
#define CONFIG_XSENGINE 1
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define BOARD_LATE_INIT 1
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
/* we will never enable dcache, because we have to setup MMU first */
|
||||
#define CONFIG_SYS_NO_DCACHE
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
|
||||
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
|
||||
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
|
||||
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
||||
#define CONFIG_SYS_DRAM_BASE 0xa0000000
|
||||
#define CONFIG_SYS_DRAM_SIZE 0x04000000
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
|
||||
|
||||
/* FLASH organization */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */
|
||||
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*/
|
||||
/* No command line, one static partition, whole device */
|
||||
#undef CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_JFFS2_DEV "nor0"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
|
||||
/* mtdparts command line support */
|
||||
/* Note: fake mtd_id used, no linux mtd map file */
|
||||
/*
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor0=xsengine-0"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
|
||||
*/
|
||||
|
||||
/* Environment settings */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/
|
||||
#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (75*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (50*CONFIG_SYS_HZ) /* Timeout for Flash Write */
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/* Hardware drivers */
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_SMC91111
|
||||
#define CONFIG_SMC91111_BASE 0x04000300
|
||||
#define CONFIG_SMC_USE_32_BIT 1
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_PXA_SERIAL
|
||||
#define CONFIG_FFUART 1
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 192.168.1.50
|
||||
#define CONFIG_SERVERIP 192.168.1.2
|
||||
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_HUSH_PARSER 1
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_MEMTEST_START 0xA0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0xA0000000 /* load kernel to this address */
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_PXA_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_SYS_MMC_BASE 0xF0000000
|
||||
#endif
|
||||
|
||||
/* Stack sizes - The stack sizes are set up in start.S using the settings below */
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/* GP set register */
|
||||
#define CONFIG_SYS_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
|
||||
#define CONFIG_SYS_GPSR1_VAL 0x00020000 /* nPWE */
|
||||
#define CONFIG_SYS_GPSR2_VAL 0x0000C000 /* CS2, CS3 */
|
||||
|
||||
/* GP clear register */
|
||||
#define CONFIG_SYS_GPCR0_VAL 0x00000000
|
||||
#define CONFIG_SYS_GPCR1_VAL 0x00000000
|
||||
#define CONFIG_SYS_GPCR2_VAL 0x00000000
|
||||
|
||||
/* GP direction register */
|
||||
#define CONFIG_SYS_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
|
||||
#define CONFIG_SYS_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
|
||||
#define CONFIG_SYS_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
|
||||
|
||||
/* GP rising edge detect register */
|
||||
#define CONFIG_SYS_GRER0_VAL 0x00000000
|
||||
#define CONFIG_SYS_GRER1_VAL 0x00000000
|
||||
#define CONFIG_SYS_GRER2_VAL 0x00000000
|
||||
|
||||
/* GP falling edge detect register */
|
||||
#define CONFIG_SYS_GFER0_VAL 0x00000000
|
||||
#define CONFIG_SYS_GFER1_VAL 0x00000000
|
||||
#define CONFIG_SYS_GFER2_VAL 0x00000000
|
||||
|
||||
/* GP alternate function register */
|
||||
#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 /* CS1 */
|
||||
#define CONFIG_SYS_GAFR0_U_VAL 0x00000010 /* RDY */
|
||||
#define CONFIG_SYS_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
|
||||
#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 /* nPWE */
|
||||
#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
|
||||
#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x00000020 /* Power manager sleep status */
|
||||
#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */
|
||||
#define CONFIG_SYS_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */
|
||||
#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
|
||||
|
||||
/* Memory settings */
|
||||
#define CONFIG_SYS_MSC0_VAL 0x25F425F0
|
||||
|
||||
/* MDCNFG: SDRAM Configuration Register */
|
||||
#define CONFIG_SYS_MDCNFG_VAL 0x000009C9
|
||||
|
||||
/* MDREFR: SDRAM Refresh Control Register */
|
||||
#define CONFIG_SYS_MDREFR_VAL 0x00018018
|
||||
|
||||
/* MDMRS: Mode Register Set Configuration Register */
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00220022
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -27,6 +27,7 @@
|
||||
*/
|
||||
#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
|
||||
#define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
#undef BOARD_LATE_INIT
|
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
Reference in New Issue
Block a user