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riscv: sifive: fu540: add SPL configuration

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Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.

SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Pragnesh Patel
2020-05-29 11:33:35 +05:30
committed by Andes
parent 7c45fc9870
commit 01cdef22ee
9 changed files with 172 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
board/sifive/fu540/Kconfig
View File

@@ -13,12 +13,20 @@ config SYS_CONFIG_NAME
default "sifive-fu540"
config SYS_TEXT_BASE
default 0x80200000 if SPL
default 0x80000000 if !RISCV_SMODE
default 0x80200000 if RISCV_SMODE
config SPL_TEXT_BASE
default 0x08000000
config SPL_OPENSBI_LOAD_ADDR
default 0x80000000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select SIFIVE_FU540
select SUPPORT_SPL
select RAM
select SPL_RAM if SPL
imply CMD_DHCP

4
board/sifive/fu540/Makefile
View File

@@ -3,3 +3,7 @@
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif

21
board/sifive/fu540/fu540.c
View File

@@ -14,6 +14,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <misc.h>
#include <spl.h>
/*
* This define is a value used for error/unknown serial.
@@ -117,3 +118,23 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_SPL
u32 spl_boot_device(void)
{
#ifdef CONFIG_SPL_MMC_SUPPORT
return BOOT_DEVICE_MMC1;
#else
puts("Unknown boot device\n");
hang();
#endif
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* boot using first FIT config */
return 0;
}
#endif

74
board/sifive/fu540/spl.c Normal file
View File

@@ -0,0 +1,74 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <init.h>
#include <spl.h>
#include <misc.h>
#include <log.h>
#include <linux/delay.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
int init_clk_and_ddr(void)
{
int ret;
ret = soc_spl_init();
if (ret) {
debug("FU540 SPL init failed: %d\n", ret);
return ret;
}
/*
* GEMGXL init VSC8541 PHY reset sequence;
* leave pull-down active for 2ms
*/
udelay(2000);
ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
if (ret) {
debug("gem_phy_reset gpio request failed: %d\n", ret);
return ret;
}
/* Set GPIO 12 (PHY NRESET) */
ret = gpio_direction_output(GEM_PHY_RESET, 1);
if (ret) {
debug("gem_phy_reset gpio direction set failed: %d\n", ret);
return ret;
}
udelay(1);
/* Reset PHY again to enter unmanaged mode */
gpio_set_value(GEM_PHY_RESET, 0);
udelay(1);
gpio_set_value(GEM_PHY_RESET, 1);
mdelay(15);
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
ret = spl_early_init();
if (ret)
panic("spl_early_init() failed: %d\n", ret);
arch_cpu_init_dm();
preloader_console_init();
ret = init_clk_and_ddr();
if (ret)
panic("init_clk_and_ddr() failed: %d\n", ret);
}