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Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

Browse Source 
Conflicts:
	lib_ppc/board.c

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
2009-03-09 00:41:48 +01:00
parent 9c2d63ec0e f70fd13e2f
commit 014c595f12
10 changed files with 258 additions and 69 deletions
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34
cpu/mpc83xx/cpu.c
View File

@@ -35,6 +35,10 @@
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#ifdef CONFIG_BOOTCOUNT_LIMIT
#include <asm/immap_qe.h>
#include <asm/io.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -399,3 +403,33 @@ int cpu_mmc_init(bd_t *bis)
return 0;
#endif
}
#ifdef CONFIG_BOOTCOUNT_LIMIT
#if !defined(CONFIG_MPC8360)
#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented"
#endif
#if !defined(CONFIG_BOOTCOUNT_ADDR)
#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long))
#endif
#include <asm/io.h>
void bootcount_store (ulong a)
{
void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
out_be32 (reg, a);
out_be32 (reg + 4, BOOTCOUNT_MAGIC);
}
ulong bootcount_load (void)
{
void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC)
return 0;
else
return in_be32 (reg);
}
#endif /* CONFIG_BOOTCOUNT_LIMIT */

18
cpu/mpc83xx/fdt.c
View File

@@ -32,6 +32,20 @@ extern void ft_qe_setup(void *blob);
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360)
#include <asm/immap_qe.h>
void fdt_fixup_muram (void *blob)
{
ulong data[2];
data[0] = 0;
data[1] = QE_MURAM_SIZE - 2 * sizeof(unsigned long);
do_fixup_by_path(blob, "/qe/muram/data-only", "reg",
data, sizeof (data), 0);
}
#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
@@ -83,4 +97,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#endif
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_BOOTCOUNT_LIMIT)
fdt_fixup_muram (blob);
#endif
}

26
cpu/mpc83xx/spd_sdram.c
View File

@@ -319,7 +319,20 @@ long int spd_sdram()
ddrc_clk = gd->mem_clk / 1000000;
effective_data_rate = 0;
if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
if (spd.cas_lat & 0x08)
caslat = 3;
else
caslat = 4;
if (ddrc_clk <= 460 && ddrc_clk > 350)
effective_data_rate = 400;
else if (ddrc_clk <=350 && ddrc_clk > 280)
effective_data_rate = 333;
else if (ddrc_clk <= 280 && ddrc_clk > 230)
effective_data_rate = 266;
else
effective_data_rate = 200;
} else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
if (ddrc_clk <= 460 && ddrc_clk > 350) {
/* DDR controller clk at 350~460 */
effective_data_rate = 400; /* 5ns */
@@ -466,6 +479,8 @@ long int spd_sdram()
} else {
twr_clk = picos_to_clk(spd.twr * 250);
twtr_clk = picos_to_clk(spd.twtr * 250);
if (twtr_clk < 2)
twtr_clk = 2;
}
/*
@@ -529,7 +544,7 @@ long int spd_sdram()
if (spd.mem_type == SPD_MEMTYPE_DDR2
&& (odt_wr_cfg || odt_rd_cfg)
&& (caslat < 4)) {
add_lat = trcd_clk - 1;
add_lat = 4 - caslat;
if ((add_lat + caslat) < 4) {
add_lat = 0;
}
@@ -566,6 +581,9 @@ long int spd_sdram()
/* Convert SPD value from quarter nanos to picos. */
trtp_clk = picos_to_clk(spd.trtp * 250);
if (trtp_clk < 2)
trtp_clk = 2;
trtp_clk += add_lat;
cke_min_clk = 3; /* By the book. */
four_act = picos_to_clk(37500); /* By the book. 1k pages? */
@@ -579,7 +597,9 @@ long int spd_sdram()
if (spd.mem_type == SPD_MEMTYPE_DDR2) {
if (effective_data_rate == 266) {
cpo = 0x4; /* READ_LAT + 1/2 */
} else if (effective_data_rate == 333 || effective_data_rate == 400) {
} else if (effective_data_rate == 333) {
cpo = 0x6; /* READ_LAT + 1 */
} else if (effective_data_rate == 400) {
cpo = 0x7; /* READ_LAT + 5/4 */
} else {
/* Automatic calibration */