484 lines
27 KiB
C
Executable File
Vendored
484 lines
27 KiB
C
Executable File
Vendored
/////////////////////////////////////////////////////////////////////////////////////////////////////////
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//
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// Name: z80io.h
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// Created: Oct 2022
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// Author(s): Philip Smart
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// Description: Z80 IO Interface
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// This file contains the declarations used in interfacing the SOM to the Z80 socket
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// and host hardware via a CPLD.
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// Credits:
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// Copyright: (c) 2019-2022 Philip Smart <philip.smart@net2net.org>
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//
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// History: Oct 2022 - Initial write of the z80 kernel driver software.
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//
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// Notes: See Makefile to enable/disable conditional components
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//
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/////////////////////////////////////////////////////////////////////////////////////////////////////////
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// This source file is free software: you can redistribute it and#or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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/////////////////////////////////////////////////////////////////////////////////////////////////////////
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#ifndef Z80IO_H
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#define Z80IO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Definitions to control compilation.
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#define INCLUDE_TEST_METHODS 1
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// CPLD Commands.
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#define CPLD_CMD_FETCH_ADDR 0x10
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#define CPLD_CMD_FETCH_ADDR_P1 0x11
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#define CPLD_CMD_FETCH_ADDR_P2 0x12
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#define CPLD_CMD_FETCH_ADDR_P3 0x13
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#define CPLD_CMD_FETCH_ADDR_P4 0x14
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#define CPLD_CMD_FETCH_ADDR_P5 0x15
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#define CPLD_CMD_FETCH_ADDR_P6 0x16
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#define CPLD_CMD_FETCH_ADDR_P7 0x17
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#define CPLD_CMD_WRITE_ADDR 0x18
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#define CPLD_CMD_WRITE_ADDR_P1 0x19
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#define CPLD_CMD_WRITE_ADDR_P2 0x1A
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#define CPLD_CMD_WRITE_ADDR_P3 0x1B
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#define CPLD_CMD_WRITE_ADDR_P4 0x1C
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#define CPLD_CMD_WRITE_ADDR_P5 0x1D
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#define CPLD_CMD_WRITE_ADDR_P6 0x1E
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#define CPLD_CMD_WRITE_ADDR_P7 0x1F
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#define CPLD_CMD_READ_ADDR 0x20
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#define CPLD_CMD_READ_ADDR_P1 0x21
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#define CPLD_CMD_READ_ADDR_P2 0x22
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#define CPLD_CMD_READ_ADDR_P3 0x23
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#define CPLD_CMD_READ_ADDR_P4 0x24
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#define CPLD_CMD_READ_ADDR_P5 0x25
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#define CPLD_CMD_READ_ADDR_P6 0x26
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#define CPLD_CMD_READ_ADDR_P7 0x27
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#define CPLD_CMD_WRITEIO_ADDR 0x28
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#define CPLD_CMD_WRITEIO_ADDR_P1 0x29
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#define CPLD_CMD_WRITEIO_ADDR_P2 0x2A
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#define CPLD_CMD_WRITEIO_ADDR_P3 0x2B
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#define CPLD_CMD_WRITEIO_ADDR_P4 0x2C
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#define CPLD_CMD_WRITEIO_ADDR_P5 0x2D
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#define CPLD_CMD_WRITEIO_ADDR_P6 0x2E
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#define CPLD_CMD_WRITEIO_ADDR_P7 0x2F
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#define CPLD_CMD_READIO_ADDR 0x30
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#define CPLD_CMD_READIO_ADDR_P1 0x31
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#define CPLD_CMD_READIO_ADDR_P2 0x32
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#define CPLD_CMD_READIO_ADDR_P3 0x33
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#define CPLD_CMD_READIO_ADDR_P4 0x34
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#define CPLD_CMD_READIO_ADDR_P5 0x35
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#define CPLD_CMD_READIO_ADDR_P6 0x36
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#define CPLD_CMD_READIO_ADDR_P7 0x37
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#define CPLD_CMD_HALT 0x50
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#define CPLD_CMD_REFRESH 0x51
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#define CPLD_CMD_SET_SIGROUP1 0xF0
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#define CPLD_CMD_SET_AUTO_REFRESH 0xF1
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#define CPLD_CMD_CLEAR_AUTO_REFRESH 0xF2
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#define CPLD_CMD_SET_SPI_LOOPBACK 0xFE
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#define CPLD_CMD_NOP1 0x00
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#define CPLD_CMD_NOP2 0xFF
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// Pad numbers for using the MHal GPIO library.
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#define PAD_Z80IO_IN_DATA_0 PAD_GPIO0
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#define PAD_Z80IO_IN_DATA_1 PAD_GPIO1
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#define PAD_Z80IO_IN_DATA_2 PAD_GPIO2
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#define PAD_Z80IO_IN_DATA_3 PAD_GPIO3
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#define PAD_Z80IO_IN_DATA_4 PAD_GPIO4
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#define PAD_Z80IO_IN_DATA_5 PAD_GPIO5
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#define PAD_Z80IO_IN_DATA_6 PAD_GPIO6
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#define PAD_Z80IO_IN_DATA_7 PAD_GPIO7
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#define PAD_SPIO_0 PAD_GPIO8
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#define PAD_SPIO_1 PAD_GPIO9
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#define PAD_SPIO_2 PAD_GPIO10
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#define PAD_SPIO_3 PAD_GPIO11
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#define PAD_Z80IO_HIGH_BYTE PAD_SAR_GPIO2 // Byte requiured, 0 = Low Byte, 1 = High Byte.
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#define PAD_Z80IO_READY PAD_GPIO12
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#define PAD_Z80IO_LTSTATE PAD_PM_IRIN // IRIN
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#define PAD_Z80IO_BUSRQ PAD_GPIO13
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#define PAD_Z80IO_BUSACK PAD_GPIO14
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#define PAD_Z80IO_INT PAD_UART0_RX // GPIO47
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#define PAD_Z80IO_NMI PAD_UART0_TX // GPIO48
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#define PAD_Z80IO_WAIT PAD_HSYNC_OUT // GPIO85
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#define PAD_Z80IO_RESET PAD_VSYNC_OUT // GPIO86
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#define PAD_Z80IO_RSV1 PAD_SATA_GPIO // GPIO90
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// Physical register addresses.
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#define PAD_Z80IO_IN_DATA_0_ADDR 0x103C00
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#define PAD_Z80IO_IN_DATA_1_ADDR 0x103C02
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#define PAD_Z80IO_IN_DATA_2_ADDR 0x103C04
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#define PAD_Z80IO_IN_DATA_3_ADDR 0x103C06
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#define PAD_Z80IO_IN_DATA_4_ADDR 0x103C08
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#define PAD_Z80IO_IN_DATA_5_ADDR 0x103C0A
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#define PAD_Z80IO_IN_DATA_6_ADDR 0x103C0C
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#define PAD_Z80IO_IN_DATA_7_ADDR 0x103C0E
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#define PAD_SPIO_0_ADDR 0x103C10
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#define PAD_SPIO_1_ADDR 0x103C12
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#define PAD_SPIO_2_ADDR 0x103C14
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#define PAD_SPIO_3_ADDR 0x103C16
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#define PAD_Z80IO_HIGH_BYTE_ADDR 0x1425
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#define PAD_Z80IO_READY_ADDR 0x103C18
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#define PAD_Z80IO_LTSTATE_ADDR 0xF28 // IRIN
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#define PAD_Z80IO_BUSRQ_ADDR 0x103C1A
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#define PAD_Z80IO_BUSACK_ADDR 0x103C1C
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#define PAD_Z80IO_INT_ADDR 0x103C30 // GPIO47
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#define PAD_Z80IO_NMI_ADDR 0x103C32 // GPIO48
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#define PAD_Z80IO_WAIT_ADDR 0x103C80 // GPIO85
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#define PAD_Z80IO_RESET_ADDR 0x103C82 // GPIO86
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#define PAD_Z80IO_RSV1_ADDR 0x103C8A // GPIO90
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#ifdef NOTNEEDED
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#define PAD_Z80IO_OUT_DATA_0 PAD_GPIO12
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#define PAD_Z80IO_OUT_DATA_1 PAD_GPIO13
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#define PAD_Z80IO_OUT_DATA_2 PAD_GPIO14
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#define PAD_Z80IO_OUT_DATA_3 PAD_UART0_RX // GPIO47
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#define PAD_Z80IO_OUT_DATA_4 PAD_UART0_TX // GPIO48
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#define PAD_Z80IO_OUT_DATA_5 PAD_HSYNC_OUT // GPIO85
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#define PAD_Z80IO_OUT_DATA_6 PAD_VSYNC_OUT // GPIO86
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#define PAD_Z80IO_OUT_DATA_7 PAD_SATA_GPIO // GPIO90
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#define PAD_Z80IO_WRITE PAD_PM_IRIN // Write data clock.
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#endif
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//-------------------------------------------------------------------------------------------------
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// The definitions below come from SigmaStar kernel drivers. No header file exists hence the
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// duplication.
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//-------------------------------------------------------------------------------------------------
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#define SUPPORT_SPI_1 0
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#define MAX_SUPPORT_BITS 16
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#define BANK_TO_ADDR32(b) (b<<9)
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#define BANK_SIZE 0x200
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#define MS_BASE_REG_RIU_PA 0x1F000000
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#define gChipBaseAddr 0xFD203C00
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#define gPmSleepBaseAddr 0xFD001C00
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#define gSarBaseAddr 0xFD002800
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#define gRIUBaseAddr 0xFD000000
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#define gMOVDMAAddr 0xFD201600
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#define gClkBaseAddr 0xFD207000
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#define gMspBaseAddr 0xfd222000
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#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)((gChipBaseAddr) + (((addr) & ~1)<<1) + (addr & 1)))
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#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)((gPmSleepBaseAddr) + (((addr) & ~1)<<1) + (addr & 1)))
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#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)((gSarBaseAddr) + (((addr) & ~1)<<1) + (addr & 1)))
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#define MHal_RIU_REG(addr) (*(volatile U8*)((gRIUBaseAddr) + (((addr) & ~1)<<1) + (addr & 1)))
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#define MSPI0_BANK_ADDR 0x1110
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#define MSPI1_BANK_ADDR 0x1111
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#define CLK__BANK_ADDR 0x1038
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#define CHIPTOP_BANK_ADDR 0x101E
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#define MOVDMA_BANK_ADDR 0x100B
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#define BASE_REG_MSPI0_ADDR MSPI0_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111000)
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#define BASE_REG_MSPI1_ADDR MSPI1_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x111100)
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#define BASE_REG_CLK_ADDR CLK__BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x103800)
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#define BASE_REG_CHIPTOP_ADDR CHIPTOP_BANK_ADDR*0x200 //GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00)
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//-------------------------------------------------------------------------------------------------
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// Hardware Register Capability
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//-------------------------------------------------------------------------------------------------
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#define MSPI_WRITE_BUF_OFFSET 0x40
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#define MSPI_READ_BUF_OFFSET 0x44
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#define MSPI_WBF_SIZE_OFFSET 0x48
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#define MSPI_RBF_SIZE_OFFSET 0x48
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// read/ write buffer size
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#define MSPI_RWSIZE_MASK 0xFF
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#define MSPI_RSIZE_BIT_OFFSET 0x8
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#define MAX_READ_BUF_SIZE 0x8
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#define MAX_WRITE_BUF_SIZE 0x8
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// CLK config
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#define MSPI_CTRL_OFFSET 0x49
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#define MSPI_CLK_CLOCK_OFFSET 0x49
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#define MSPI_CLK_CLOCK_BIT_OFFSET 0x08
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#define MSPI_CLK_CLOCK_MASK 0xFF
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#define MSPI_CLK_PHASE_MASK 0x40
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#define MSPI_CLK_PHASE_BIT_OFFSET 0x06
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#define MSPI_CLK_POLARITY_MASK 0x80
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#define MSPI_CLK_POLARITY_BIT_OFFSET 0x07
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#define MSPI_CLK_PHASE_MAX 0x1
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#define MSPI_CLK_POLARITY_MAX 0x1
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#define MSPI_CLK_CLOCK_MAX 0x7
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#define MSPI_CTRL_CPOL_LOW 0x00
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#define MSPI_CTRL_CPOL_HIGH 0x80
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#define MSPI_CTRL_CPHA_LOW 0x00
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#define MSPI_CTRL_CPHA_HIGH 0x40
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#define MSPI_CTRL_3WIRE 0x10
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#define MSPI_CTRL_INTEN 0x04
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#define MSPI_CTRL_RESET 0x02
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#define MSPI_CTRL_ENABLE_SPI 0x01
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// DC config
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#define MSPI_DC_MASK 0xFF
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#define MSPI_DC_BIT_OFFSET 0x08
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#define MSPI_DC_TR_START_OFFSET 0x4A
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#define MSPI_DC_TRSTART_MAX 0xFF
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#define MSPI_DC_TR_END_OFFSET 0x4A
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#define MSPI_DC_TREND_MAX 0xFF
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#define MSPI_DC_TB_OFFSET 0x4B
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#define MSPI_DC_TB_MAX 0xFF
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#define MSPI_DC_TRW_OFFSET 0x4B
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#define MSPI_DC_TRW_MAX 0xFF
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// Frame Config
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#define MSPI_FRAME_WBIT_OFFSET 0x4C
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#define MSPI_FRAME_RBIT_OFFSET 0x4E
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#define MSPI_FRAME_BIT_MAX 0x07
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#define MSPI_FRAME_BIT_MASK 0x07
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#define MSPI_FRAME_BIT_FIELD 0x03
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#define MSPI_LSB_FIRST_OFFSET 0x50
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#define MSPI_TRIGGER_OFFSET 0x5A
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#define MSPI_DONE_OFFSET 0x5B
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#define MSPI_DONE_CLEAR_OFFSET 0x5C
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#define MSPI_CHIP_SELECT_OFFSET 0x5F
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#define MSPI_CS1_DISABLE 0x01
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#define MSPI_CS1_ENABLE 0x00
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#define MSPI_CS2_DISABLE 0x02
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#define MSPI_CS2_ENABLE 0x00
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#define MSPI_CS3_DISABLE 0x04
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#define MSPI_CS3_ENABLE 0x00
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#define MSPI_CS4_DISABLE 0x08
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#define MSPI_CS4_ENABLE 0x00
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#define MSPI_CS5_DISABLE 0x10
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#define MSPI_CS5_ENABLE 0x00
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#define MSPI_CS6_DISABLE 0x20
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#define MSPI_CS6_ENABLE 0x00
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#define MSPI_CS7_DISABLE 0x40
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#define MSPI_CS7_ENABLE 0x00
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#define MSPI_CS8_DISABLE 0x80
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#define MSPI_CS8_ENABLE 0x00
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#define MSPI_FULL_DEPLUX_RD_CNT (0x77)
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#define MSPI_FULL_DEPLUX_RD00 (0x78)
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#define MSPI_FULL_DEPLUX_RD01 (0x78)
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#define MSPI_FULL_DEPLUX_RD02 (0x79)
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#define MSPI_FULL_DEPLUX_RD03 (0x79)
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#define MSPI_FULL_DEPLUX_RD04 (0x7a)
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#define MSPI_FULL_DEPLUX_RD05 (0x7a)
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#define MSPI_FULL_DEPLUX_RD06 (0x7b)
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#define MSPI_FULL_DEPLUX_RD07 (0x7b)
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#define MSPI_FULL_DEPLUX_RD08 (0x7c)
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#define MSPI_FULL_DEPLUX_RD09 (0x7c)
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#define MSPI_FULL_DEPLUX_RD10 (0x7d)
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#define MSPI_FULL_DEPLUX_RD11 (0x7d)
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#define MSPI_FULL_DEPLUX_RD12 (0x7e)
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#define MSPI_FULL_DEPLUX_RD13 (0x7e)
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#define MSPI_FULL_DEPLUX_RD14 (0x7f)
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#define MSPI_FULL_DEPLUX_RD15 (0x7f)
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//chip select bit map
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#define MSPI_CHIP_SELECT_MAX 0x07
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// control bit
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#define MSPI_DONE_FLAG 0x01
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#define MSPI_TRIGGER 0x01
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#define MSPI_CLEAR_DONE 0x01
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#define MSPI_INT_ENABLE 0x04
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#define MSPI_RESET 0x02
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#define MSPI_ENABLE 0x01
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// clk_mspi0
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#define MSPI0_CLK_CFG 0x33 //bit 2 ~bit 3
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#define MSPI0_CLK_108M 0x00
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#define MSPI0_CLK_54M 0x04
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#define MSPI0_CLK_12M 0x08
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#define MSPI0_CLK_MASK 0x0F
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// clk_mspi1
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#define MSPI1_CLK_CFG 0x33 //bit 10 ~bit 11
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#define MSPI1_CLK_108M 0x0000
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#define MSPI1_CLK_54M 0x0400
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#define MSPI1_CLK_12M 0x0800
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#define MSPI1_CLK_MASK 0x0F00
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// clk_mspi
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#define MSPI_CLK_CFG 0x33
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#define MSPI_SELECT_0 0x0000
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#define MSPI_SELECT_1 0x4000
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#define MSPI_CLK_MASK 0xF000
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// Clock settings
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#define MSPI_CPU_CLOCK_1_2 0x0000
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#define MSPI_CPU_CLOCK_1_4 0x0100
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#define MSPI_CPU_CLOCK_1_8 0x0200
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#define MSPI_CPU_CLOCK_1_16 0x0300
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#define MSPI_CPU_CLOCK_1_32 0x0400
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#define MSPI_CPU_CLOCK_1_64 0x0500
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#define MSPI_CPU_CLOCK_1_128 0x0600
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#define MSPI_CPU_CLOCK_1_256 0x0700
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//CHITOP 101E mspi mode select
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#define MSPI0_MODE 0x0C //bit0~bit1
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#define MSPI0_MODE_MASK 0x07
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#define MSPI1_MODE 0x0C //bit4~bit5
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#define MSPI1_MODE_MASK 0x70
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#define EJTAG_MODE 0xF
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#define EJTAG_MODE_1 0x01
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#define EJTAG_MODE_2 0x02
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#define EJTAG_MODE_3 0x03
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#define EJTAG_MODE_MASK 0x03
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//MOVDMA 100B
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#define MOV_DMA_SRC_ADDR_L 0x03
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#define MOV_DMA_SRC_ADDR_H 0x04
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#define MOV_DMA_DST_ADDR_L 0x05
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#define MOV_DMA_DST_ADDR_H 0x06
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#define MOV_DMA_BYTE_CNT_L 0x07
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#define MOV_DMA_BYTE_CNT_H 0x08
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#define DMA_MOVE0_IRQ_CLR 0x28
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#define MOV_DMA_IRQ_FINAL_STATUS 0x2A
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#define DMA_MOVE0_ENABLE 0x00
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#define DMA_RW 0x50 //0 for dma write to device, 1 for dma read from device
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#define DMA_READ 0x01
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#define DMA_WRITE 0x00
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#define DMA_DEVICE_MODE 0x51
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#define DMA_DEVICE_SEL 0x52
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//spi dma
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#define MSPI_DMA_DATA_LENGTH_L 0x30
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#define MSPI_DMA_DATA_LENGTH_H 0x31
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#define MSPI_DMA_ENABLE 0x32
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#define MSPI_DMA_RW_MODE 0x33
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#define MSPI_DMA_WRITE 0x00
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#define MSPI_DMA_READ 0x01
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#define MSTAR_SPI_TIMEOUT_MS 30000
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#define MSTAR_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA /*| SPI_CS_HIGH | SPI_NO_CS | SPI_LSB_FIRST*/)
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//-------------------------------------------------------------------------------------------------
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// Macros
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//-------------------------------------------------------------------------------------------------
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#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)((gChipBaseAddr) + (((addr) & ~1)<<1) + (addr & 1)))
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#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)((gPmSleepBaseAddr) + (((addr) & ~1)<<1) + (addr & 1)))
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#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)((gSarBaseAddr) + (((addr) & ~1)<<1) + (addr & 1)))
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#define MHal_RIU_REG(addr) (*(volatile U8*)((gRIUBaseAddr) + (((addr) & ~1)<<1) + (addr & 1)))
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#define READ_BYTE(_reg) (*(volatile u8*)(_reg))
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#define READ_WORD(_reg) (*(volatile u16*)(_reg))
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#define READ_LONG(_reg) (*(volatile u32*)(_reg))
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#define WRITE_BYTE(_reg, _val) {(*((volatile u8*)(_reg))) = (u8)(_val); }
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#define WRITE_WORD(_reg, _val) {(*((volatile u16*)(_reg))) = (u16)(_val); }
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#define WRITE_LONG(_reg, _val) {(*((volatile u32*)(_reg))) = (u32)(_val); }
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#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile u16*)(_reg))) = ((*((volatile u16*)(_reg))) & ~(_mask)) | ((u16)(_val) & (_mask)); }
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#define READ_CPLD_DATA_IN() ((MHal_RIU_REG(PAD_Z80IO_IN_DATA_7_ADDR) & 0x1) << 7 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_6_ADDR) & 0x1) << 6 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_5_ADDR) & 0x1) << 5 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_4_ADDR) & 0x1) << 4 |\
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(MHal_RIU_REG(PAD_Z80IO_IN_DATA_3_ADDR) & 0x1) << 3 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_2_ADDR) & 0x1) << 2 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_1_ADDR) & 0x1) << 1 | (MHal_RIU_REG(PAD_Z80IO_IN_DATA_0_ADDR) & 0x1))
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#define SET_CPLD_READ_DATA() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) |= 0x4;}
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#define SET_CPLD_READ_STATUS() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) &= ~0x4;}
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#define SET_CPLD_HIGH_BYTE() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) |= 0x4;}
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#define CLEAR_CPLD_HIGH_BYTE() {MHal_RIU_REG(PAD_Z80IO_HIGH_BYTE_ADDR) &= ~0x4;}
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#define CPLD_READY() (MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1)
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#define CPLD_RESET() (MHal_RIU_REG(PAD_Z80IO_RESET_ADDR) & 0x1)
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#define CPLD_LAST_TSTATE() (MHal_RIU_REG(PAD_Z80IO_LTSTATE_ADDR) & 0x4)
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#define SPI_SEND8(_d_) { uint32_t timeout = MAX_CHECK_CNT; \
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MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \
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MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 1); \
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while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\
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MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \
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MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \
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while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \
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MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \
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MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE);\
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}
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#define SPI_SEND16(_d_) { uint32_t timeout = MAX_CHECK_CNT; \
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MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \
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MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 2); \
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while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\
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MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \
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MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \
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while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \
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MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \
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MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); \
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}
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#define SPI_SEND32(_d_) { uint32_t timeout = MAX_CHECK_CNT; \
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MSPI_WRITE(MSPI_WRITE_BUF_OFFSET, (uint16_t)(_d_)); \
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MSPI_WRITE(MSPI_WRITE_BUF_OFFSET+1, (uint16_t)((_d_) >> 16)); \
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MSPI_WRITE(MSPI_WBF_SIZE_OFFSET, 4); \
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while((MHal_RIU_REG(PAD_Z80IO_READY_ADDR) & 0x1) == 0);\
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MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_ENABLE); \
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MSPI_WRITE(MSPI_TRIGGER_OFFSET, MSPI_TRIGGER); \
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while((MSPI_READ(MSPI_DONE_OFFSET) & MSPI_DONE_FLAG) == 0) { if(--timeout == 0) break; } \
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MSPI_WRITE(MSPI_CHIP_SELECT_OFFSET, MSPI_CS8_DISABLE | MSPI_CS7_DISABLE | MSPI_CS6_DISABLE | MSPI_CS5_DISABLE | MSPI_CS4_DISABLE | MSPI_CS3_DISABLE | MSPI_CS2_DISABLE | MSPI_CS1_DISABLE); \
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MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET, MSPI_CLEAR_DONE); \
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}
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// read 2 byte
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#define MSPI_READ(_reg_) READ_WORD(gMspBaseAddr + ((_reg_)<<2))
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// write 2 byte
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//#define MSPI_WRITE(_reg_, _val_) {pr_info("PDS: MSPI_WRITE(0x%x, 0x%x, 0x%x)\n", _reg_, _val_, gMspBaseAddr + ((_reg_)<<2)); WRITE_WORD(gMspBaseAddr + ((_reg_)<<2), (_val_)); }
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#define MSPI_WRITE(_reg_, _val_) WRITE_WORD(gMspBaseAddr + ((_reg_)<<2), (_val_));
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//write 2 byte mask
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//#define MSPI_WRITE_MASK(_reg_, _val_, mask) {pr_info("PDS: WRITE_LONG(0x%x, 0x%x, mask=0x%x)\n", _reg_, _val_, mask); WRITE_WORD_MASK(gMspBaseAddr + ((_reg_)<<2), (_val_), (mask)); }
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#define MSPI_WRITE_MASK(_reg_, _val_, mask) WRITE_WORD_MASK(gMspBaseAddr + ((_reg_)<<2), (_val_), (mask));
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#define CLK_READ(_reg_) READ_WORD(gClkBaseAddr + ((_reg_)<<2))
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//#define CLK_WRITE(_reg_, _val_) {pr_info("PDS: CLK_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gClkBaseAddr + ((_reg_)<<2), (_val_)); }
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#define CLK_WRITE(_reg_, _val_) WRITE_WORD(gClkBaseAddr + ((_reg_)<<2), (_val_));
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#define CHIPTOP_READ(_reg_) READ_WORD(gChipBaseAddr + ((_reg_)<<2))
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//#define CHIPTOP_WRITE(_reg_, _val_) {pr_info("PDS: CHIPTOP_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gChipBaseAddr + ((_reg_)<<2), (_val_)); }
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#define CHIPTOP_WRITE(_reg_, _val_) WRITE_WORD(gChipBaseAddr + ((_reg_)<<2), (_val_));
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#define MOVDMA_READ(_reg_) READ_WORD(gMOVDMAAddr + ((_reg_)<<2))
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//#define MOVDMA_WRITE(_reg_, _val_) {pr_info("PDS: MOVDMA_WRITE(0x%x, 0x%x)\n", _reg_, _val_); WRITE_WORD(gMOVDMAAddr + ((_reg_)<<2), (_val_)); }
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#define MOVDMA_WRITE(_reg_, _val_) WRITE_WORD(gMOVDMAAddr + ((_reg_)<<2), (_val_));
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#define _HAL_MSPI_ClearDone() MSPI_WRITE(MSPI_DONE_CLEAR_OFFSET,MSPI_CLEAR_DONE)
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#define MAX_CHECK_CNT 2000
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#define MSPI_READ_INDEX 0x0
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#define MSPI_WRITE_INDEX 0x1
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#define SPI_MIU0_BUS_BASE 0x20000000
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#define SPI_MIU1_BUS_BASE 0xFFFFFFFF
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// Function definitions.
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//
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int z80io_init(void);
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uint8_t z80io_SPI_Send8(uint8_t txData, uint8_t *rxData);
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uint8_t z80io_SPI_Send16(uint16_t txData, uint16_t *rxData);
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uint8_t z80io_SPI_Send32(uint32_t txData, uint32_t *rxData);
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#ifdef NOTNEEDED
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uint8_t z80io_PRL_Send8(uint8_t txData);
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uint8_t z680io_PRL_Send16(uint16_t txData);
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#endif
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uint8_t z80io_PRL_Read8(uint8_t dataFlag);
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uint16_t z80io_PRL_Read16(void);
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uint8_t z80io_SPI_Test(void);
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uint8_t z80io_PRL_Test(void);
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uint8_t z80io_Z80_TestMemory(void);
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extern void MHal_GPIO_Init(void);
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extern void MHal_GPIO_Pad_Set(uint8_t u8IndexGPIO);
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extern int MHal_GPIO_PadGroupMode_Set(uint32_t u32PadMode);
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extern int MHal_GPIO_PadVal_Set(uint8_t u8IndexGPIO, uint32_t u32PadMode);
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extern void MHal_GPIO_Pad_Oen(uint8_t u8IndexGPIO);
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extern void MHal_GPIO_Pad_Odn(uint8_t u8IndexGPIO);
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extern uint8_t MHal_GPIO_Pad_Level(uint8_t u8IndexGPIO);
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extern uint8_t MHal_GPIO_Pad_InOut(uint8_t u8IndexGPIO);
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extern void MHal_GPIO_Pull_High(uint8_t u8IndexGPIO);
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extern void MHal_GPIO_Pull_Low(uint8_t u8IndexGPIO);
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extern void MHal_GPIO_Set_High(uint8_t u8IndexGPIO);
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extern void MHal_GPIO_Set_Low(uint8_t u8IndexGPIO);
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extern void MHal_Enable_GPIO_INT(uint8_t u8IndexGPIO);
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extern int MHal_GPIO_To_Irq(uint8_t u8IndexGPIO);
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extern void MHal_GPIO_Set_POLARITY(uint8_t u8IndexGPIO, uint8_t reverse);
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extern void MHal_GPIO_Set_Driving(uint8_t u8IndexGPIO, uint8_t setHigh);
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extern void MHal_GPIO_PAD_32K_OUT(uint8_t u8Enable);
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#ifdef __cplusplus
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}
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#endif
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#endif // Z80IO_H
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