228 lines
14 KiB
VHDL
228 lines
14 KiB
VHDL
---------------------------------------------------------------------------------------------------------
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--
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-- Name: tzpuFusionX_Toplevel.vhd
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-- Version: Amstrad PCW-8256
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-- Created: Mar 2023
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-- Author(s): Philip Smart
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-- Description: tzpuFusionX CPLD Top Level module.
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--
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-- This module contains the basic pin definition of the CPLD<->logic needed in the
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-- project which targets the MZ-80A host.
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--
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-- Credits:
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-- Copyright: (c) 2018-23 Philip Smart <philip.smart@net2net.org>
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--
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-- History: Nov 2022 v1.0 - Initial write for the MZ-2000, adaption to the MZ-80A.
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-- Feb 2023 v1.1 - Updates, after numerous tests to try and speed up the Z80 transaction
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-- from SSD202 issuing a command to data being returned. Source now
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-- different to the MZ-700/MZ-2000 so will need back porting.
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-- Mar 2023 v1.0 - Snapshot taken from MZ-80A source for the Amstrad PCW-8256 version.
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-- Version reset to v1.0 for the Amstrad.
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--
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---------------------------------------------------------------------------------------------------------
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-- This source file is free software: you can redistribute it and-or modify
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-- it under the terms of the GNU General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- along with this program. If not, see <http:--www.gnu.org-licenses->.
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---------------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use work.tzpuFusionX_pkg.all;
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library altera;
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use altera.altera_syn_attributes.all;
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entity tzpuFusionX_PCW8256 is
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port (
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-- Z80 Address Bus
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Z80_ADDR : inout std_logic_vector(15 downto 0);
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-- Z80 Data Bus
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Z80_DATA : inout std_logic_vector(7 downto 0);
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-- Z80 Control signals.
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Z80_BUSRQn : in std_logic;
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Z80_BUSAKn : out std_logic;
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Z80_INTn : in std_logic;
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Z80_IORQn : inout std_logic;
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Z80_MREQn : inout std_logic;
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Z80_NMIn : in std_logic;
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Z80_RDn : inout std_logic;
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Z80_WRn : inout std_logic;
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Z80_RESETn : in std_logic; -- Host CPU Reset signal, also CPLD reset.
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Z80_HALTn : out std_logic;
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Z80_WAITn : in std_logic;
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Z80_M1n : inout std_logic;
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Z80_RFSHn : inout std_logic;
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-- SOM SPI
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VSOM_SPI_CSn : in std_logic; -- SPI Slave Select
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VSOM_SPI_CLK : in std_logic; -- SPI Clock
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VSOM_SPI_MOSI : in std_logic; -- SPI Master Output Slave Input
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VSOM_SPI_MISO : out std_logic; -- SPI Master Input Slave Output
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-- SOM Parallel Bus.
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VSOM_DATA_OUT : out std_logic_vector(7 downto 0); -- Address/Data bus for CPLD control registers.
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VSOM_HBYTE : in std_logic; -- Parallel Bus High (1)/Low (0) byte.
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VSOM_READY : out std_logic; -- FSM Ready (1), Busy (0)
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VSOM_LTSTATE : out std_logic; -- Last T-State in current cycle, 1 = active.
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VSOM_BUSRQ : out std_logic; -- Host device requesting Z80 Bus.
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VSOM_BUSACK : out std_logic; -- Host device granted Z80 Bus
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VSOM_INT : out std_logic; -- Z80 INT signal
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VSOM_NMI : out std_logic; -- Z80 NMI signal
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VSOM_WAIT : out std_logic; -- Z80 WAIT signal
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VSOM_RESET : out std_logic; -- Z80 RESET signal
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VSOM_RSV : out std_logic_vector(1 downto 1); -- Reserved pins.
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-- SOM Control Signals
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PM_RESET : out std_logic; -- Reset SOM
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-- VGA_Palette Control
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VGA_R : in std_logic_vector(9 downto 7); -- Signals used for detecting blank or no video output.
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VGA_G : in std_logic_vector(9 downto 7);
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VGA_B : in std_logic_vector(9 downto 8);
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-- VGA Control Signals
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VGA_PXL_CLK : in std_logic; -- VGA Pixel clock for DAC conversion.
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VGA_DISPEN : in std_logic; -- Displayed Enabled (SOM video output).
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VGA_VSYNCn : in std_logic; -- SOM VSync.
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VGA_HSYNCn : in std_logic; -- SOM HSync.
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VGA_COLR : out std_logic; -- COLR colour carrier frequency.
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VGA_CSYNCn : out std_logic; -- VGA Composite Sync.
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VGA_BLANKn : out std_logic; -- VGA Blank detected.
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-- CRT Control Signals
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MONO_PXL_CLK : out std_logic; -- Mono CRT pixel clock for DAC conversion.
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MONO_BLANKn : out std_logic; -- Mono CRT Blank (no active pixel) detection.
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MONO_CSYNCn : out std_logic; -- Mono CRT composite sync.
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MONO_RSV : out std_logic;
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-- CRT Lower Chrominance Control
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MONO_R : out std_logic_vector(2 downto 0); -- Signals to fine tune Red level of monochrome chrominance.
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MONO_G : out std_logic_vector(2 downto 0); -- Signals to fine tune Green level of monochrome chrominance.
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MONO_B : out std_logic_vector(2 downto 1); -- Signals to fine tune Blue level of monochrome chrominance.
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-- MUX Control Signals
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VIDEO_SRC : out std_logic; -- Select video source, Mainboard or SOM.
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MONO_VIDEO_SRC : out std_logic; -- Select crt video source, Mainboard or SOM.
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AUDIO_SRC_L : out std_logic; -- Select Audio Source Left Channel, Mainboard or SOM.
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AUDIO_SRC_R : out std_logic; -- Select Audio Source Right Channel, Mainboard or SOM.
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-- Mainboard Reset Signals
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MB_RESETn : in std_logic; -- Motherboard Reset pressed.
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MB_IPLn : in std_logic; -- Motherboard IPL pressed.
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-- USB Power Control
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VBUS_EN : out std_logic; -- USB Enable Power Output
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-- Clocks.
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Z80_CLK : in std_logic; -- Host CPU Clock
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CLK_50M : in std_logic -- 50MHz oscillator.
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);
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END entity;
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architecture rtl of tzpuFusionX_PCW8256 is
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begin
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cpldl512Toplevel : entity work.cpld512
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generic map (
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SPI_CLK_POLARITY => '0'
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)
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port map
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(
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-- Z80 Address Bus
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Z80_ADDR => Z80_ADDR,
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-- Z80 Data Bus
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Z80_DATA => Z80_DATA,
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-- Z80 Control signals.
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Z80_BUSRQn => Z80_BUSRQn,
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Z80_BUSAKn => Z80_BUSAKn,
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Z80_INTn => Z80_INTn,
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Z80_IORQn => Z80_IORQn,
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Z80_MREQn => Z80_MREQn,
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Z80_NMIn => Z80_NMIn,
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Z80_RDn => Z80_RDn,
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Z80_WRn => Z80_WRn,
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Z80_RESETn => Z80_RESETn,
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Z80_HALTn => Z80_HALTn,
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Z80_WAITn => Z80_WAITn,
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Z80_M1n => Z80_M1n,
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Z80_RFSHn => Z80_RFSHn,
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-- SOM SPI
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VSOM_SPI_CSn => VSOM_SPI_CSn, -- SPI Slave Select
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VSOM_SPI_CLK => VSOM_SPI_CLK, -- SPI Clock
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VSOM_SPI_MOSI => VSOM_SPI_MOSI, -- SPI Master Output Slave Input
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VSOM_SPI_MISO => VSOM_SPI_MISO, -- SPI Master Input Slave Output
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-- SOM Parallel Bus.
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VSOM_DATA_OUT => VSOM_DATA_OUT, -- Address/Data bus for CPLD control registers.
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VSOM_HBYTE => VSOM_HBYTE, -- Parallel Bus High (1)/Low (0) byte.
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VSOM_READY => VSOM_READY, -- FSM Ready (1), Busy (0)
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VSOM_LTSTATE => VSOM_LTSTATE, -- Last T-State in current cycle.
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VSOM_BUSRQ => VSOM_BUSRQ, -- Host device requesting Z80 Bus.
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VSOM_BUSACK => VSOM_BUSACK, -- Host device granted Z80 Bus
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VSOM_INT => VSOM_INT, -- Z80 INT signal
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VSOM_NMI => VSOM_NMI, -- Z80 NMI signal
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VSOM_WAIT => VSOM_WAIT, -- Z80 WAIT signal
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VSOM_RESET => VSOM_RESET, -- Z80 RESET signal
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VSOM_RSV => VSOM_RSV, -- Reserved pins.
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-- SOM Control Signals
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PM_RESET => PM_RESET, -- Reset SOM
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-- VGA_Palette Control
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VGA_R => VGA_R, -- Signals used for detecting blank or no video output.
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VGA_G => VGA_G,
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VGA_B => VGA_B,
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-- VGA Control Signals
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VGA_PXL_CLK => VGA_PXL_CLK, -- VGA Pixel clock for DAC conversion.
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VGA_DISPEN => VGA_DISPEN, -- Displayed Enabled (SOM video output).
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VGA_VSYNCn => VGA_VSYNCn, -- SOM VSync.
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VGA_HSYNCn => VGA_HSYNCn, -- SOM HSync.
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VGA_COLR => VGA_COLR, -- COLR colour carrier frequency.
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VGA_CSYNCn => VGA_CSYNCn, -- VGA Composite Sync.
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VGA_BLANKn => VGA_BLANKn, -- VGA Blank detected.
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-- CRT Control Signals
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MONO_PXL_CLK => MONO_PXL_CLK, -- Mono CRT pixel clock for DAC conversion.
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MONO_BLANKn => MONO_BLANKn, -- Mono CRT Blank (no active pixel) detection.
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MONO_CSYNCn => MONO_CSYNCn, -- Mono CRT composite sync.
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MONO_RSV => MONO_RSV,
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-- CRT Lower Chrominance Control
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MONO_R => MONO_R, -- Signals to fine tune Red level of monochrome chrominance.
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MONO_G => MONO_G, -- Signals to fine tune Green level of monochrome chrominance.
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MONO_B => MONO_B, -- Signals to fine tune Blue level of monochrome chrominance.
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-- MUX Control Signals
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VIDEO_SRC => VIDEO_SRC, -- Select video source, Mainboard or SOM.
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MONO_VIDEO_SRC => MONO_VIDEO_SRC, -- Select crt video source, Mainboard or SOM.
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AUDIO_SRC_L => AUDIO_SRC_L, -- Select Audio Source Left Channel, Mainboard or SOM.
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AUDIO_SRC_R => AUDIO_SRC_R, -- Select Audio Source Right Channel, Mainboard or SOM.
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-- Mainboard Reset Signals=> MONO_R,
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MB_RESETn => MB_RESETn, -- Motherboard Reset pressed.
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MB_IPLn => MB_IPLn, -- Motherboard IPL pressed.
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-- USB Power Control
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VBUS_EN => VBUS_EN, -- USB Enable Power Output
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-- Clocks.
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Z80_CLK => Z80_CLK, -- Host CPU Clock
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CLK_50M => CLK_50M -- 50MHz oscillator.
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);
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end architecture;
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