325 lines
21 KiB
Tcl
325 lines
21 KiB
Tcl
## Generated SDC file "tzpuFusionX.out.sdc"
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## Copyright (C) 1991-2013 Altera Corporation
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, Altera MegaCore Function License
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## Agreement, or other applicable license agreement, including,
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## without limitation, that your use is for the sole purpose of
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## programming logic devices manufactured by Altera and sold by
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## Altera or its authorized distributors. Please refer to the
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## applicable agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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## DATE "Fri Jun 26 22:10:05 2020"
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##
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## DEVICE "EPM7160STC100-10"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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# Standard mainboard clock. If using tzpuFusionX on a different host then set to the host frequency.
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create_clock -name {Z80_CLK} -period 500.000 -waveform { 0.000 250.000 } [get_ports { Z80_CLK }]
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# For 50MHz crystal.
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create_clock -name {CLK_50M} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CLK_50M }]
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# For SPI CSn
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#create_clock -name {VSOM_SPI_CSn} -period 200.000 -waveform { 160.000 40.000 } [ get_ports { VSOM_SPI_CSn }]
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# For SPI CLK
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create_clock -name {VSOM_SPI_CLK} -period 14.000 -waveform { 0.000 7.000 } [ get_ports { VSOM_SPI_CLK }]
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# For basic board with oscillator.
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#create_clock -name {CTLCLK} -period 20.000 -waveform { 0.000 10.000 } [ get_ports { CTLCLK }]
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#create_clock -name {cpld512:cpldl512Toplevel|CTLCLKi} -period 280.000 -waveform { 0.000 140.000 } [ get_keepers {cpld512:cpldl512Toplevel|CTLCLKi} ]
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##create_clock -name {Z80_CLK} -period 50.000 -waveform { 0.000 25.000 } [get_ports { CTLCLK }]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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#derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_MBSEL}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_BUSRQn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CTL_WAITn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_BUSRQn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {SYS_WAITn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_ADDR[*]}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HI_ADDR[*]}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_ADDR[*]}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_BUSACKn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_DATA[*]}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_HALTn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_IORQn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_M1n}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_MREQn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RESETn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RFSHn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_WRn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {Z80_RDn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {R_IN}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {G_IN}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {B_IN}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {COLR_IN}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CSYNC_IN}]
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##set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {CVIDEO_IN}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {HSYNC_IN}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VSYNC_IN}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 1.000 [get_ports {VZ80_DATA[*]}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSACKn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_INTn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_NMIn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}]
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#set_input_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}]
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_BUSACKn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_HALTn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_M1n}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {CTL_RFSHn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CSn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_CS2n}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_OEn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {RAM_WEn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SVCREQn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {SYS_BUSACKn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_BUSRQn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_DATA[*]}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_ADDR[*]}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HI_ADDR[*]}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RA_ADDR[*]}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_WAITn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_MREQn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_CLK}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_ADDR[*]}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_DATA[*]}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_CLK}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_MREQn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_IORQn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_RDn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_WRn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_M1n}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_RDn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VIDEO_WRn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A18_INTn_V_R}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_BUSRQn_V_G}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A16_WAITn_V_B}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A17_NMIn_V_COLR}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VWAITn_A21_V_CSYNC}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A20_RFSHn_V_HSYNC}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {VZ80_A19_HALTn_V_VSYNC}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_HALTn}]
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#set_output_delay -add_delay -clock [get_clocks {SYSCLK}] 5.000 [get_ports {Z80_RFSHn}]
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# For K64F
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#set_output_delay -add_delay -clock [get_clocks {CTLCLK}] 5.000 [get_ports {Z80_CLK}]
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# For basic board with oscillator.
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#set_output_delay -add_delay -clock [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] 5.000 [get_ports {Z80_CLK}]
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#**************************************************************
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# Set Max Delay
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#**************************************************************
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#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 30.000
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#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 30.000
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#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 30.000
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#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 30.000
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#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 30.000
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#set_max_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 30.000
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#set_max_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 30.000
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#set_max_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 30.000
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#set_max_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 30.000
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#set_max_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 30.000
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#set_max_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 30.000
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#set_max_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 30.000
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#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 40.000
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#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 40.000
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#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 40.000
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#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 30.000
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#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 30.000
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#set_max_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 30.000
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#set_max_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 30.000
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#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 30.000
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#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 30.000
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#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 30.000
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#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 30.000
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#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 30.000
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#set_max_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 30.000
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#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 45.000
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#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 30.000
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#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 30.000
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#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 30.000
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#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 45.000
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#set_max_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 30.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 45.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 50.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 45.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 60.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 45.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 40.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 40.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 40.000
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#set_max_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 60.000
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#**************************************************************
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# Set Min Delay
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#**************************************************************
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#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_HALTn} 1.000
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#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_IORQn} 1.000
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#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_M1n} 1.000
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#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RDn} 1.000
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#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_WRn} 1.000
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#set_min_delay -from [get_ports {CTL_BUSRQn}] -to {Z80_RFSHn} 1.000
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#set_min_delay -from [get_ports {VZ80_A19_HALTn_V_VSYNC}] -to {Z80_HALTn} 1.000
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#set_min_delay -from [get_ports {VZ80_IORQn}] -to {Z80_IORQn} 1.000
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#set_min_delay -from [get_ports {VZ80_MREQn}] -to {Z80_IORQn} 1.000
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#set_min_delay -from [get_ports {VZ80_M1n}] -to {Z80_M1n} 1.000
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#set_min_delay -from [get_ports {VZ80_RDn}] -to {Z80_RDn} 1.000
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#set_min_delay -from [get_ports {VZ80_WRn}] -to {Z80_WRn} 1.000
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#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_HALTn} 1.000
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#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RFSHn} 1.000
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#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_IORQn} 1.000
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#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_M1n} 1.000
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#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_RDn} 1.000
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#set_min_delay -from [get_ports {VZ80_BUSACKn}] -to {Z80_WRn} 1.000
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#set_min_delay -from [get_ports {VZ80_A20_RFSHn_V_HSYNC}] -to {Z80_RFSHn} 1.000
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#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_HALTn} 1.000
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#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_IORQn} 1.000
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#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_M1n} 1.000
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#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RDn} 1.000
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#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_WRn} 1.000
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#set_min_delay -from [get_ports {Z80_BUSACKn}] -to {Z80_RFSHn} 1.000
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#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_HALTn}] 1.000
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#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_IORQn}] 1.000
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#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_M1n}] 1.000
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#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RDn}] 1.000
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#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_RFSHn}] 1.000
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#set_min_delay -from {Z80_BUSACKn} -to [get_ports {Z80_WRn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_HALTn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_IORQn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_M1n}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RDn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_WRn}] 1.000
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#set_min_delay -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to [get_ports {Z80_RFSHn}] 1.000
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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# For K64F
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#set_false_path -from [get_clocks {CTLCLK}] -to [get_clocks {SYSCLK}]
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#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
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# For basic board with oscillator.
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#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {SYSCLK}]
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#set_false_path -from [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}] -to [get_clocks {CTLCLK}]
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#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {cpld512:cpldl512Toplevel|CTLCLKi}]
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#set_false_path -from [get_clocks {SYSCLK}] -to [get_clocks {CTLCLK}]
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# For both configurations.
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#set_false_path -from {cpld512:cpldl512Toplevel|KEY_SUBSTITUTE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
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#set_false_path -from {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
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#set_false_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
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#set_false_path -from {cpld512:cpldl512Toplevel|CPLD_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
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#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_HI_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
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#set_false_path -from {cpld512:cpldl512Toplevel|MZ80B_VRAM_LO_ADDR} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
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#set_false_path -from {cpld512:cpldl512Toplevel|MODE_VIDEO_MZ80B} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
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#set_false_path -from {cpld512:cpldl512Toplevel|GRAM_PAGE_ENABLE} -to {cpld512:cpldl512Toplevel|CTLCLK_Q}
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -setup -end 2
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#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|CTLCLK_Q} -hold -end 1
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#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2
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#set_multicycle_path -from {cpld512:cpldl512Toplevel|CTL_BUSRQni} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1
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#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -setup -end 2
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#set_multicycle_path -from {cpld512:cpldl512Toplevel|CPU_CFG_DATA[*]} -to {cpld512:cpldl512Toplevel|MEM_MODE_LATCH[*]} -hold -end 1
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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