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tzpuFusionX/CPLD/v1.0/MZ700/build/tzpuFusionX_MZ700.qsf
2022-12-01 09:35:39 +00:00

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:29:32 June 24, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# tzpuFusionX_MZ700.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY MAX7000AE
set_global_assignment -name DEVICE "EPM7512AETC144-10"
set_global_assignment -name TOP_LEVEL_ENTITY tzpuFusionX_MZ700
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:29:32 JUNE 24, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000_DEVICE_IO_STANDARD LVTTL
# Z80 Data Bus
# ============
set_location_assignment PIN_88 -to Z80_DATA[0]
set_location_assignment PIN_91 -to Z80_DATA[1]
set_location_assignment PIN_83 -to Z80_DATA[2]
set_location_assignment PIN_79 -to Z80_DATA[3]
set_location_assignment PIN_60 -to Z80_DATA[4]
set_location_assignment PIN_93 -to Z80_DATA[5]
set_location_assignment PIN_80 -to Z80_DATA[6]
set_location_assignment PIN_86 -to Z80_DATA[7]
# Z80 Control signals.
# ====================
set_location_assignment PIN_92 -to Z80_INTn
set_location_assignment PIN_96 -to Z80_NMIn
set_location_assignment PIN_97 -to Z80_HALTn
set_location_assignment PIN_98 -to Z80_MREQn
set_location_assignment PIN_99 -to Z80_IORQn
set_location_assignment PIN_110 -to Z80_RDn
set_location_assignment PIN_108 -to Z80_WRn
set_location_assignment PIN_107 -to Z80_BUSAKn
set_location_assignment PIN_106 -to Z80_WAITn
set_location_assignment PIN_103 -to Z80_BUSRQn
set_location_assignment PIN_100 -to Z80_RFSHn
set_location_assignment PIN_102 -to Z80_M1n
set_location_assignment PIN_56 -to Z80_RESETn
set_location_assignment PIN_101 -to Z80_CLK
# Z80 Address Bus
# ===============
set_location_assignment PIN_94 -to Z80_ADDR[0]
set_location_assignment PIN_90 -to Z80_ADDR[1]
set_location_assignment PIN_87 -to Z80_ADDR[2]
set_location_assignment PIN_84 -to Z80_ADDR[3]
set_location_assignment PIN_81 -to Z80_ADDR[4]
set_location_assignment PIN_78 -to Z80_ADDR[5]
set_location_assignment PIN_69 -to Z80_ADDR[6]
set_location_assignment PIN_70 -to Z80_ADDR[7]
set_location_assignment PIN_71 -to Z80_ADDR[8]
set_location_assignment PIN_68 -to Z80_ADDR[9]
set_location_assignment PIN_65 -to Z80_ADDR[10]
set_location_assignment PIN_67 -to Z80_ADDR[11]
set_location_assignment PIN_66 -to Z80_ADDR[12]
set_location_assignment PIN_63 -to Z80_ADDR[13]
set_location_assignment PIN_62 -to Z80_ADDR[14]
set_location_assignment PIN_61 -to Z80_ADDR[15]
# SOM SPI
# =======
set_location_assignment PIN_32 -to VSOM_SPI_CSn
set_location_assignment PIN_31 -to VSOM_SPI_CLK
set_location_assignment PIN_30 -to VSOM_SPI_MOSI
set_location_assignment PIN_29 -to VSOM_SPI_MISO
# SOM Parallel Bus
# ================
set_location_assignment PIN_41 -to VSOM_DATA_OUT[0]
set_location_assignment PIN_40 -to VSOM_DATA_OUT[1]
set_location_assignment PIN_39 -to VSOM_DATA_OUT[2]
set_location_assignment PIN_38 -to VSOM_DATA_OUT[3]
set_location_assignment PIN_37 -to VSOM_DATA_OUT[4]
set_location_assignment PIN_36 -to VSOM_DATA_OUT[5]
set_location_assignment PIN_35 -to VSOM_DATA_OUT[6]
set_location_assignment PIN_34 -to VSOM_DATA_OUT[7]
set_location_assignment PIN_132 -to VSOM_HBYTE
# SOM Reserved signals.
# =====================
set_location_assignment PIN_21 -to VSOM_RSV[1]
# SOM Control Signals
# ===================
set_location_assignment PIN_28 -to VSOM_READY
set_location_assignment PIN_18 -to VSOM_LTSTATE
set_location_assignment PIN_27 -to VSOM_BUSRQ
set_location_assignment PIN_26 -to VSOM_BUSACK
set_location_assignment PIN_19 -to VSOM_INT
set_location_assignment PIN_22 -to VSOM_NMI
set_location_assignment PIN_25 -to VSOM_WAIT
set_location_assignment PIN_23 -to VSOM_RESET
set_location_assignment PIN_16 -to PM_RESET
# VGA_Palette Control
# ===================
set_location_assignment PIN_133 -to VGA_R[7]
set_location_assignment PIN_137 -to VGA_R[8]
set_location_assignment PIN_140 -to VGA_R[9]
set_location_assignment PIN_134 -to VGA_G[7]
set_location_assignment PIN_138 -to VGA_G[8]
set_location_assignment PIN_141 -to VGA_G[9]
set_location_assignment PIN_136 -to VGA_B[8]
set_location_assignment PIN_139 -to VGA_B[9]
# VGA Control Signals
# ===================
set_location_assignment PIN_142 -to VGA_PXL_CLK
set_location_assignment PIN_14 -to VGA_DISPEN
set_location_assignment PIN_12 -to VGA_VSYNCn
set_location_assignment PIN_11 -to VGA_HSYNCn
set_location_assignment PIN_82 -to VGA_COLR
set_location_assignment PIN_109 -to VGA_CSYNCn
set_location_assignment PIN_143 -to VGA_BLANKn
# CRT Control Signals
# ===================
set_location_assignment PIN_15 -to MONO_PXL_CLK
set_location_assignment PIN_114 -to MONO_BLANKn
set_location_assignment PIN_113 -to MONO_CSYNCn
set_location_assignment PIN_116 -to MONO_RSV
# CRT Lower Chrominance Control
# =============================
set_location_assignment PIN_1 -to MONO_R[0]
set_location_assignment PIN_6 -to MONO_R[1]
set_location_assignment PIN_10 -to MONO_R[2]
set_location_assignment PIN_2 -to MONO_G[0]
set_location_assignment PIN_7 -to MONO_G[1]
set_location_assignment PIN_9 -to MONO_G[2]
set_location_assignment PIN_5 -to MONO_B[1]
set_location_assignment PIN_8 -to MONO_B[2]
# MUX Control Signals
# ===================
set_location_assignment PIN_72 -to VIDEO_SRC
set_location_assignment PIN_74 -to MONO_VIDEO_SRC
set_location_assignment PIN_77 -to AUDIO_SRC_L
set_location_assignment PIN_75 -to AUDIO_SRC_R
# Mainboard Reset Signals
# =======================
#set_location_assignment PIN_127 -to CPU_RESETn
set_location_assignment PIN_122 -to MB_RESETn
set_location_assignment PIN_111 -to MB_IPLn
# USB Power Control
# =================
set_location_assignment PIN_55 -to VBUS_EN
# Clocks
# ======
#set_location_assignment PIN_125 -to CPU_CLK
set_location_assignment PIN_128 -to CLK_50M
# Unused ports
# ============
#set_location_assignment PIN_42 -to
#set_location_assignment PIN_43 -to
#set_location_assignment PIN_44 -to
#set_location_assignment PIN_45 -to
#set_location_assignment PIN_112 -to
#set_location_assignment PIN_131 -to
#set_location_assignment PIN_117 -to
#set_location_assignment PIN_118 -to
#set_location_assignment PIN_119 -to
#set_location_assignment PIN_120 -to
#set_location_assignment PIN_121 -to
#set_location_assignment PIN_25 -to
#set_location_assignment PIN_53 -to
#set_location_assignment PIN_128 -to
#set_location_assignment PIN_47 -to
#set_location_assignment PIN_54 -to
#set_location_assignment PIN_127 -to
#set_location_assignment PIN_125 -to
#set_location_assignment PIN_48 -to
#set_location_assignment PIN_46 -to
#set_location_assignment PIN_49 -to
set_global_assignment -name VHDL_FILE ../tzpuFusionX_Toplevel.vhd
set_global_assignment -name VHDL_FILE ../tzpuFusionX_pkg.vhd
set_global_assignment -name VHDL_FILE ../tzpuFusionX.vhd
set_global_assignment -name SDC_FILE tzpuFusionX_MZ700_constraints.sdc
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name AUTO_RESOURCE_SHARING OFF
set_global_assignment -name PRE_MAPPING_RESYNTHESIS OFF
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING OFF
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC OFF
set_global_assignment -name AUTO_LCELL_INSERTION ON
set_global_assignment -name CDF_FILE output_files/tzpuFusionX_MZ700.cdf